KR102166924B1 - Method of operating storage device - Google Patents

Abstract

In a method of driving a storage device, based on a first volatile memory device, first valid pages included in a first block set for a plurality of nonvolatile memory devices are copied to a first latch unit. Based on the first volatile memory device, second valid pages included in the first block are copied to the second latch unit. The first valid pages copied to the first latch unit and the second valid pages copied to the second latch unit are copied to a second block set for a plurality of nonvolatile memory devices.

Description

How to drive a storage device {METHOD OF OPERATING STORAGE DEVICE}

The present invention relates to a storage device, and more particularly, to a volatile memory device and a method of driving a storage device including a nonvolatile memory device.

Recently, data storage devices such as a memory card and a solid state drive (SSD) using a memory device are widely used. The data storage device as described above has advantages in that there is no mechanical driving unit, so that stability and durability are excellent, and information access speed is very fast and power consumption is low. Such a data storage device may include a nonvolatile memory device and a volatile memory device. The nonvolatile memory device may be used as a storage medium for storing data, and the volatile memory device may be used as a buffer that processes data write/read requests, that is, a cache.

An object of the present invention is to provide a method of driving a storage device capable of effectively performing a garbage collection operation.

In order to achieve the above object, in a method of driving a storage device according to embodiments of the present invention, a first block included in a first block set for a plurality of nonvolatile memory devices is based on a first volatile memory device. The valid pages are copied to the first latch unit. Based on the first volatile memory device, second valid pages included in the first block are copied to a second latch unit. The first valid pages copied to the first latch unit and the second valid pages copied to the second latch unit are copied to a second block set for the plurality of nonvolatile memory devices.

In an embodiment, when copying the first valid pages to the first latch unit, first data stored in the first valid pages may be accumulated in the first volatile memory device. The first data accumulated in the first volatile memory device may be stored in the first latch unit.

The first data may be accumulated in the first volatile memory device via at least one third latch unit.

When copying the second valid pages to the second latch unit, second data stored in the second valid pages may be accumulated in the first volatile memory device. The second data accumulated in the first volatile memory device may be stored in the second latch unit.

When copying the first and second valid pages to the second block, a first program operation of storing the first data stored in the first latch unit in the second block may be performed. A second program operation of storing the second data copied to the second latch unit in the second block may be performed. The second program operation may be started before the first program operation is completed.

The first latch part may be included in a first nonvolatile memory device among the plurality of nonvolatile memory devices, and the second latch part may be included in a second nonvolatile memory device among the plurality of nonvolatile memory devices.

The plurality of first memory cells included in the first block are multi level memory cells (MLCs) storing a plurality of data bits, and a plurality of second memory cells included in the second block is one They may be single level memory cells (SLCs) that store bits of data.

In an embodiment, the method may further include performing an erase operation on the first block, and copying the first and second valid pages copied to the second block to a third block.

In an embodiment, copying third valid pages included in the first block to a third latch unit based on the first volatile memory device, the first block based on the first volatile memory device Copying the fourth valid pages included in a fourth latch unit, and the third valid pages copied to the third latch unit and the fourth valid pages copied to the fourth latch unit to the second It may further include the step of copying the block.

In an embodiment, the step of copying third valid pages included in the first block to a third latch unit based on a second volatile memory device, and in the first block based on the second volatile memory device Copying the included fourth valid pages to a fourth latch unit, and the third valid pages copied to the third latch unit and the fourth valid pages copied to the fourth latch unit to the second block It may further include the step of copying to.

In order to achieve the above object, in a method of driving a storage device according to embodiments of the present invention, first valid pages included in a first block set for a plurality of nonvolatile memory devices are converted to a first volatile memory device and Separate and copy at least one first latch. The second valid pages included in the first block are separated and copied to a second volatile memory device and at least one second latch. The first valid pages separated and copied from the first volatile memory device and the at least one first latch part, and the second copied separately from the second volatile memory device and the at least one second latch part Effective pages are copied to a second block set for the plurality of nonvolatile memory devices.

In one embodiment, when copying the first valid pages by separating them, first bit data corresponding to the first bits of the first data stored in the first valid pages is accumulated in the first volatile memory device. can do. The first bit data accumulated in the first volatile memory device may be stored in the at least one first latch unit. Second bit data corresponding to second bits of the first data stored in the first valid pages may be accumulated in the first volatile memory device.

When the second valid pages are separated and copied, third bit data corresponding to first bits of the second data stored in the second valid pages may be accumulated in the second volatile memory device. The third bit data accumulated in the second volatile memory device may be stored in the at least one second latch unit. Fourth bit data corresponding to second bits of second data stored in the second valid pages may be accumulated in the second volatile memory device.

In copying the first and second valid pages to the second block, a first program operation of storing the first data in the second block based on the first and second bit data may be performed. have. A second program operation of storing the second data in the second block may be performed based on the third and fourth bit data. The second program operation may be started before the first program operation is completed.

Each of the plurality of nonvolatile memory devices may be a vertical memory device in which a plurality of word lines are vertically stacked. The plurality of memory cells included in the first and second blocks may be multi level memory cells (MLCs) each storing a plurality of data bits.

In the method of driving a storage device according to the embodiments of the present invention as described above, when nonvolatile memory devices are implemented to perform an on-chip buffered program, there are fewer volatile memory devices and nonvolatile memory devices than nonvolatile memory devices. A garbage collection operation is performed using latch units inside the volatile memory devices, and when the nonvolatile memory devices are vertical memory devices and are implemented to perform HSP, the same number of volatile memory devices as the nonvolatile memory devices and Garbage collection may be performed using internal latch units. Accordingly, the performance and size of the storage device can be improved.

1 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.
2 is a block diagram illustrating an example of a computing system including a storage device driven according to the method of FIG. 1.
3 is a block diagram illustrating an example of a nonvolatile memory device included in the storage device of FIG. 2.
4 is a diagram illustrating an example of a memory cell array included in the nonvolatile memory device of FIG. 3.
5A, 5B, and 5C are flowcharts illustrating an example of steps included in the method of driving the storage device of FIG. 1.
6A, 6B, 6C, 6D, 6e, 6f, 6g, and 6H are diagrams for explaining an example of a method of driving the storage device of FIG. 1.
7A, 7B, 7C, 7D, 7E, and 7F are diagrams for explaining another example of a method of driving the storage device of FIG. 1.
8 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.
9A, 9B, 9C, and 9D are diagrams for explaining an example of a method of driving the storage device of FIG. 8.
10 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.
11A, 11B, 11C, and 11D are diagrams for describing an example of a method of driving the storage device of FIG. 10.
12 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.
13A, 13B, 13C, and 13D are diagrams for explaining an example of a method of driving the storage device of FIG. 12.
14 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.
15 is a block diagram illustrating an example of a computing system including a storage device driven according to the method of FIG. 14.
16 is a block diagram illustrating an example of a nonvolatile memory device included in the storage device of FIG. 15.
17 is a diagram illustrating an example of a memory cell array included in the nonvolatile memory device of FIG. 16.
18A, 18B, and 18C are flowcharts illustrating an example of steps included in the method of driving the storage device of FIG. 14.
19A, 19B, 19C, 19D, and 19E are diagrams for describing an example of a method of driving the storage device of FIG. 14.
20A, 20B, and 20C are flowcharts illustrating another example of steps included in the method of driving the storage device of FIG. 14.
21A, 21B, 21C, 21D, and 21E are diagrams for explaining another example of a method of driving the storage device of FIG. 14.
22 is a flowchart illustrating a method of driving a nonvolatile memory device according to example embodiments.
23 is a diagram illustrating an example in which a storage device according to embodiments of the present invention is applied to a memory card.
24 is a diagram illustrating an example in which a storage device according to embodiments of the present invention is applied to a solid state drive.
25 is a block diagram illustrating a computing system according to embodiments of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions have been exemplified only for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It should not be construed as being limited to the embodiments described in.

Since the present invention can apply various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of a set feature, number, step, action, component, part, or combination thereof, and one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. .

Meanwhile, when a certain embodiment can be implemented differently, a function or operation specified in a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be executed at the same time, or the blocks may be executed in reverse depending on a related function or operation.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

1 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.

The method of driving the storage device shown in FIG. 1 may be used to drive a storage device including at least one volatile memory device and a plurality of nonvolatile memory devices, and in particular, a storage device that cannot be used in the storage device. It can be used to perform a garbage collection operation that converts the area to be usable. For example, as described later with reference to FIGS. 23 and 24, the storage device may be any storage device such as a memory card, a solid state drive (SSD), or the like.

Referring to FIG. 1, in a method of driving a storage device according to embodiments of the present invention, first valid pages included in a first block are copied to a first latch unit based on a first volatile memory device (step S110). ). The second valid pages included in the first block are copied to the second latch unit based on the first volatile memory device (step S120). The first valid pages copied to the first latch unit and the second valid pages copied to the second latch unit are copied to a second block (step S150). The first block and the second block are set for a plurality of nonvolatile memory devices. For example, the first block may be a source block for the garbage collection operation, and the second block may be a destination block for the garbage collection operation.

As will be described later with reference to FIG. 3, each of the plurality of nonvolatile memory devices may include at least one latch unit. In an embodiment, the first and second latch units may be included in different nonvolatile memory devices. For example, the first latch unit is included in a first nonvolatile memory device among the plurality of nonvolatile memory devices, and the second latch unit is included in a second nonvolatile memory device among the plurality of nonvolatile memory devices. I can.

In addition, as will be described later with reference to FIG. 3, the memory cell array included in each of the plurality of nonvolatile memory devices includes multi level memory cells (MLCs) storing a plurality of data bits and one memory cell array. It may be implemented by including single level memory cells (SLCs) that store the data bits of. In this case, each of the plurality of nonvolatile memory devices may be implemented to perform an on-chip buffered program that stores data in MLCs via SLCs. In an embodiment, a plurality of first memory cells included in the first block may be the MLCs, and a plurality of second memory cells included in the second block may be the SLCs.

As will be described later with reference to FIGS. 6A to 6H, step S120 may be performed after step S110 is completed, and step S150 may be performed after steps S110 and S120 are completed.

In a method of driving a storage device according to embodiments of the present invention, a garbage collection operation is effectively performed using fewer volatile memory devices than nonvolatile memory devices. For example, a plurality of valid pages included in a source block are not copied to a destination block via a plurality of volatile memory devices, and the plurality of valid pages are not copied from the source block to a plurality of valid pages via at least one volatile memory device. After being sequentially copied to the internal latch units, the plurality of valid pages may be copied from the plurality of internal latch units to the target block. Accordingly, the amount of use of the volatile memory device may be reduced, so that the performance of the storage device may be improved, and the area occupied by the volatile memory device may be reduced, so that the size of the storage device may be reduced.

2 is a block diagram illustrating an example of a computing system including a storage device driven according to the method of FIG. 1.

Referring to FIG. 2, the computing system 100a includes a host 110 and a storage device 200.

The host 110 may perform various computing functions, such as performing specific calculations and/or tasks, or may execute various application programs such as an operating system (OS) and/or application. Although not shown, the host 110 may be implemented including a processor, a main memory, and a bus.

The storage device 200 includes a controller 210, at least one volatile memory device 220, and a plurality of nonvolatile memory devices 300.

The controller 210 may receive a command from the host 110 and control the operation of the storage device 200 in response to the command. Meanwhile, the controller 210 may control a garbage collection operation of the storage device 200 irrespective of a command received from the host 110. For example, the garbage collection operation may be performed when the number of invalid pages included in the plurality of nonvolatile memory devices 300 exceeds a reference number or after a predetermined reference driving time has elapsed.

At least one volatile memory device 220 acts as a write buffer temporarily storing data provided from the host 110 and/or a read cache temporarily storing data output from the plurality of nonvolatile memory devices 300 can do. For example, the volatile memory device 220 may include a dynamic random access memory (DRAM) or a static random access memory (SRAM). 2 illustrates an example in which the volatile memory device 220 is located outside the controller 210, the volatile memory device 220 may be located inside the controller 210 according to embodiments.

The plurality of nonvolatile memory devices 300 may store data provided from the host 110 or output stored data. The plurality of nonvolatile memory devices 300 may maintain stored data even when power supply is cut off. For example, each of the plurality of nonvolatile memory devices 300 includes a flash memory, a phase change random access memory (PRAM), and a ferroelectric random access memory (FRAM). , Resistive random access memory (RRAM), or ferromagnetic random access memory (MRAM).

3 is a block diagram illustrating an example of a nonvolatile memory device included in the storage device of FIG. 2.

Referring to FIG. 3, the nonvolatile memory device 300 includes a memory cell array 310, a row decoder 320, a page buffer circuit 330, a latch circuit 340, a voltage generator 350, and an input/output buffer circuit ( 360) and a control circuit 370.

The memory cell array 310 may include a plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines. As will be described later with reference to FIG. 4, each of the plurality of memory cells may be a NAND flash memory cell, and the plurality of memory cells may be arranged in a two-dimensional array structure. Meanwhile, as will be described later with reference to FIG. 17, the plurality of memory cells may be arranged in a three-dimensional vertical array structure. Further, although not shown, each of the plurality of memory cells may be a NOR flash memory cell.

In one embodiment, the memory cell array 310 may be implemented including SLCs 312 and MLCs 314. In other words, the plurality of memory cells may be SLCs 312 or MLCs 314. The nonvolatile memory device 300 may program write data in the memory cell array 310 based on an on-chip buffered program method.

The latch circuit 340 may include a plurality of latch units 342. In an embodiment, at least some of the plurality of latch units 342 may temporarily store data stored in valid pages during a garbage collection operation. In another embodiment, at least some of the plurality of latch units 342 may temporarily store one of the bits of write data to be programmed in the MLCs 314 during a program operation. In another embodiment, at least some of the plurality of latch units 342 may be used to perform an error correction function performed by an error correction circuit (not shown) and/or firmware during a read operation. 3 illustrates an example in which the plurality of latch units 342 are located outside the page buffer circuit 330, but according to the embodiment, the plurality of latch units 342 may be located inside the page buffer circuit 330. have.

The page buffer circuit 330 is connected to the plurality of bit lines and may store write data to be programmed in the memory cell array 310 or read data read from the memory cell array 310. In other words, the page buffer circuit 330 may operate as a write driver or a sense amplifier according to an operation mode of the nonvolatile memory device 300. For example, the page buffer circuit 330 may operate as a write driver in a program mode and as a sense amplifier in a read mode.

The input/output buffer circuit 360 receives write data to be programmed in the memory cell array 310 from an external controller (for example, 210 of FIG. 2), and receives the read data read from the memory cell array 310 to the external device. Can be transferred to the controller of

The row decoder 320 is connected to the plurality of word lines, and may select at least one of the plurality of word lines in response to a row address. The voltage generator 350 may generate word line voltages such as a program voltage, a program pass voltage, a verify voltage, an erase voltage, a read voltage, and a read pass voltage under the control of the control circuit 370. The control circuit 370 includes a row decoder 320, a page buffer circuit 330, a latch circuit 340, a voltage generator 350, and input/output to perform data program, erase, and read operations for the memory cell array 310. The buffer circuit 360 can be controlled.

4 is a diagram illustrating an example of a memory cell array included in the nonvolatile memory device of FIG. 3.

Referring to FIG. 4, the memory cell array 310 may include string select transistors SST, ground select transistors GST, and memory cells MC. The string select transistors SST may be connected to the bit lines BL(1), ..., BL(m), and the ground select transistors GST may be connected to the common source line CSL. The memory cells MC arranged in the same column may be arranged in series between one of the bit lines BL(1), ..., BL(m) and the common source line CSL, and are arranged in the same row. The memory cells MC may be commonly connected to one of the word lines WL(1), WL(2), WL(3), ..., WL(n-1), WL(n). . In other words, memory cells MC2 may be connected in series between the string selection transistors SST and the ground selection transistors GST, and 16 between the string selection line SSL and the ground selection line GSL, A plurality of 32 or 64 word lines may be arranged.

The string selection transistors SST are connected to the string selection line SSL and may be controlled according to the level of a voltage applied from the string selection line SSL. The ground selection transistors GST are connected to the ground selection line GSL and may be controlled according to the level of a voltage applied from the ground selection line GSL. The memory cells MC may be controlled according to the level of voltage applied to the word lines WL(1), ..., WL(n).

The nonvolatile memory device including the memory cell array 310 may be a NAND flash memory device. The NAND flash memory device may perform a program operation and a read operation in units of pages PG, and may perform an erase operation in units of blocks BLK. Meanwhile, according to an embodiment, each of the page buffers may have an even bit line and an odd bit line connected one by one. In this case, even bit lines form an even page, odd bit lines form an odd page, and a write operation for the memory cells MC may be sequentially performed alternately between even and odd pages.

5A, 5B, and 5C are flowcharts illustrating an example of steps included in the method of driving the storage device of FIG. 1. FIG. 5A shows an example of step S110 of FIG. 1, FIG. 5B shows an example of step S120 of FIG. 1, and FIG. 5C shows an example of step S150 of FIG. 1.

Referring to FIG. 5A, in copying the first valid pages to the first latch, first data stored in the first valid pages is accumulated in the first volatile memory device (step S111), and the first 1 The first data accumulated in the volatile memory device may be stored in the first latch unit (step S113).

Referring to FIG. 5B, in copying the second valid pages to the second latch, the second data stored in the second valid pages is accumulated in the first volatile memory device (step S121), and The second data accumulated in the first volatile memory device may be stored in the second latch unit (step S123).

5C, in copying the first and second valid pages to the second block, a first program operation of storing the first data stored in the first latch unit in the second block is performed, and (Step S151), a second program operation of storing the second data copied to the second latch unit in the second block may be performed (step S153), and before the first program operation is completed, the The second program operation may be started.

6A, 6B, 6C, 6D, 6e, 6f, 6g, and 6H are diagrams for explaining an example of a method of driving the storage device of FIG. 1.

Referring to FIG. 6A, the storage device may include a first volatile memory device 220a, a first nonvolatile memory device 300a, and a second nonvolatile memory device 300b. The first nonvolatile memory device 300a includes first SLCs 312a, first MLCs 314a, and a first latch unit 342a, and the second nonvolatile memory device 300b includes a second SLC. They may include 312b, second MLCs 314b, and a second latch part 342b. The first block SRCB1 for the garbage collection operation is set for the first and second MLCs 314a and 314b, and the second block DSTB1 for the garbage collection operation is the first and second SLCs. It can be set for (312a, 312b). For convenience of illustration, other components (eg, a row decoder, a page buffer circuit, an input/output buffer circuit, etc.) included in the nonvolatile memory devices 300a and 300b are omitted.

The first block SRCB1 may include valid pages VP and invalid pages IP, and the second block DSTB1 may include free pages FP. Valid pages VP include data D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22) can be stored.

When a garbage collection operation is performed based on a method of driving a storage device according to embodiments of the present invention, only valid pages VP among a plurality of pages included in the first block SRCB1 are the second block ( DSTB1) can be copied.

6B, first data D1, D2, D3, D4 stored in first valid pages among valid pages VP of a first block SRCB1 are accumulated in the first volatile memory device 220a. Can be. Referring to FIG. 6C, first data D1 to D4 accumulated in the first volatile memory device 220a may be stored in the first latch unit 342a. Although not shown, the first data D1 to D4 accumulated in the first volatile memory device 220a may be deleted after the first data D1 to D4 are stored in the first latch unit 342a.

Referring to FIG. 6D, second data D5, D6, D7, D8 stored in second valid pages among valid pages VP of the first block SRCB1 are accumulated in the first volatile memory device 220a. Can be. Referring to FIG. 6E, second data D5 to D8 accumulated in the first volatile memory device 220a may be stored in the second latch unit 342b. Although not shown, after the second data D5 to D8 are stored in the second latch unit 342b, the second data D5 to D8 accumulated in the first volatile memory device 220a may be deleted.

Referring to FIG. 6F, first and second data D1 to D8 stored in the first and second latch units 342a and 342b may be stored in the second block DSTB1. At this time, as shown in FIG. 6G, a first program operation of storing the first data D1 to D4 stored in the first latch unit 342a at time t1 in the second block DSTB1 starts, and the first A second program operation for storing the second data D5 to D8 stored in the second latch unit 342b in the second block DSTB1 at time t2 before completion of the first program operation may be started. As described above, a method in which the second program operation is started before the first program operation is completed may be referred to as an interleaving method.

Among the valid pages VP of the first block SRCB1, the operations described above with reference to FIGS. 6B to 6G may be sequentially performed for the remaining valid pages except for the first and second valid pages. Finally, as shown in FIG. 6H, all valid pages VP of the first block SRCB1 are copied to the second block DSTB1, and data D1 to D22 stored in the valid pages VP It may be sequentially stored in the second block DSTB1.

For convenience of illustration, the first and second data D1 to D8 are directly transferred from the first block SRCB1 to the first volatile memory device 220a (FIGS. 6B and 6D ), and the first volatile memory device 220a ) Is directly transmitted to the first and second latch units 342a and 342b (Figs. 6c and 6e), and is directly transmitted from the first and second latch units 342a and 342b to the second block DSTB1 ( Although shown in FIG. 6F), the above data transmission processes include a page buffer circuit (eg, 330 in FIG. 3) and/or an input/output buffer circuit (eg, 360 in FIG. 3) included in the nonvolatile memory device. It can be done using

7A, 7B, 7C, 7D, 7E, and 7F are diagrams for explaining another example of a method of driving the storage device of FIG. 1.

Referring to FIG. 7A, the storage device may include a first volatile memory device 220a, a first nonvolatile memory device 300c, and a second nonvolatile memory device 300d. The first nonvolatile memory device 300c of FIG. 7A may be substantially the same as the first nonvolatile memory device 300a of FIG. 6A except that the latch units 344a and 346a are further included. The second nonvolatile memory device 300d may be substantially the same as the second nonvolatile memory device 300b of FIG. 6A except that the latch units 344b and 346b are further included.

Referring to FIG. 7B, among the valid pages VP of the first block SRCB1, first data D1, D2, D3, and D4 stored in the first valid pages are accumulated in the first volatile memory device 220a. Can be. At this time, the first data D1 to D4 is the first volatile memory device 220a via at least one latch portion different from the first latch portion 342a, that is, the latch portions 344a, 346a, 344b, 346b. Can accumulate in As described above with reference to FIG. 3, the latch units 344a, 346a, 344b, and 346b may be used to perform an error correction function, and the first data D1 to D4 are the latch units 344a, 346a, 344b, and Errors in the first data D1 to D4 may be corrected by being accumulated in the first volatile memory device 220a via 346b. Referring to FIG. 7C, first data D1 to D4 accumulated in the first volatile memory device 220a may be stored in the first latch unit 342a.

Referring to FIG. 7D, second data D5, D6, D7, D8 stored in second valid pages among valid pages VP of the first block SRCB1 are accumulated in the first volatile memory device 220a. Can be. At this time, the second data D5 to D8 is transmitted to the first volatile memory device 220a through at least one latch portion different from the second latch portion 342b, that is, the latch portions 344a, 346a, 344b, and 346b. May be accumulated in, and accordingly, errors for the second data D5 to D8 may be corrected. Referring to FIG. 7E, second data D5 to D8 accumulated in the first volatile memory device 220a may be stored in the second latch unit 342b.

Referring to FIG. 7F, first and second data D1 to D8 stored in the first and second latch units 342a and 342b may be stored in the second block DSTB1. At this time, as described above with reference to FIG. 6G, the first program operation for the first data D1 to D4 and the second program operation for the second data D5 to D8 may be performed in an interleaving method. have. Finally, similar to the one described above with reference to FIG. 6H, all valid pages VP of the first block SRCB1 may be copied to the second block DSTB1.

8 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.

Referring to FIG. 8, in a method of driving a storage device according to embodiments of the present invention, first valid pages included in a first block are copied to a first latch unit based on a first volatile memory device (step S110). ). The second valid pages included in the first block are copied to the second latch unit based on the first volatile memory device (step S120). The first valid pages copied to the first latch unit and the second valid pages copied to the second latch unit are copied to a second block (step S150). The first block and the second block are set for a plurality of nonvolatile memory devices. Steps S110, S120, and S150 of FIG. 8 are substantially the same as steps S110, S120, and S150 of FIG. 1, respectively, and may be performed as described above with reference to FIGS. 5A, 5B, and 5C.

After copying the first and second data to the second block, an erase operation is performed on the first block (step S210), and the first and second valid pages copied to the second block are Copy to the third block (step S220). For example, the third block may be a target block for the garbage collection operation.

In an embodiment, a plurality of first memory cells included in the first block are the MLCs, a plurality of second memory cells included in the second block are the SLCs, and a plurality of first memory cells included in the third block The third memory cells may be the MLCs.

9A, 9B, 9C, and 9D are diagrams for explaining an example of a method of driving the storage device of FIG. 8.

Referring to FIG. 9A, the storage device may include a first volatile memory device 220a, a first nonvolatile memory device 300e, and a second nonvolatile memory device 300f. The first nonvolatile memory device 300e includes first SLCs 312a, first MLCs 314e, and a first latch unit 342a, and the second nonvolatile memory device 300f includes a second SLC. They may include 312b, second MLCs 314f, and a second latch part 342b. The first block SRCB1 for the garbage collection operation is set for some of the first and second MLCs 314e and 314f, and the second block DSTB1 for the garbage collection operation is first and second. It is set for the SLCs 312a and 312b, and a third block TGTB1 for the garbage collection operation may be set for some of the first and second MLCs 314e and 314f.

Referring to FIG. 9B, all valid pages VP of the first block SRCB1 are copied to the second block DSTB1 by performing an operation similar to that described above with reference to FIGS. 6A to 6H, and valid pages ( The data D1 to D22 stored in the VP) may be sequentially stored in the second block DSTB1. Meanwhile, although not shown, the nonvolatile memory devices 300e and 300f may further include at least one latch unit in addition to the latch units 342a and 342b. In this case, an operation similar to that described above with reference to FIGS. 7A to 7F By performing the operation, valid pages VP of the first block SRCB1 may be copied to the second block DSTB1.

Referring to FIG. 9C, an erase operation is performed on the first block SRCB1, and accordingly, valid pages VP and invalid pages IP included in the first block SRCB1 are free pages FP. ) Can be converted. In addition, all valid pages VP are copied from the second block DSTB1 to the third block TGTB1, and the data D1 to D22 stored in the valid pages VP are sequentially transferred to the third block TGTB1. Can be saved as

Referring to FIG. 9D, an erase operation is performed on the second block DSTB1, and accordingly, valid pages VP included in the second block DSTB1 may be converted into free pages FP.

As described above, the data D1 to D22 stored in the first block SRCB1 are converted to the second block DSTB1 based on an on-chip buffered program method of storing multi-bit data in MLCs via SLCs. The garbage collection operation for the storage device may be completed by storing the data in the third block TGTB1 and performing the erase operation on the first block SRCB1 and the second block DSTB1 via.

10 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.

Referring to FIG. 10, in a method of driving a storage device according to embodiments of the present invention, first valid pages included in a first block are copied to a first latch unit based on a first volatile memory device (step S110). ). The second valid pages included in the first block are copied to the second latch unit based on the first volatile memory device (step S120). The third valid pages included in the first block are copied to a third latch unit based on the first volatile memory device (step S130). The fourth valid pages included in the first block are copied to a fourth latch unit based on the first volatile memory device (step S140). The first block is set for a plurality of nonvolatile memory devices. Steps S110 and S120 of FIG. 10 are substantially the same as steps S110 and S120 of FIG. 1, respectively, and steps S130 and S140 of FIG. 10 may be performed similarly to steps S110 and S120 of FIG. 10.

The first to fourth valid pages are copied to the second block (step S170). Specifically, the first valid pages copied to the first latch unit and the second valid pages copied to the second latch unit are copied to the second block (step S150), and the third latch unit The copied third valid pages and the fourth valid pages copied to the fourth latch unit are copied to the second block (step S160). The second block is set for the plurality of nonvolatile memory devices. Step S150 of FIG. 10 is substantially the same as step S150 of FIG. 1, and step S160 of FIG. 10 may be performed similarly to step S150.

In an embodiment, the first to fourth latch units may be included in different nonvolatile memory devices. For example, the first latch unit is included in a first nonvolatile memory device, the second latch unit is included in a second nonvolatile memory device, and the third latch unit is included in a third nonvolatile memory device, and the The fourth latch unit may be included in the fourth nonvolatile memory device. In an embodiment, each of the plurality of nonvolatile memory devices may be implemented to perform an on-chip buffered program, and the plurality of first memory cells included in the first block are MLCs, and the second block is The included second memory cells may be SLCs.

As will be described later with reference to FIGS. 11A to 11D, step S120 may be performed after step S110 is completed, step S130 may be performed after step S120 is completed, and step S140 may be performed after step S130 is completed. After steps S110 to S140 are completed, step S170 may be performed.

11A, 11B, 11C, and 11D are diagrams for describing an example of a method of driving the storage device of FIG. 10.

Referring to FIG. 11A, the storage device includes a first volatile memory device 220b, a first nonvolatile memory device 300g, a second nonvolatile memory device 300h, a third nonvolatile memory device 300i, and a third nonvolatile memory device 300i. 4 A nonvolatile memory device 300j may be included. Each of the first to fourth nonvolatile memory devices 300g, 300h, 300i, and 300j includes one of the first to fourth SLCs 312g, 312h, 312i, and 312j, the first to fourth MLCs 314g, 314h, 314i, 314j) and one of the first to fourth latch portions 342g, 342h, 342i, and 342j. A first block (SRCB2) for the garbage collection operation is set for the first to fourth MLCs 314g, 314h, 314i, 314j, and a second block (DSTB2) for the garbage collection operation is first to It may be set for the fourth SLCs 312g, 312h, 312i, 312j.

The first block SRCB2 includes valid pages VP and invalid pages IP, the second block DSTB2 includes free pages FP, and data is included in the valid pages VP. (D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25 , D26, D27, D28, D29, D30, D31, D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42) can be stored.

Referring to FIG. 11B, among the valid pages VP of the first block SRCB2, first to fourth data D1 to D16 stored in the first to fourth valid pages are a first volatile memory device 220b. ) May be sequentially stored in the first to fourth latch portions 342g, 342h, 342i, and 342j.

For example, the first data D1 to D4 stored in the first valid pages are accumulated in the first volatile memory device 220b (1 in FIG. 11B), and accumulated in the first volatile memory device 220b. The first data D1 to D4 may be stored in the first latch unit 342g (2 in FIG. 11B). The second data D5 to D8 stored in the second valid pages are accumulated in the first volatile memory device 220b (③ in FIG. 11B), and the second data stored in the first volatile memory device 220b ( D5 to D8) may be stored in the second latch unit 342h (④ in FIG. 11B). The third data D9 to D12 stored in the third valid pages are accumulated in the first volatile memory device 220b (5 in FIG. 11B), and the third data stored in the first volatile memory device 220b ( D9 to D12) may be stored in the third latch unit 342i (6 in FIG. 11B). The fourth data D13 to D16 stored in the first valid pages are accumulated in the first volatile memory device 220b (7 in FIG. 11B), and the fourth data stored in the first volatile memory device 220b ( D13 to D16) may be stored in the fourth latch unit 342j (8 in FIG. 11B).

Referring to FIG. 11C, first to fourth data D1 to D16 stored in the first to fourth latch units 342g, 342h, 342i, and 342j may be stored in the second block DSTB2. At this time, as shown in FIG. 11D, the first program operation for the first data D1 to D4 starts at time ta, and the second data D5 to D at time tb before the first program operation is completed. The second program operation for D8) starts, and a third program operation for the third data (D9 to D12) starts at time tc before the second program operation is completed, and the third program operation is completed. Before this, the fourth program operation for the fourth data D13 to D16 may be started at time td.

Among the valid pages VP of the first block SRCB2, the operations described above with reference to FIGS. 11B to 11D may be sequentially performed for the remaining valid pages except for the first to fourth valid pages. All valid pages VP of the first block SRCB2 may be copied to the second block DSTB2.

12 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.

Referring to FIG. 12, in a method of driving a storage device according to embodiments of the present invention, first valid pages included in a first block are copied to a first latch unit based on a first volatile memory device (step S110). ). The second valid pages included in the first block are copied to the second latch unit based on the second volatile memory device (step S120a). The third valid pages included in the first block are copied to a third latch unit based on the first volatile memory device (step S130). The fourth valid pages included in the first block are copied to a fourth latch unit based on the second volatile memory device (step S140). The first block is set for a plurality of nonvolatile memory devices. Steps S110 and S130 of FIG. 12 are substantially the same as steps S110 and S130 of FIG. 10, respectively, and steps S120a and S140a of FIG. 12 are performed based on the second volatile memory device, except that steps S120 and S140 of FIG. And each may be substantially the same.

The first to fourth valid pages are copied to the second block (step S170). Specifically, the first and second valid pages are copied to the second block (step S150), and the third and fourth valid pages are copied to the second block (step S160). The second block is set for the plurality of nonvolatile memory devices. Steps S150, S160, and S170 of FIG. 12 may be substantially the same as steps S150, S160, and S170 of FIG. 10, respectively.

As will be described later with reference to FIGS. 13A to 13D, steps S110 and S120a are performed substantially simultaneously, and after steps S110 and S120a are completed, steps S130 and S140a may be performed substantially simultaneously. After steps S110 to S140a are completed, step S170 may be performed.

13A, 13B, 13C, and 13D are diagrams for explaining an example of a method of driving the storage device of FIG. 12.

Referring to FIG. 13A, the storage device includes a first volatile memory device 220b, a second volatile memory device 220c, a first nonvolatile memory device 300g, a second nonvolatile memory device 300h, and a third storage device. A nonvolatile memory device 300i and a fourth nonvolatile memory device 300j may be included. The storage device of FIG. 13A may be substantially the same as the storage device of FIG. 11A except that the second volatile memory device 220c is further included.

13B, first and second data D1 to D8 stored in first and second valid pages among valid pages VP of the first block SRCB1 are first and second volatile memories. It may be stored in the first and second latch units 342g and 342h via the devices 220b and 220c. For example, the first data D1 to D4 stored in the first valid pages are accumulated in the first volatile memory device 220b, and at the same time, the second data D5 to D8 stored in the second valid pages ) May be accumulated in the second volatile memory device 220c (1 in FIG. 13B). Thereafter, the first data D1 to D4 accumulated in the first volatile memory device 220b are stored in the first latch unit 342g, and at the same time, the second data stored in the second volatile memory device 220c ( D5 to D8) may be stored in the second latch portion 342h (2 in FIG. 13B).

13C, third and fourth data D9 to D16 stored in third and fourth valid pages among valid pages VP of a first block SRCB1 are first and second volatile memories. It may be stored in the third and fourth latch units 342i and 342j via the devices 220b and 220c. For example, third data D9 to D12 stored in the third valid pages are accumulated in the first volatile memory device 220b, and at the same time, fourth data D13 to D16 stored in the fourth valid pages ) May be accumulated in the second volatile memory device 220c (③ in FIG. 13C). Thereafter, the third data D9 to D12 accumulated in the first volatile memory device 220b are stored in the third latch unit 342i, and at the same time, the fourth data stored in the second volatile memory device 220c ( D13 to D16) may be stored in the fourth latch unit 342j (4 in FIG. 13B).

Referring to FIG. 13D, first to fourth data D1 to D16 stored in the first to fourth latch units 342g, 342h, 342i and 342j may be stored in the second block DSTB2. At this time, as described above with reference to FIG. 11D, the first program operation for the first data D1 to D4, the second program operation for the second data D5 to D8, and the third data D9 to D8. The third program operation for D12) and the fourth program operation for the fourth data D13 to D16 may be performed in an interleaving method. Finally, all valid pages VP of the first block SRCB2 may be copied to the second block DSTB2.

Meanwhile, although not shown in FIGS. 11A to 11D and 13A to 13D, the nonvolatile memory devices 300g, 300h, 300i, and 300j further include at least one latch unit in addition to the latch units 342g, 342h, 342i, and 342j. In this case, all valid pages VP of the first block SRCB2 may be copied to the second block DSTB2 by performing an operation similar to that described above with reference to FIGS. 7A to 7F. In addition, although not shown in FIGS. 11A to 11D and 13A to 13D, after all valid pages VP of the first block SRCB2 are copied to the second block DSTB2, refer to FIGS. 9A to 9D. Similar to the above, an erase operation for the first block SRCB2 and an operation for copying all valid pages VP to a third block (eg, a target block) may be further performed.

As described above, when the storage device includes one volatile memory device and two nonvolatile memory devices, the storage device includes one volatile memory device and four nonvolatile memory devices, and the storage device includes two volatile memory devices The embodiments of the present invention have been described on the basis of the case including the volatile memory devices and four nonvolatile memory devices, but the method of driving the storage device according to the embodiments of the present invention is It can be applied to any storage device including. For example, if the storage device includes one volatile memory device and three, five, or seven nonvolatile memory devices, the storage device is one, two, or three volatile memory devices and six nonvolatile memory devices. The method of driving a storage device according to embodiments of the present invention is applied to cases including devices and cases in which the storage device includes one, two, or four volatile memory devices and eight nonvolatile memory devices. I can. In addition, although embodiments of the present invention have been described based on the case where the storage device copies four valid pages at a time, the number of valid pages that the storage device copies at one time may be variously changed.

14 is a flowchart illustrating a method of driving a storage device according to embodiments of the present invention.

The method of driving the storage device illustrated in FIG. 14 may be used to drive a storage device including a plurality of volatile memory devices and a plurality of nonvolatile memory devices, and in particular, a storage device that cannot be used in the storage device. It can be used to perform a garbage collection operation that converts the area to be usable.

Referring to FIG. 14, in a method of driving a storage device according to embodiments of the present invention, first valid pages included in a first block are separated and copied to a first volatile memory device and at least one first latch ( separately copy) (step S310). The second valid pages included in the first block are copied to the second volatile memory device and at least one second latch (step S320). The first valid pages separated and copied from the first volatile memory device and the at least one first latch part, and the second copied separately from the second volatile memory device and the at least one second latch part Valid pages are copied to the second block (step S350). The first block and the second block are set for a plurality of nonvolatile memory devices. For example, the first block may be a source block for the garbage collection operation, and the second block may be a destination block for the garbage collection operation.

As will be described later with reference to FIG. 16, each of the plurality of nonvolatile memory devices may include at least one latch unit. In an embodiment, the at least one first latch unit and the at least one second latch unit may be included in different nonvolatile memory devices. For example, the at least one first latch unit is included in a first nonvolatile memory device among the plurality of nonvolatile memory devices, and the at least one second latch unit is It may be included in a nonvolatile memory device.

In addition, as will be described later with reference to FIGS. 16 and 17, each of the plurality of nonvolatile memory devices may be a vertical memory device in which a plurality of word lines included in a memory cell array are vertically stacked. In an embodiment, the plurality of memory cells included in the first and second blocks may be MLCs that store a plurality of data bits. Each of the plurality of nonvolatile memory devices separates and temporarily stores the bits of the write data to be programmed in the MLCs, and then collects the separated bits of the write data at once and stores them in the MLCs. ; HSP) can be implemented.

As described below with reference to FIGS. 19A to 19E, steps S310 and S320 may be performed substantially simultaneously, and step S350 may be performed after steps S310 and S320 are completed.

In a method of driving a storage device according to embodiments of the present invention, a garbage collection operation is effectively performed using the same number of volatile memory devices as the nonvolatile memory devices. For example, a plurality of valid pages included in a source block are not separated and copied to a larger number of volatile memory devices than a plurality of nonvolatile memory devices, and the plurality of valid pages are included in the plurality of nonvolatile memory devices. The plurality of valid pages based on the separated and copied valid pages after being separated and copied (e.g., separated by bit units and copied) into the same number of volatile memory devices and a plurality of internal latch units. Can be copied to the destination block. Accordingly, the amount of use of the volatile memory device may be reduced, so that the performance of the storage device may be improved, and the area occupied by the volatile memory device may be reduced, so that the size of the storage device may be reduced.

15 is a block diagram illustrating an example of a computing system including a storage device driven according to the method of FIG. 14.

Referring to FIG. 15, the computing system 100b includes a host 110 and a storage device 400.

The host 110 may perform various computing functions or execute various application programs, and may be substantially the same as the host 110 of FIG. 2.

The storage device 400 includes a controller 410, a plurality of volatile memory devices 420, and a plurality of nonvolatile memory devices 500.

The controller 410 controls the operation of the storage device 400 in response to a command received from the host 110, or controls the garbage collection operation of the storage device 400 regardless of the command received from the host 110. I can. The plurality of volatile memory devices 420 may operate as a write buffer for data provided from the host 110 and/or a read cache for data output from the plurality of nonvolatile memory devices 500. The plurality of nonvolatile memory devices 500 may store data provided from the host 110 or may output stored data. The controller 410, the plurality of volatile memory devices 420, and the plurality of nonvolatile memory devices 500 of FIG. 15 are each of the controller 210, at least one volatile memory device 220, and a plurality of It may be implemented similarly to the nonvolatile memory devices 300.

16 is a block diagram illustrating an example of a nonvolatile memory device included in the storage device of FIG. 15.

Referring to FIG. 16, the nonvolatile memory device 500 includes a memory cell array 510, a row decoder 520, a page buffer circuit 530, a latch circuit 540, a voltage generator 550, and an input/output buffer circuit ( 560) and a control circuit 570.

The memory cell array 510 may include a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, respectively. As will be described later with reference to FIG. 17, each of the plurality of memory cells may be a NAND flash memory cell, and the plurality of memory cells may be arranged in a 3D vertical array structure.

In an embodiment, the memory cell array 510 may be implemented including MLCs, and the nonvolatile memory device 500 may program write data into the memory cell array 510 based on the HSP method. Meanwhile, as described above with reference to FIG. 3, the memory cell array 510 may be implemented including SLCs and MLCs. In this case, the nonvolatile memory device 500 is an on-chip buffered program method and a shadow Write data may be programmed in the memory cell array 510 based on a program method or a reprogram method.

The latch circuit 540 may include a plurality of latch units 542. At least some of the plurality of latch units 542 may temporarily store part of data (eg, first bits or second bits of multi-bit data) stored in valid pages during a garbage collection operation. The page buffer circuit 530 may store write data to be programmed in the memory cell array 510 or read data read from the memory cell array 510. The input/output buffer circuit 560 may receive the write data from an external controller (eg, 410 of FIG. 15) and transmit the read data to the external controller. The row decoder 520 may select at least one of the plurality of word lines in response to a row address. The voltage generator 550 may generate word line voltages under the control of the control circuit 570. The control circuit 570 may control the row decoder 520, the page buffer circuit 530, the latch circuit 540, the voltage generator 550, and the input/output buffer circuit 560. The row decoder 520, the page buffer circuit 530, the latch circuit 540, the voltage generator 550, the input/output buffer circuit 560 and the control circuit 570 of FIG. 15 are the row decoder 320 of FIG. The page buffer circuit 330, the latch circuit 340, the voltage generator 350, the input/output buffer circuit 360, and the control circuit 370 may be implemented similarly, respectively.

17 is a diagram illustrating an example of a memory cell array included in the nonvolatile memory device of FIG. 16.

Referring to FIG. 17, a memory cell array 510 may include a plurality of strings 511 having a vertical structure. A plurality of strings 511 may be formed along the second direction D2 to form a string column, and a plurality of string columns may be formed along the third direction D3 to form a string array. The plurality of strings 511 are ground selection transistors arranged in series along the first direction D1 between the bit lines BL(1), ..., BL(m) and the common source line CSL. GSTVs), memory cells MCVs, and string select transistors SSTVs, respectively.

The ground select transistors GSTV are connected to the ground select lines GSL11, GSL12, ..., GSLi1, GSLi2, respectively, and the string select transistors SSTV are string select lines SSL11, SSL12, ..., SSLi1. , SSLi2) can be connected respectively. The memory cells MCV arranged on the same layer may be connected in common to one of the word lines WL(1), WL(2), ..., WL(n-1), and WL(n). The ground selection lines GSL11, ..., GSLi2 and the string selection lines SSL11, ..., SSLi2 extend in the second direction D2 and may be formed in plural along the third direction D3. have. The word lines WL(1), ..., WL(n) extend in the second direction D2 and may be formed in plural along the first direction D1 and the third direction D3. The bit lines BL(1), ..., BL(m) extend in the third direction D3 and may be formed in a plurality along the second direction D2. The memory cells MCV may be controlled according to the level of a voltage applied to the word lines WL(1), ..., WL(n).

Since the vertical memory device including the memory cell array 510 is a NAND flash memory device including NAND flash memory cells, a write operation and a read operation are performed on a page basis, and an erase operation is performed on a block basis.

According to an embodiment, two string selection transistors included in one string 511 are connected to one string selection line, and two ground selection transistors included in one string are connected to one ground selection line. May be. Also, according to embodiments, one string may be implemented including one string selection transistor and one ground selection transistor.

18A, 18B, and 18C are flowcharts illustrating an example of steps included in the method of driving the storage device of FIG. 14. 18A shows an example of step S310 of FIG. 14, FIG. 18B shows an example of step S320 of FIG. 14, and FIG. 18C shows an example of step S350 of FIG. 14. 18A, 18B, and 18C, the first data stored in the first valid pages and the second data stored in the second valid pages may be 2-bit data.

Referring to FIG. 18A, when the first valid pages are separated and copied, first bit data corresponding to first bits of the first data stored in the first valid pages is transferred to the first volatile memory device. Accumulate (step S311), store the first bit data accumulated in the first volatile memory device in a first latch unit (step S313), and a second bit of the first data stored in the first valid pages The second bit data corresponding to the data may be accumulated in the first volatile memory device (step S315).

Referring to FIG. 18B, when the second valid pages are separated and copied, third bit data corresponding to the first bits of the second data stored in the second valid pages is transferred to the second volatile memory device. Accumulating (step S321), storing the third bit data accumulated in the second volatile memory device in a second latch unit (step S323), and second bits of the second data stored in the second valid pages The fourth bit data corresponding to the may be accumulated in the second volatile memory device (step S325).

Referring to FIG. 18C, in copying the first and second valid pages to the second block, a first storing the first data in the second block based on the first and second bit data A second program operation of performing a program operation (step S351) and storing the second data in the second block based on the third and fourth bit data may be performed (step S353), and the The second program operation may be started before the first program operation is completed.

19A, 19B, 19C, 19D, and 19E are diagrams for describing an example of a method of driving the storage device of FIG. 14.

Referring to FIG. 19A, the storage device may include a first volatile memory device 420a, a second volatile memory device 420b, a first nonvolatile memory device 500a, and a second nonvolatile memory device 500b. I can. The first nonvolatile memory device 500a includes a first memory cell array 510a and a first latch unit 542a, and the second nonvolatile memory device 500b includes a second memory cell array 510b and a second memory cell array 510b. It may include 2 latch part 542b. The first and second memory cell arrays 510a and 510b include MLCs, and may be implemented in a three-dimensional vertical array structure as described above with reference to FIG. 17. The first block SRCB3 for the garbage collection operation is set for some of the first and second memory cell arrays 510a and 510b, and the second block DSTB3 for the garbage collection operation is first and second. It may be set for some of the second memory cell arrays 510a and 510b. For convenience of illustration, other components (eg, row decoder, page buffer circuit, input/output buffer circuit, etc.) included in the nonvolatile memory devices 500a and 500b are omitted.

The first block SRCB3 may include valid pages VP and invalid pages IP, and the second block DSTB3 may include free pages FP. Valid pages VP include 2-bit data D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22) can be stored.

Referring to FIG. 19B, a first bit corresponding to first bits of first data D1, D2, D3, D4 stored in first valid pages among valid pages VP of a first block SRCB3. Data D1', D2', D3', and D4' may be accumulated in the first volatile memory device 420a. At the same time, the third bit data D5 corresponding to the first bits of the second data D5, D6, D7, D8 stored in the second valid pages among the valid pages VP of the first block SRCB3. ', D6', D7', and D8' may be accumulated in the second volatile memory device 420b. For example, the first bit data D1' to D4' correspond to the least significant bits (LSBs) of the first data D1 to D4, and the third bit data D5' to D8' May correspond to LSBs of the second data D5 to D8.

Referring to FIG. 19C, first bit data D1' to D4' accumulated in the first volatile memory device 420a may be stored in the first latch unit 542a. At the same time, third bit data D5' to D8' accumulated in the second volatile memory device 420b may be stored in the second latch unit 542b. Although not shown, after the first and second bit data D1 ′ to D8 ′ are stored in the first and second latch units 542a and 542b, the first and second volatile memory devices 420a and 420b The first and second bit data D1' to D8' accumulated in) may be deleted.

Referring to FIG. 19D, second bit data D1", D2", D3", and D4" corresponding to second bits of the first data D1 to D4 stored in the first valid pages are first It may be accumulated in the volatile memory device 420a. At the same time, the fourth bit data D5", D6", D7", D8" corresponding to the second bits of the second data D5 to D8 stored in the second valid pages are transferred to the second volatile memory device. It can be accumulated in (420b). For example, the second bit data (D1" to D4") corresponds to the Most Significant Bits (MSBs) of the first data (D1 to D4), and the fourth bit data (D5" to D8") May correspond to MSBs of the second data D5 to D8.

Referring to FIG. 19E, first and second data D1 to D8 may be stored in a second block DSTB3. For example, by performing HSP based on the first bit data D1' to D4' and the second bit data D1" to D4", the first data D1 to D4 is transferred to the second block DSTB3. Is stored, and the second data (D5 to D8) is stored in the second block (DSTB3) by performing HSP based on the third bit data (D5' to D8') and the fourth bit data (D5" to D8") Can be. In this case, the first data D1 to D4 and the second data D5 to D8 may be programmed in an interleaving method. In other words, the second program operation for the second data D5 to D8 may be started before the first program operation for the first data D1 to D4 is completed.

Among the valid pages VP of the first block SRCB3, the operations described above with reference to FIGS. 19B to 19E may be sequentially performed for the remaining valid pages except for the first and second valid pages. Finally, all valid pages VP of the first block SRCB3 are copied to the second block DSTB3, and data D1 to D22 stored in the valid pages VP are the second block DSTB3. Can be stored in sequence.

20A, 20B, and 20C are flowcharts illustrating another example of steps included in the method of driving the storage device of FIG. 14. FIG. 20A shows another example of step S310 of FIG. 14, FIG. 20B shows another example of step S320 of FIG. 14, and FIG. 20C shows another example of step S350 of FIG. 14. 20A, 20B, and 20C, the first data stored in the first valid pages and the second data stored in the second valid pages may be 3-bit data.

Referring to FIG. 20A, when the first valid pages are separated and copied, first bit data corresponding to first bits of the first data stored in the first valid pages is transferred to the first volatile memory device. Accumulating (step S311), storing the first bit data accumulated in the first volatile memory device in a first latch unit (step S313), and storing the second bit of the first data stored in the first valid pages Accumulating second bit data corresponding to the data in the first volatile memory device (step S315), storing the second bit data accumulated in the first volatile memory device in a second latch unit (step S317), Third bit data corresponding to third bits of the first data stored in the first valid pages may be accumulated in the first volatile memory device (step S319).

Referring to FIG. 20B, when the second valid pages are separated and copied, fourth bit data corresponding to first bits of the second data stored in the second valid pages is transferred to the second volatile memory device. Accumulating (step S321a), storing the fourth bit data accumulated in the second volatile memory device in a third latch unit (step S323a), and second bits of the second data stored in the second valid pages Accumulating fifth bit data corresponding to the second volatile memory device in the second volatile memory device (step S325a), storing the fifth bit data accumulated in the second volatile memory device in a fourth latch part (step S327), the Sixth bit data corresponding to third bits of the second data stored in second valid pages may be accumulated in the second volatile memory device (step S329).

Referring to FIG. 20C, in copying the first and second valid pages to the second block, a first storing the first data in the second block based on the first to third bit data Perform a program operation (step S351a), and perform a second program operation of storing the second data in the second block based on the fourth to sixth bit data (step S353a), and The second program operation may be started before the first program operation is completed.

21A, 21B, 21C, 21D, and 21E are diagrams for explaining another example of a method of driving the storage device of FIG. 14.

Referring to FIG. 21A, the storage device may include a first volatile memory device 420a, a second volatile memory device 420b, a first nonvolatile memory device 500c, and a second nonvolatile memory device 500d. I can. The first nonvolatile memory device 500c of FIG. 21A may be substantially the same as the first nonvolatile memory device 500a of FIG. 19A except that the latch part 542c is further included, and the second nonvolatile memory device 500c of FIG. The nonvolatile memory device 500d may be substantially the same as the second nonvolatile memory device 500b of FIG. 19A except that the latch part 542d is further included.

Referring to FIG. 21B, a first bit corresponding to first bits of first data D1, D2, D3, D4 stored in first valid pages among valid pages VP of a first block SRCB3. Data (D1', D2', D3', D4') are accumulated in the first volatile memory device 420a, and at the same time, stored in the second valid pages among the valid pages VP of the first block SRCB3. Fourth bit data D5', D6', D7', D8' corresponding to the first bits of the second data D5, D6, D7, D8 may be accumulated in the second volatile memory device 420b. Yes (1) in Fig. 21B). In addition, the first bit data D1' to D4' accumulated in the first volatile memory device 420a are stored in the first latch unit 542a, and at the same time, the first bit data D1' to D4' accumulated in the second volatile memory device 420b. 4-bit data D5' to D8' may be stored in the second latch unit 542b (2 in FIG. 21B). For example, the first bit data D1' to D4' correspond to the LSBs of the first data D1 to D4, and the fourth bit data D5' to D8' are the second data D5 to D8. ) May correspond to LSBs.

Referring to FIG. 21C, second bit data D1", D2", D3", and D4" corresponding to second bits of the first data D1 to D4 stored in the first valid pages are first The fifth bit data D5", D6", D7", which are accumulated in the volatile memory device 420a and correspond to the second bits of the second data D5 to D8 stored in the second valid pages at the same time. D8") may be accumulated in the second volatile memory device 420b (③ in FIG. 21C). Also, the second bit data D1" to D4" accumulated in the first volatile memory device 420a is stored in the first latch part 542a, and at the same time, the second bit data D1" to D4" accumulated in the second volatile memory device 420b. 5-bit data D5" to D8" may be stored in the second latch part 542b (4 in FIG. 21C). For example, the second bit data (D1" to D4") corresponds to the central significant bits (CSB) of the first data (D1 to D4), and the fifth bit data (D5" to D8") May correspond to CSBs of the second data D5 to D8.

Referring to FIG. 21D, third bit data D1"', D2"', D3"', D4"' corresponding to the third bits of first data D1 to D4 stored in the first valid pages. ) Is accumulated in the first volatile memory device 420a, and at the same time, sixth bit data D5"' and D6 corresponding to the third bits of the second data D5 to D8 stored in the second valid pages. "', D7"', D8"') may be accumulated in the second volatile memory device 420b (5 in FIG. 21D). For example, the third bit data D1"' to D4"' corresponds to the MSBs of the first data D1 to D4, and the sixth bit data D5"' to D8"' is the second data. It may correspond to MSBs of (D5~D8).

Referring to FIG. 21E, first and second data D1 to D8 may be stored in a second block DSTB3. For example, HSP is performed based on the first bit data D1' to D4', the second bit data D1" to D4", and the third bit data D1"' to D4"'. Data (D1 to D4) are stored in the second block (DSTB3), and the fourth bit data (D5' to D8'), the fifth bit data (D5" to D8"), and the sixth bit data (D5"' to The second data D5 to D8 may be stored in the second block DSTB3 by performing HSP based on D8"'). In this case, the first data D1 to D4 and the second data D5 to D8 may be programmed in an interleaving method. Finally, all valid pages VP of the first block SRCB3 may be copied to the second block DSTB3.

The embodiments of the present invention have been described above based on the case where the storage device stores 2-bit data and 3-bit data, but the method of driving the storage device according to the embodiments of the present invention stores multi-bit data of 2 bits or more. It can be applied to any storage device. In addition, although embodiments of the present invention have been described based on the case where the storage device includes two volatile memory devices and two nonvolatile memory devices, the method of driving a storage device according to the embodiments of the present invention is a nonvolatile memory device. It can be applied to any storage device including the same number of volatile memory devices as the devices. In addition, although embodiments of the present invention have been described based on the case where the storage device copies four valid pages at a time, the number of valid pages that the storage device copies at one time may be variously changed.

22 is a flowchart illustrating a method of driving a nonvolatile memory device according to example embodiments.

The method of driving a nonvolatile memory device illustrated in FIG. 22 may be used to drive a nonvolatile memory device operating in association with at least one externally disposed volatile memory device. It may be used to perform a garbage collection operation on a nonvolatile memory device included in the storage device.

Referring to FIG. 22, in a method of driving a nonvolatile memory device according to embodiments of the present invention, first valid pages included in a first block of a memory cell array are stored based on an external volatile memory device. Copy to the latch part. Specifically, the first valid pages included in the first block are copied to the external volatile memory device (step S410), and the first valid pages copied to the external volatile memory device are copied to the internal first Copy to the latch unit (step S420). In addition, second valid pages included in the first block are copied to an internal second latch unit based on the external volatile memory device. Specifically, the second valid pages included in the first block are copied to the external volatile memory device (step S430), and the second valid pages copied to the external volatile memory device are copied to the second internal volatile memory device. Copy to the latch unit (step S440). The first valid pages copied to the internal first latch part and the second valid pages copied to the internal second latch part are copied to the second block of the memory cell array (step S450).

In an embodiment, the memory cell array may be implemented including a plurality of MLCs and a plurality of SLCs. In this case, the nonvolatile memory device may be implemented to perform an on-chip buffered program, and the plurality of first memory cells included in the first block are the MLCs, and the plurality of first memory cells included in the second block 2 The memory cells may be the SLCs. In this case, an erase operation may be performed on the first block, and the first and second valid pages copied to the second block may be copied to a third block.

23 is a diagram illustrating an example in which a storage device according to embodiments of the present invention is applied to a memory card.

Referring to FIG. 23, a memory card 900 includes a plurality of connection pins 910, a memory controller 920, at least one volatile memory device 930, and a plurality of nonvolatile memory devices 940.

A plurality of connection pins 910 may be connected to the host so that signals between the host (not shown) and the memory card 900 are transmitted and received. The plurality of connection pins 910 may include a clock pin, a command pin, a data pin, and/or a reset pin.

The memory controller 920 may receive data from the host and store the received data in a plurality of nonvolatile memory devices 940 via the volatile memory device 930, and a plurality of nonvolatile memory devices Data output from 940 may be provided to the host via the volatile memory device 930. Also, the memory controller 920 may perform a garbage collection operation on a plurality of nonvolatile memory devices 940 by using the volatile memory device 930.

The memory card 900 may operate according to the method of driving a storage device according to embodiments of the present invention described above with reference to FIGS. 1 to 22. Specifically, when the nonvolatile memory devices 940 are implemented to perform an on-chip buffered program, the memory card 900 includes fewer volatile memory devices 930 than the nonvolatile memory devices 940 and A garbage collection operation is performed using the latch units inside the nonvolatile memory devices 940, and when the nonvolatile memory devices 940 are vertical memory devices and are implemented to perform HSP, the memory card 900 is The garbage collection operation may be performed using the same number of volatile memory devices 930 as the nonvolatile memory devices 940 and internal latch units. Accordingly, the performance of the memory card 900 may be improved and the size of the memory card 900 may be reduced.

For example, the memory card 900 is a multimedia card (MultiMedia Card; MMC), an embedded multimedia card (eMMC), a hybrid embedded multimedia card (hybrid embedded MultiMedia Card; hybrid eMMC), and a Secure Digital (SD) card. , Micro SD card, Memory Stick, ID card, PCMCIA (Personal Computer Memory Card International Association) card, Chip Card, USB card, Smart Card, CF card (Compact Flash Card) It may be a memory card such as.

According to an embodiment, the memory card 900 includes a computer, a laptop, a cellular, a smart phone, an MP3 player, a personal digital assistant (PDA), a portable multimedia player. ; PMP), digital TV, digital camera, portable game console (portable game console) can be mounted on a host.

24 is a diagram illustrating an example in which a storage device according to embodiments of the present invention is applied to a solid state drive.

Referring to FIG. 24, the SSD 1000 includes a memory controller 1010, at least one volatile memory device 1020, and a plurality of nonvolatile memory devices 1030.

The memory controller 1010 may receive data from a host (not shown) and store the received data in a plurality of nonvolatile memory devices 1030. At least one volatile memory device 1020 may temporarily store data exchanged between the host and the plurality of nonvolatile memory devices 1030.

The SSD 1000 may operate according to the method of driving the storage device according to embodiments of the present invention described above with reference to FIGS. 1 to 22. Specifically, when the nonvolatile memory devices 1030 are implemented to perform an on-chip buffered program, the SSD 1000 includes fewer volatile memory devices 1020 and non-volatile memory devices 1020 than the nonvolatile memory devices 1030. When the nonvolatile memory devices 1030 are vertical memory devices and are implemented to perform HSP, a garbage collection operation is performed by using the latch units inside the volatile memory devices 1030, and the SSD 1000 is nonvolatile. The garbage collection operation may be performed using the same number of volatile memory devices 1020 as the memory devices 1030 and internal latch units. Accordingly, the performance of the SSD 1000 may be improved and the size of the SSD 1000 may be reduced.

According to an embodiment, the SSD 1000 may be mounted on a host such as a computer, a notebook computer, a mobile phone, a smart phone, an MP3 player, a PDA, a PMP, a digital TV, a digital camera, a portable game console, or the like.

25 is a block diagram illustrating a computing system according to embodiments of the present invention.

Referring to FIG. 25, a computing system 1100 includes a processor 1110, a memory device 1120, a user interface 1130, a bus 1150, and a storage device 1160. According to an embodiment, the computing system 1100 may further include a modem 1140 such as a baseband chipset.

The processor 1110 may perform certain calculations or tasks. For example, the processor 1110 may be a microprocessor or a central processing unit (CPU). The processor 1110 may be connected to the memory device 1120 through a bus 1150 such as an address bus, a control bus, and/or a data bus. For example, the memory device 1120 may be implemented as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. Also, the processor 1110 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. Accordingly, the processor 1110 may control the user interface 1130 including one or more input devices such as a keyboard or a mouse, and one or more output devices such as a printer or a display device. The modem 1140 may wirelessly transmit and receive data with an external device.

In the nonvolatile memory devices 1190 of the storage device 1160, data processed by the processor 1110 or data received through the modem 1140 are transmitted through the memory controller 1170 and the volatile memory device 1180. Can be saved. The storage device 1160 operates according to the driving method according to embodiments of the present invention, thereby improving performance and reducing the size.

According to an embodiment, the computing system 1100 may further include a power supply for supplying an operating voltage. In addition, according to an embodiment, the computing system 1100 may further include an application chipset, a camera image processor (CIS), and the like.

The present invention can be applied to a storage device including a volatile memory device and a nonvolatile memory device, and to any device and electronic device including the same. In particular, the present invention can be applied to memory cards, SSDs, eMMCs, universal flash storage, hybrid universal flash storage, computers, digital cameras, 3D cameras, mobile phones, PDAs, scanners, vehicle navigation, and the like.

Although described above with reference to the preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can.

Claims (10)

Copying first valid pages from a first block set for a plurality of nonvolatile memory devices to a first volatile memory device;
Copying the first valid pages from the first volatile memory device to a first latch part included in the plurality of nonvolatile memory devices;
Copying second valid pages from the first block to the first volatile memory device;
Copying the second valid pages from the first volatile memory device to a second latch part included in the plurality of nonvolatile memory devices;
Performing a first program operation in which the first valid pages are set for the plurality of nonvolatile memory devices by the first latch unit and are written to a second block different from the first block; And
And performing a second program operation of writing the second valid pages to the second block by the second latch unit,
The second program operation is started before the first program operation is completed. delete delete delete The method of claim 1,
The plurality of first memory cells included in the first block are multi level memory cells (MLCs) storing a plurality of data bits, and a plurality of second memory cells included in the second block is one A method of driving a storage device, characterized in that they are single level memory cells (SLCs) that store bits of data. The method of claim 1,
Performing an erase operation on the first block; And
And copying the first and second valid pages written in the second block to a third block that is set for the plurality of nonvolatile memory devices and is different from the first and second blocks. A method of driving a storage device, characterized in that. The method of claim 1,
Copying third valid pages from the first block to a second volatile memory device;
Copying the third valid pages from the second volatile memory device to a third latch part included in the plurality of nonvolatile memory devices;
Copying fourth valid pages from the first block to the second volatile memory device;
Copying the fourth valid pages from the second volatile memory device to a fourth latch part included in the plurality of nonvolatile memory devices;
Copying the third valid pages from the third latch unit to the second block; And
And copying the fourth valid pages from the fourth latch unit to the second block. Copying first valid pages from a first block set for a plurality of nonvolatile memory devices to a first volatile memory device;
Copying the first valid pages from the first volatile memory device to a first latch part included in the plurality of nonvolatile memory devices;
Copying second valid pages from the first block to a second volatile memory device;
Copying the second valid pages from the second volatile memory device to a second latch part included in the plurality of nonvolatile memory devices;
Performing a first program operation in which the first valid pages are set for the plurality of nonvolatile memory devices by the first latch unit and are written to a second block different from the first block; And
And performing a second program operation of writing the second valid pages to the second block by the second latch unit,
The second program operation is started before the first program operation is completed. delete The method of claim 8,
Each of the plurality of nonvolatile memory devices is a vertical memory device in which a plurality of word lines are vertically stacked,
A method of driving a storage device, wherein the plurality of memory cells included in the first and second blocks are multi level memory cells (MLCs) each storing a plurality of data bits.

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