KR102158965B1 - Apparatus and methods for driving displays - Google Patents

Abstract

An apparatus for driving an electro-optic display comprises: a first switch designed to supply a first voltage to the electro-optical display during a first driving phase, a second switch designed to control the voltage during a second driving phase, and during a second driving phase. It may include resistors coupled to the first and second switches to control the attenuation rate of the voltage.

Description

Apparatus and methods for driving displays

relation Reference to applications

This application claims the benefit of Provisional Application No. 62/219,606, filed September 16, 2015.

This application is also filed on August 3, 2016 by U.S. It relates to provisional application No. 62/370,703, which is essentially a U.S. filed on November 30, 2015. Provisional application 62/261,104 and U.S., filed on February 4, 2015. It relates to Provisional Application No. 62/111,927.

This application is further related to co-pending application No. 15/014,236, filed on February 4, 2015. The applications mentioned above and all U.S. The disclosures of patents and published and co-pending applications are also incorporated herein by reference.

background

This invention relates to methods for driving bistable electro-optical displays, and an apparatus for use in such methods. More specifically, this invention relates to driving methods and apparatus for adjusting a gate-on voltage value after an active update to reduce transistor degradation associated with voltage stress that may be caused by residual voltage discharge.

According to one aspect of the claims disclosed herein, an apparatus for driving an electro-optic display comprises: a first switch designed to supply a voltage to the electro-optical display during a first driving phase, a first switch designed to control the voltage during a second driving phase. It may include two switches, and a resistor coupled to the first and second switches to control the attenuation rate of the voltage during the second driving phase. In some embodiments, during the first and second drive phase, only one of the first and second switches is engaged. Also in some other embodiments, both the first and second switches are separated during the third drive phase.

Various aspects and embodiments of the application will be described with reference to the following figures. It should be noted that the drawings are not necessarily drawn to scale. Items appearing in multiple figures are denoted by the same reference number in all figures in which they appear.
1A is a schematic diagram of a simple gate-on voltage electrical circuit of an electro-optical display, in accordance with some embodiments.
1B is a graph showing gate-on voltage versus time during a voltage decay phase and active update, including a post-driving discharge phase, in accordance with some embodiments, wherein the gate-on voltage is an exponential function to ground. Decay into
1C is a graph showing gate-on voltage versus time during an active update and a voltage decay phase with a preferred voltage profile, in accordance with some embodiments.
2A is a schematic diagram of a gate on voltage electrical circuit, including a resistor, of an electro-optical display, in accordance with some embodiments.
2B is a graphical schematic diagram illustrating a gate on voltage over time for the circuit of FIG. 2A, in accordance with some embodiments.
3A is a schematic diagram of a gate on voltage electrical circuit including a resistor and a capacitor of an electro-optical display, in accordance with some embodiments.
3B is a graphical schematic diagram illustrating a gate-on voltage over time for the circuit of FIG. 3A, in accordance with some embodiments.
4A is a schematic diagram of a gate on voltage electrical circuit, including resistors and capacitors, of an electro-optical display, in accordance with some embodiments.
4B is a graphical schematic diagram illustrating a gate-on voltage over time for the circuit of FIG. 4A, in accordance with some embodiments.
5A is a schematic diagram of a gate on voltage electrical circuit including a resistor and a capacitor of an electro-optic display, in accordance with some embodiments.
5B is a schematic diagram of a gate on voltage electrical circuit, including resistors and capacitors, of an electro-optical display, in accordance with some embodiments.
6A is a schematic diagram of a gate on voltage electrical circuit including multiple capacitors and resistors of an electro-optical display, in accordance with some embodiments.
6B is a graphical schematic diagram illustrating a gate on voltage over time for the circuit of FIG. 6A, in accordance with some embodiments.
7 is a schematic diagram of a gate on voltage electrical circuit including a Zenor diode of an electro-optical display, in accordance with some embodiments.
8A is a schematic diagram of a gate on voltage electrical circuit including a resistor and a capacitor of an electro-optical display, in accordance with some embodiments.
8B is a graphical schematic diagram illustrating a gate on voltage over time for the circuit of FIG. 8A, in accordance with some embodiments.
9 is a graphical illustration of a comparison with a conventional device for the capabilities of the device shown in FIG. 8A.
10A is a graph showing a maximum graytone shift versus the number of updates with or without residual voltage discharge, in accordance with some embodiments.
10B is a graph showing a maximum ghost shift with respect to the number of updates with or without residual discharge, according to some embodiments.
11A is a graph showing a maximum gray tone shift versus number of updates with residual discharge, without residual discharge, and with residual discharge and negative biasing, in accordance with some embodiments.
11B is a graph showing a maximum ghost shift versus number of updates with residual discharge, without residual discharge, and with residual voltage discharge and reduced charge biasing, in accordance with some embodiments.
12A is a schematic diagram of a signal-timing diagram representing gate voltage over time, in accordance with some embodiments.
12B is a schematic diagram of a signal-timing diagram representing voltage over time, in accordance with some embodiments.

Terms

Electro-optical displays include a layer of electro-optical material, the term used herein in its conventional sense in imaging technology to refer to a material having first and second display states that differ in at least one optical property. And the material is changed from its first display state to its second display state by application of an electric field to the material. In the displays of the present disclosure, the electro-optical medium may be solid, in the sense that the electro-optical medium has solid outer surfaces, although the medium may and often do not have internal liquid or gas filling spaces (hereinafter, such display Are referred to as "solid electro-optical displays"). Thus, the term “solid electro-optic displays” includes encapsulated electrophoretic displays, encapsulated liquid crystal displays, and other types of displays discussed below.

The optical property may be a color perceptible to the human eye, but other optical properties such as optical transmission, reflectance, luminescence, or, in the case of displays intended for machine reading, the implication of a change in the reflectance of an electromagnetic wavelength outside the visible range. May be pseudo color The term L star may be used herein or may be represented by “L*”. L* usually has a CIE definition: L* = 116(R/R0)1/3-16, where R is the reflectance and R0 is the standard reflection value.

The term "gray state" is used in its conventional meaning in imaging technology to refer to a state in the middle of two extreme states of a pixel, and does not necessarily imply a black-white transition between the two extreme states. For example, in some of the patents and published applications mentioned below, the extreme states are white and dark blue, so that the intermediate "gray state" is actually a light blue color. Indeed, as already mentioned, the transition between the two extreme states may not be a color change at all.

The terms “bistable” and “bistable” are used in their conventional meaning in the art to refer to displays comprising display elements having first and second display states that differ in at least one optical property, and is limited to After the addressing pulse of the duration, after the given element has been driven, in order to assume either its first or second display state, after the addressing pulse has ended, the state is at least several times, for example 4 times. , It will last for the minimum duration of the addressing pulse used to change the display element. The published U.S. Patent Application No. 2002/0180687 shows that some particle-based electrophoretic displays that enable gray scale are stable in their extreme black and white states as well as in their intermediate gray states, and some other electro-optic displays The same is true for types. This type of display is aptly referred to as “multi-stable” rather than bistable, but for convenience herein the term “bistable” may be used to cover bistable and multi-stable displays.

The term “residual voltage” is used herein to refer to a sustained or decaying electric field that may remain in the electro-optical display after the addressing pulse (voltage pulse used to change the optical state of the electro-optical medium) has ended. Used. The attenuation rate of the residual voltage of the electro-optical display may decrease as the residual voltage approaches a threshold. Low residual voltage (e.g., residual voltage of about 200 mV or less) is electrical, including, without limitation, shift in the optical state associated with the addressing pulse, drift in the optical state of the display over time, and/or ghosting. Artifacts in optical displays can occur.

The persistence of the residual voltage for a significant period of time imposes a "residual impulse" on the electro-optical medium, strictly speaking the effects on the optical states of electro-optical displays, which are usually considered to be caused by residual voltage rather than residual voltage. May be responsible for Such residual voltage induces undesirable effects on images displayed on electro-optic displays, including without limitation, so-called "ghosting", where traces of the previous image are still visible after the display is rewritten. can do.

The "shift" in the optical state associated with the addressing pulse means that the first application of a particular addressing pulse to the electro-optical display results in a first optical state (e.g., a first gray tone), and the same addressing to the electro-optical display. Refers to a situation in which the subsequent application of the pulse results in a second optical state (eg, a second gray tone). The residual voltages may cause a shift in the optical state, since the voltage applied to the pixel of the electro-optical display during the application of the addressing pulse includes the sum of the voltage of the addressing pulse and the residual voltage.

"Drift" in the optical state of the display over time refers to a situation in which the optical state of the electro-optical display changes while the display is stopped (eg, while no addressing pulses are applied to the display). The residual voltage may cause a drift in the optical state because the optical state of the pixel may depend on the residual voltage of the pixel, and the residual voltage of the pixel may attenuate with time.

As discussed above, “ghosting” refers to a situation in which, after the electro-optical display has been rewritten, the traces of the previous image(s) are still visible. The residual voltage may cause “edge ghosting”, a type of ghosting in which the contours (edges) of some of the previous images are still visible.

The term “impulse” is used herein in its conventional sense in the imaging technique of the integral of voltage over time. However, some bistable electro-optic media act as charge transducers, and with such media an alternative definition of impulse, i.e. the integration of current over time (equal to the applied total charge) may be used. An appropriate definition of impulse should be used, depending on whether the medium acts as a voltage-time impulse transducer or a charge impulse transducer.

Several types of electro-optical displays are known. One type of electro-optical display is, for example, U.S. Patent number 5,808,783; 5,777,782; 5,760,761; 6,054,071 6,055,091; 6,097,531; 6,128,124; 6,137,467; And a rotating bichromal member type as described in 6,147,791 (this type of display is often referred to as a "rotating two-color ball", but in some of the patents mentioned above it is not spherical, so the term "rotating two-color Absent" is preferred). Such a display uses an internal dipole, and a number of small bodies (which may be spherical or cylindrical, without limitation) having two or more sections with different optical characteristics. These bodies are suspended in liquid filling vacuoles in the matrix, and the vacuoles are filled with liquid so that the bodies are free to rotate. The appearance of the display is changed by applying an electric field to the display, thus rotating the bodies in various positions, and changing which of the sections of the bodies are visible through the viewing surface. Electro-optical media of this type may be bistable.

Another type of electro-optic display is in the form of a nanochromic medium comprising an electrode at least partially formed from an electrochromic medium, for example, a plurality of dye molecules capable of reversible color change attached to an electrode and a semiconductor metal oxide. Use electrochromic media; For example, O'Regan, B. et al., Naure 1991, 353, 737; And Wood, D., Information Display, 18(3), 24 (March 2002). In addition, Bach, U. et al., Adv. See Mater., 2002, 14(11), 845. Nanochromic films of this type are also described, for example, in U.S. Patent No. 6,301,038, International Application Publication No. WO 01/27690, and U.S. It is described in Patent Application No. 2003/0214695. Media of this type may be bistable.

Another type of electro-optical display is a particle-based electrophoretic display, in which a plurality of charged particles move through a suspending fluid under the influence of an electric field. Some properties of electrophoretic displays are listed in U.S., entitled "Methods for Addressing Electrophoretic Displays" published March 11, 2003. Patent No. 6,531,997, the entirety of which is incorporated herein.

Electrophoretic displays may have properties of good brightness and contrast, wide viewing angle, state bistableness, and low power consumption compared to liquid crystal displays. Nevertheless, there may be problems with the long-term image quality of some particle-based electrophoretic displays. For example, particles that make up some electrophoretic displays may precipitate, resulting in an inadequate lifetime for such displays.

As mentioned above, electrophoretic media may comprise a suspending fluid. This suspending fluid may be liquid, but electrophoretic media can be prepared using gaseous suspending fluids; For example, "Electrical toner movement for electronic paper-like display" by Kitamura, T. et al., IDW Japan, 2001, Paper HCS1-1, and "Toner display using insulative particles charged triboelectrically" by Yamaguchi, Y. et al., IDW Japan, 2001, Paper AMD4-4). See also European Patent Applications 1,429,178; 1,462,847; And 1,482,354; And international applications WO 2004/090626; WO 2004/079442; WO 2004/077140; WO 2004/059379; WO 2004/055586; WO 2004/008239; WO 2004/006006; WO 2004/001498; WO 03/091799; And WO 03/088495. Some gas-based electrophoretic media suffer from the same type of problems as some liquid-based electrophoretic media due to particle precipitation, for example when the media is used in an orientation that allows such precipitation with a sign placed in a vertical plane. It may be susceptible to influence. In fact, particle sedimentation appears to be a more serious problem with some gas-based electrophoretic media than with some liquid-based electrophoretic media, which is due to the lower viscosity of gaseous suspending fluids compared to liquid suspending fluids. This is because it allows for faster precipitation of the particles.

Massachusetts Institute of Technology (MIT), E Ink Corporation, E Ink California, LLC. And many of the patents and applications assigned to or in the names of related companies, describe a variety of technologies used in encapsulated and microcell electrophoresis, and other electro-optical media. Encapsulated electrophoretic media comprise a number of small capsules, each comprising an inner phase containing electrophoretic-moving particles within the fluid medium, and a capsule wall surrounding the inner phase. Typically, the capsules themselves are held in a polymeric binder to form a coherent layer positioned between the two electrodes. In a microcell electrophoretic display, charged particles and fluid are not encapsulated within microcapsules, but instead are held within a plurality of cavities formed within a carrier medium, typically a polymeric film [[hereinafter, the term "microcavity electrophoretic display May be used to cover both encapsulated and microcell electrophoretic displays]]. The techniques described in these patents and applications include:

(a) electrophoretic particles, fluids and additives; For example, U.S. See patents 7,002,728 and 7,679,814;

(b) capsules, binders, and encapsulation processes; For example, U.S. Patent number Nos. 6,922,276***; See 7,411,719***;;

(c) microcell structures, wall materials, and methods of forming microcells; For example, U.S. Patent number 7,072,095 and U.S. See Patent Application Publication No. 2014/0065369;

(d) methods of filling and sealing microcells; For example, U.S. Patent number 7,144,942 and U.S. See Patent Application Publication No. 2008/0007815;

(e) films and sub-assemblies comprising electro-optical materials; U.S. Patent No. 6,982,178; See 7,839,564;

(f) backplanes, adhesive layer and other auxiliary layers and methods used in displays; For example, U.S. See patent numbers 7,116,318 and 7,535,624;

(g) color shaping and color adjustment; For example, U.S. See patent numbers 7,075,502 and 7,839,564;

(h) methods for driving displays; For example, U.S. Patent No. 5,930,026; 6,445,489; 6,504,524; 6,512,354; 6,531,997; 6,753,999; 6,825,970; 6,900,851; 6,995,550; 7,012,600; 7,023,420; 7,034,783; 7,061,166; 7,061,662; 7,116,466; 7,119,772; 7,177,066; 7,193,625; 7,202,847; 7,242,514; 7,259,744; 7,304,787; 7,312,794; 7,327,511; 7,408,699; 7,453,445; 7,492,339; 7,528,822; 7,545,358; 7,583,251; 7,602,374; 7,612,760; 7,679,599; 7,679,813; 7,683,606; 7,688,297; 7,729,039; 7,733,311; 7,733,335; 7,787,169; 7,859,742; 7,952,557; 7,956,841; 7,982,479; 7,999,787; 8,077,141; 8,125,501; 8,139,050; 8,174,490; 8,243,013; 8,274,472; 8,289,250; 8,300,006; 8,305,341; 8,314,784; 8,373,649; 8,384,658; 8,456,414; 8,462,102; 8,537,105; 8,558,783; 8,558,785; 8,558,786; 8,558,855; 8,576,164; 8,576,259; 8,593,396; 8,605,032; 8,643,595; 8,665,206; 8,681,191; 8,730,153; 8,810,525; 8,928,562; 8,928,641; 8,976,444; 9,013,394; 9,019,197; 9,019,198; 9,019,318; 9,082,352; 9,171,508; 9,218,773; 9,224,338; 9,224,342; 9,224,344; 9,230,492; 9,251,736; 9,262,973; 9,269,311; 9,299,294; 9,373,289; 9,390,066; 9,390,661; And 9,412,314; And U.S. Patent Application Publication No. 2003/0102858; 2004/0246562; 2005/0253777; 2007/0070032; 2007/0076289; 2007/0091418; 2007/0103427; 2007/0176912; 2007/0296452; 2008/0024429; 2008/0024482; 2008/0136774; 2008/0169821; 2008/0218471; 2008/0291129; 2008/0303780; 2009/0174651; 2009/0195568; 2009/0322721; 2010/0194733; 2010/0194789; 2010/0220121; 2010/0265561; 2010/0283804; 2011/0063314; 2011/0175875; 2011/0193840; 2011/0193841; 2011/0199671; 2011/0221740; 2012/0001957; 2012/0098740; 2013/0063333; 2013/0194250; 2013/0249782; 2013/0321278; 2014/0009817; 2014/0085355; 2014/0204012; 2014/0218277; 2014/0240210; 2014/0240373; 2014/0253425; 2014/0292830; 2014/0293398; 2014/0333685; 2014/0340734; 2015/0070744; 2015/0097877; 2015/0109283; 2015/0213749; 2015/0213765; 2015/0221257; 2015/0262255; 2016/0071465; 2016/0078820; 2016/0093253; 2016/0140910; And 2016/0180777;

(i) applications of displays; For example, U.S. Patent numbers 7,312,784 and 8,009,348; And 9,197,704; And

(j) U.S. Patent No. 6,241,921 and U.S. Patent Application Publication No. 2015/0277160; And U.S. Non-electrophoretic displays, as described in Patent Application Publication Nos. 2015/0005720 and 2016/0012710.

Many of the patents and applications mentioned above, in an encapsulated electrophoretic medium, the walls surrounding discrete microcapsules can be replaced by a continuous phase, thereby producing a so-called polymeric distributed electrophoretic display, wherein the electrophoretic medium Contains a plurality of distinct droplets of an electrophoretic fluid and a continuous phase of a polymeric material, and within such a polymer dispersed electrophoretic display, the distinct droplets of an electrophoretic fluid are each individual liquid. Even if it is not associated with the enemy, it may also be considered as capsules or microcapsules; See, for example, 2002/0131147 mentioned above. Thus, for the purposes of this application, such polymer dispersed electrophoretic media are considered as subspecies of encapsulated electrophoretic media.

A related type of electrophoretic display is the so-called "microcell electrophoretic display". In a microcell electrophoretic display, charged particles and suspending fluid are not encapsulated within the microcapsules but instead are held within a plurality of cavities formed within a carrier medium, for example a polymeric film. For example, Sipix Imaging, Inc. International Application Publication No. WO 02/01281 all transferred to and published U.S. See Application No. 2002/0075556.

Many of the E Ink and MIT patents and applications mentioned above also contemplate microcell electrophoretic displays and polymer dispersed electrophoretic displays. The term “encapsulated electrophoretic displays” can refer to all such display types, which may also be collectively described as “microcavity electrophoretic displays” to generalize across the morphology of the walls.

Another type of electro-optic display is the electrowetting display developed by Philips and described in Hayes, R. A. et al. "Video-Speed Electronic Paper Based on Electrowetting", Nature, 425, 383-385 (2003). It is shown in co-pending application No. 10/711,802 filed October 6, 2004 that such electrowetting displays can be made bistable.

Other types of electro-optical materials may also be used. Of particular interest are bistable ferroelectric liquid crystal displays (FLCs) are known in the art and exhibit residual voltage behavior.

Electrophoretic media are opaque (e.g., in many electrophoretic media, because the particles substantially block the transmission of visible light through the display) and may operate in reflective mode, but some electrophoretic displays are in a single display state. Can be made to operate in a so-called "shutter mode" which is substantially opaque and one is light-transmitting. For example, the patents U.S. Patent numbers 6,130,774 and 6,172,798, and U.S. Patent No. 5,872,552; 6,144,361; 6,271,823; 6,225,971; And 6,184,856. Similar to an electrophoretic display, but relying on variations in electric field strength, a dielectric electrophoretic display may operate in a similar mode; U.S. See patent number 4,418,346. Other types of electro-optical displays may also be capable of operating in a shutter mode.

Encapsulated or microcell electrophoretic displays may not suffer from clustering and precipitation failures of typical electrophoretic devices and may provide additional benefits, such as the ability to print or coat the display on various flexible and rigid substrates (the word The use of “printing” includes pre-metered coatings such as patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating ; Dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; silk screen printing processes; electrostatic printing processes; thermal printing processes; inkjet printing processes; electrophoretic deposition; and other similar It is intended to include all forms of printing and coating, including but not limited to techniques). Thus, the display of results can be flexible. Further, since the display medium can be printed (using various methods), the display itself can be produced inexpensively.

Other electro-optical displays that display the bistable or multi-stable behavior and similar behavior of particle-based electrophoretic displays (such displays may be referred to as “impulse driven displays” for convenience) are liquid crystal displays (LCDs). It is in striking contrast to the behavior of the fields. Twisted nematic liquid crystal displays are not bi- or multi-stable, but act as voltage transducers, so applying a given electric field to a pixel of such a display produces a specific gray level in the pixel, regardless of the gray level previously present in the pixel. do. In addition, LCD displays operate only in one direction (impermeable or "dark" to transmissive or "bright"), and the reverse transition from a brighter state to a darker state is affected by reducing or eliminating the electric field. Also, the gray level of the pixels of an LC display is not sensitive to the polarity of the electric field, only for its size, and for practical technical reasons commercial LC displays usually reverse the polarity of the driving field at frequent intervals. In contrast, bistable electro-optic displays act as a first approximation as impulse transducers, so that the final state of the pixel depends not only on the applied electric field and the time at which this electric field is applied, but also on the state of the pixel before the application of the electric field. Depends.

A high-resolution display may include individual pixels addressable without interference from adjacent pixels. One way to obtain such pixels is to provide an array of non-linear elements, such as transistors or diodes, with at least one non-linear element associated with each pixel to create an “active matrix” display. The addressing or pixel electrode addressing one pixel is connected to an appropriate voltage source via an associated nonlinear element. When the nonlinear element is a transistor, the pixel electrode may be connected to the drain of the transistor, and this arrangement will be assumed in the following description, but it is essentially arbitrary and the pixel electrode can be connected to the source of the transistor. In high resolution arrays, pixels may be arranged in a two-dimensional array of rows and columns, such that any particular pixel is uniquely defined by the intersection of one specified row and one specified column. The sources of all transistors in each column may be connected to a single column electrode, while the gates of all transistors in each row may be connected to a single row electrode; Again the allocation of sources to rows and gates to columns may be reversed if desired.

The display may be written in a row-by-row manner. The row electrodes are connected to the row driver, which, for example, applies a voltage to the selected row electrode to ensure that all transistors in the selected row are conductive, while, for example, all transistors in these unselected rows are non-conductive. A voltage can also be applied to all other rows to ensure that the state remains. The column electrodes are connected to the column drivers, which place various column electrode voltages selected to drive the pixels in the selected row to their desired optical states (the voltages mentioned above are the voltages of the electro-optical medium from the nonlinear array. It may be provided on the opposite side or relates to a common front electrode extending over the entire display). After a preselected interval known as the "line address time", the selected row is deselected, another row is selected, and the voltage on the column drivers is changed so that another line of the display is written.

Residual voltage discharge

U.S., filed on February 4, 2015 As described in Provisional Application No. 62/111,927, the entire contents are incorporated herein by reference, and a preferred embodiment for dissipating the residual voltage keeps all pixel transistors in a conducting state for an extended period of time. For example, all pixel transistors are relative to the source line voltage with a value that makes the pixel transistors relatively conductive compared to the non-conductive state used to isolate the pixels from the source lines as part of normal active matrix drive. It may be brought into a conducting state by bringing the gate line (referred to herein as a “select line”) voltage.

In some embodiments, a specially designed circuit may provide addressing of all pixels at the same time. In standard active matrix operation, the select line control circuit typically does not bring all gate lines to values that achieve the above-mentioned conduction state for all pixel transistors. A convenient way to achieve this conduction is a select line with an input control line that causes an external signal to impose a condition for all select line outputs to receive a voltage supplied to a select select driver to bring the pixel transistors into conduction. It is supplied by the driver chips. By applying an appropriate voltage value to this particular input control line, all transistors may be in a conducting state. As an example, for displays with n-type pixel transistors, some select drivers have a "Xon" control input. By selecting a voltage value for input to the select drivers as the Xon pin input, the gate-on voltage is routed to all select lines. For simplicity, the description of this invention is written for a backplane employing n-type pixel transistors. In this case, the gate-on low voltage is positive. However, for a backplane fabricated with p-type pixel transistors, all methods described herein can be employed by inverting all voltages described and indicated in this invention. In this case, the gate-on voltage is negative.

The gate-on voltage is an important voltage for the purpose of dissipating the residual voltage of the electro-optical active matrix display. The application of the gate-on voltage across the entire display is essential for "discharge after driving", which is typically applied at the end of the "active driving phase" (also referred to herein as "image update" or "active update period"). . The “discharge phase after driving” (also referred to herein as “residual voltage discharge phase” or “residual voltage discharge”) is part of the “voltage attenuation phase”, and if the discharge phase after driving is the same as the voltage attenuation phase, these The terms may be used interchangeably (and are used interchangeably herein).

However, the U.S. filed on September 16, 2015. As described in Provisional Application No. 62/219,606, the entire contents of which are incorporated herein by reference, and maintaining the pixel transistors in a conducting state for the extended duration required for residual voltage discharge is the deterioration of the pixel transistor and/or of the display. It may cause a shift in optical performance. It is advantageous to be able to adjust the gate-on voltage value during the discharging phase after driving to reduce and/or prevent the effects of maintaining the pixel transistors for an extended duration. Post-driving discharge may be performed after every active update, after a specified number of active updates, after a specified time period, or when requested by a user. Additionally, the discharge after driving may be stopped by active update so that the gate-on voltage may not reach the zero value.

The present invention describes apparatuses and methods for adjusting a gate on voltage after an active update phase.

E/O electronics

As described above, extended periods of high gate voltage values, such as those experienced during residual voltage discharge, may cause pixel transistor deterioration. Reducing the high gate voltage value during the residual voltage discharge and/or increasing the speed of the attenuation rate to dissipate the residual voltage may reduce or prevent pixel transistor degradation. The optimal attenuation rate for dissipating the residual voltage in the display may be determined empirically by balancing the acceptable level of discharge efficiency and the effect on the transconductance of the pixel transistor. An advantage of this invention is that the discharge after driving may be achieved at a low voltage which will reduce pixel transistor degradation and prevent optical shifting.

The various aspects described above, as well as additional aspects, will now be described in detail below. It should be appreciated that these aspects may be used alone, all together, or in any combination of two or more, without being mutually exclusive.

Electro-optical displays may receive power from an external electronic device such as a display controller and supply voltage from a “power management” circuit. The power management circuit may supply multiple voltages, including a "gate on voltage" supplied to the gate lines (also referred to herein as "select lines") to bring the transistors on the selected lines into a conducting state. have. The power management circuit may be discrete components or an integrated circuit (eg, a power management integrated circuit (“PMIC”)). The additional circuit may include pull-down resistor(s) and/or pull-down capacitor(s).

1A is a schematic diagram of a simple gate-on voltage circuit of an electro-optical display using PMIC 102 showing a gate-on voltage line 104 from PMIC 102 to a gate driver 106 of an active matrix display. The circuit of Figure 1 allows controlling the gate-on voltage 104 at the end of the active drive by changing the value of the pull-down resistor (R) 108. A high value for R 108 slows down the gate-on voltage decay rate, while a low value for R 108 speeds up the gate-on voltage decay rate. Assuming some level of the capacitive element ("C") on line 104 (not shown) from PMIC to gate driver, the pull-down resistor ("R") 108 means that the gate on line 104 is 0 volts. Will be decayed exponentially, and the time constant is given as the product of the resistance value ("R") and the line capacitance ("C"). The voltage attenuation through R resistance 108 may be calculated as follows:

Wherein V ₀ is the initial voltage, the line capacitance C includes any capacitance designed as part of the PMIC to stabilize the voltage and the parasitic capacitance of the voltage line.

Cited above, U.S. The post-driving discharge method described in Provisional Application No. 62/111,927 uses a slow attenuation in the gate-on voltage. During the post-driving discharge phase, which usually occurs after the active update phase, the gate-on voltage is typically allowed to decrease through resistors connected to ground. In discharge after driving, all active matrices become gate-on voltage, which attenuates from that value to ground during active display driving.

1B is a graph showing gate-on voltage versus time during a voltage decay phase and active update, including a discharge phase after driving, where the gate-on voltage exponentially attenuates to ground. Time t=0 is the end of the active update. In Fig. 1B, the "discharge after driving" period is defined as starting at time t ₁ and ending at time t ₂ . The time t ₁ may be as small as 0, and in this case, the discharge after driving starts immediately after the update, or may be delayed until the gate-on voltage value attenuates or decreases to a desired value. The time (t ₂ ) is chosen to be large enough until the discharge after driving is effective to sufficiently reduce the charge polarization in the display, or, if time allows, the gate-on voltage attenuates to 0 volts.

As described above, it is advantageous to apply a "gate on" voltage of sufficient size and not high to allow draining of the pixel residual voltage, to reduce transistor degradation. If it is higher than the required voltage level, it is not easy to increase the TFT bias stress and improve residual voltage draining. As shown in Fig. 1B, the simplest implementation of discharging after driving is to cause the "gate on" voltage to decay exponentially after driving. Although a low, subsequent voltage value may be small enough to enable timely draining of the residual voltage, a high, initial voltage value is sufficient for timely draining of the residual voltage. Additionally, it is beneficial, but no more, to minimize the time during which all select lines are turned on to allow sufficient residual voltage discharge.

This invention controls the "gate on" voltage to achieve these advantages by shaping the time profile of the "gate on" voltage during the discharge phase after driving. The invention uses a metric K, which is useful for accessing the beneficial nature of the "gate on" voltage profile during the discharge phase after driving.

Where T _m is the total time the “gate on” voltage lies between the high voltage magnitude (V _H ) and the low voltage magnitude (V _L ) within the time domain starting at the end of the display update and until the time after the end of the update (t ₂ ). And T _h is the total time when the “gate on” voltage is greater than V _H. t ₂ is the end time of discharging after driving when not interrupted by other display processes such as the next image update. The values V _L and V _H may be defined or limited hereinafter based on display performance and usage. The assignments to the values (V _L and V _H ) are described in more detail below. Values are defined for different voltages and are all related to “zero voltage” or “ground” for the driving electronics (source and/or select drivers and display controller).

Natural K ("K _natural ") may be defined as:

Where V ₀ is the “gate on” voltage applied during the image update or active update (as discussed above, all voltages are defined relative to the “gate off” voltage for the display under consideration). For convenience, here we define a normalized K referred to as α as follows.

In the equation, K, K _natural and alpha ("α") are all functions of time (t ₂ ) and voltage parameters (V _L and V _H ). A preferred voltage profile has an alpha greater than 2, an alpha greater than 5, or preferably an alpha greater than 20, wherein V _L and V _H satisfy at least two of the following constraints: 1) V _L is at least V _Is 5% of ₀ ; 2) V _H is at least less than 80% of V _O ; 3) V _H is greater than V _L ; And (V _H -V _L )/[V _H + V _L /2]> 0.1. ㅈ [4 constraints may be met to ensure that the separation between the V _H and V _L is important as compared to the average of the V _H and V _L.

1C is a graph showing gate-on voltage versus time during an active update and a voltage decay phase with a preferred voltage profile. The dashed line shown and described previously in FIG. 1B represents the typical exponential decay after active update. The solid line represents an example of a more beneficial voltage profile of the discharge phase after driving, where the gate-on voltage value decays rapidly or decreases to a lower value, and then decays from this reduced value with the time of the discharge after driving. As shown in Fig. 1C, the initial rapid reduction of the gate-on voltage after an active update is complete before "turning on" all select lines. Alternatively, all select lines may be turned on at t=0. As another alternative, all select lines may be turned on after the gate-on voltage is initially reduced and attenuated to a desired value or after a predetermined time. After the discharge after driving is effective to sufficiently reduce the charge polarization in the display, or alternatively, after the gate-on voltage has decayed to 0 volts, all select lines may be turned off (t ₂ ).

2A shows a “single pole, single throw” switch (“SW1”) 210 (“open” as shown) between the PMIC 202 and the gate driver 206. A schematic diagram of the simple electrical circuit layout of FIG. 1A, further comprising. When the SW1 switch 210 is closed, the circuit actively drives the gate driver 206. When the SW1 switch 210 is open (at the end of the active drive), the PMIC 202 will stop driving the gate high voltage 206 and the gate-on voltage attenuation rate is the pull-down resistor R 208 and the gate-on line 204. ) Will be determined by the various capacitances experienced.

FIG. 2B is a graphical schematic showing the gate-on voltage over time of the circuit of FIG. 2A during the active driving phase 220 when the SW1 switch is closed and the voltage decay phase 222 when the SW1 switch is open.

3A is a schematic diagram of a gate-on voltage electric circuit according to an embodiment of the present invention. 3A shows a gate-on voltage line 304 with a first “single pole, single throw” switch (“SW1”) 310 from PMIC 302 to gate driver 306 of an active matrix display. The circuit consists of a resistor (R) 308, a second "single pole, double throw" switch ("SW2") 312 (in position "a" as shown) and a pull-down capacitor ("C ₁ ") 314 ) Further includes.

The switches SW1 and SW2 are programmed to open and close almost simultaneously, so that only one switch will be engaged at a time. In operation, during active display driving, SW1 is closed and SW2 is open, while during the voltage decay phase and post-driving discharge, SW1 is open and SW2 is closed. SW1 is an example of a single pole, single throw that is only connected when in the closed position. SW2 is an example of a single pole, double throw, which switches between two points and is always connected to either position "a" or position "b".

By incorporating the pull-down capacitor C ₁ 314 and the second switch (SW2) 312, the gate-on voltage value may be reduced to a lower value, and then attenuated from this reduced voltage value. At the end of the active drive, SW1 is open and SW2 is at position "b", and the drive voltage ("V") attenuation may be calculated according to the following equation.

Wherein C is the line capacitance of the gate on line 304 and V _O is the initial voltage.

Figure 3b shows the circuit of Figure 3a when the SW1 switch is closed and the SW2 switch is in position "a" during the active drive phase and the SW1 switch is open and the SW2 switch is in position "b" during the voltage decay phase 322. Is a graphical schematic diagram showing the gate-on voltage over time. As shown in Fig. 3B, during the active driving phase 320 (when SW1 is closed and SW2 is in position "a"), the PMIC drives the gate driver 306. During the voltage decay phase (when SW1 is open and SW2 is in position "b"), the voltage value is quickly pulled to a smaller voltage value (ie V _o C / (C + C ₁ )) and this small value (322) Attenuates at a rate determined by the pull-down resistance (R) 308 and the capacitance of C and C ₁ from.

4A is a schematic diagram of a gate-on low voltage electric circuit according to still another embodiment of the present invention. 4A shows a gate on voltage line 404 with a first switch ("SW1") 410 from a PMIC 402 to a gate driver 406 of an active matrix display. The circuit consists of a resistor (R) 408, a second switch (SW2) 412 (at position "a" as shown), a pull-down capacitor (C ₁ ) 414, and a second pull-down resistor ("R ₁ ") (416). Pull-down capacitor (C ₁ ) 414 and pull-down resistor (R ₁ ) 416 are in series with SW2 412; However, the positions relative to SW2 may be interchanged.

As shown in Fig. 4B, during the active driving phase 420 (when SW1 is closed and SW2 is in position "a"), PMIC drives the gate driver 406 at the active driving gate-on voltage value and the capacitor C ₁ Charge (414). During the voltage decay phase 422 (when SW1 is open and SW2 is in position “b”), the gate-on voltage value is reduced to the value of capacitor C ₁ 414 and the resistors ((R) 408 and ( R1) decays at the rate determined by (416)). The addition of the capacitor C ₁ and resistors R and R ₁ allows an initial reduction of the gate-on voltage value and a greater degree of control over the attenuation rate.

5A is a schematic diagram of a gate-on voltage electric circuit according to another embodiment of the present invention, which is equivalent to FIG. 3A. 5A shows a gate-on voltage line 504 with a first switch ("SW1") from PIMC 502 to a gate driver 506 of an active matrix display. The circuit further includes a second single pole, double throw switch (“SW2”) 512 (at position “a” as shown) positioned on the gate on voltage line 504. SW2 (512) combines the pull-down resistor R (508) and the pull-down capacitor (C ₁ ) (514). During the active drive phase (320 as shown in Fig. 3B), when SW1 is closed and SW2 is in position "a", the capacitor C ₁ 514 will be charged. During the voltage decay phase (322 as shown in Fig. 3b), when SW1 is open and SW2 is in position "b", the voltage value initially drops to the value of capacitor (C ₁ ) 514, then It will decay at a rate determined by the resistance (R) 508.

Using FIG. 5A as an example electrophoretic display, during the active update phase, the PMIC may drive the gate-on voltage at +22 volts. During the post-driving discharge phase ("residual voltage discharge"), a gate-on voltage value of +22 volts is excessive and a reduced gate high voltage value is desirable. In some displays, residual voltage discharge may be achieved using a voltage value of about +8 volts. The preferred circuit of Fig. 5A includes a capacitor C ₁ sufficient to quickly drop the gate-on voltage to about 10 to 12 volts after the active drive phase. The desired value of capacitor C ₁ is attached to the display (SW2 is in position "b") but is approximately equal to the capacitance of the gate on line when the PMIC is disconnected (SW1 is in position "b"). Since different displays and drive electronics have varying gate-on capacitances, a single capacitance value (C ₁ ) will not apply to all displays but may be selected based on the desired initial voltage drop. Similar to resistor (R) 508, a single resistor value will not apply to all displays, but may be selected based on the desired voltage decay rate.

5B is a schematic diagram of a gate-on voltage electric circuit according to another embodiment of the present invention, which is equivalent to FIG. 4A. 5B is a schematic diagram of the electrical circuit of FIG. 5A further including a pull-down resistor (R ₁ ) 516. In FIG. 5B, SW2 512 combines a pull-down resistor (R) 508, a pull-down capacitor (C ₁ ) 504, and a pull-down resistor (R ₁ ) 516. During the active drive phase (420 as shown in Fig. 4B), when SW1 is closed and SW2 is in position "a", the capacitor C1 514 will discharge to 0V. During the voltage decay phase (422 as shown in Fig. 4b), when SW1 is open and SW2 is in position "b", the voltage value initially drops to the capacitor (C ₁ ) 514, then R ₁ It will decay at the rate determined by (508) and R ₁ (516).

6A is a schematic diagram of a gate-on voltage electric circuit according to another embodiment of the present invention. 6A shows a gate on voltage line 604 with a first switch ("SW1") from a PMIC 602 to a gate driver 606 of an active matrix display. The circuit consists of a pull-down resistor (R) 608, a pull-down capacitor ("C ₁ ") 614, a second pull-down resistor located between the resistor (R ₁ ) 618 and the pull-down capacitor (C ₂ ) 616. ("R ₁ ") 618, a second pull-down capacitor ("C ₂ ") 616, and a second switch ("SW2") 612 (which is "open", as shown). do. The pull-down capacitor (C ₁ ) 614, the pull-down resistor (R ₁ ) 618 and the pull-down capacitor (C ₂ ) 616 are in series.

When PMIC is closed by the SW1 and the SW2 to be open to the gate-on line V _o volts, the voltage across C ₁ rises to _{V o * C 2 / (C} 1 + C 2). The capacitors C ₁ and C ₂ are selected to set this voltage to a desired low level during the discharge period after driving. Resistor (R ₁ ) 618 is chosen to avoid current spikes that cannot be supported by PMIC and the value of R ₁ can be 0 ohms, in which case R ₁ is not essential. Also, note that the positions of R ₁ 618 and C ₁ 614 may be interchanged with each other. Then during the discharge period after driving, SW1 is open and SW2 is closed so that the gate line is now at a lower voltage, which gradually decays through the discharge through the coupling resistance of the resistors (R) 608 and (R ₁ ) 618 maintain. The advantages of this alternative embodiment compared to the previous embodiment are: 1) the switch (SW2) is a “single pole, single throw” that can be easily implemented as a transistor, and 2) the desired low voltage is achieved by the gate line 604 By choosing C ₁ and C ₂ values that are much larger than the other capacitances experienced, they can be more easily set almost independently of the gate line capacitance.

As shown in Fig. 6B, during the active driving lunge 620 (when SW1 is closed and SW2 is open), the PMIC drives the gate driver 606 at the gate-on voltage value for active driving and the capacitor C ₁ And C ₂ ) is charged with a voltage value that sums up to the “gate on” voltage value. While voltage attenuating phase 622 (when SW1 is open and SW2 is closed), the gate-on voltage value of a drop in the voltage level across the C ₁ for active driving, and then is attenuated from this lower value. The addition of capacitors C ₁ and C ₂ and resistors R and R ₁ allows a greater degree of control over the initial decrease in the gate-on voltage value, both in the decay rate and the amount and time of the decrease after the initial value drop. . These values may be set to optimize the reduction of the voltage value during the voltage decay phase or one or both of these resistors may be removed from the electrical circuit.

7 is a schematic diagram of a gate-on voltage electric circuit according to still another embodiment of the present invention. 7 shows a gate on voltage line 704 with a first switch ("SW1") 710 from a PMIC 702 to a gate driver 706 of an active matrix display. The circuit further includes a second switch ("SW2") 712 ("open" as shown) positioned in the gate-on voltage line 704. SW2 712 combines a pull-down resistor (R) 708 and a Zener diode 714. During the discharge phase, when SW1 is open and SW2 is closed, the Zener diode quickly drops the gate-on voltage to a predetermined value (the "breakdown voltage" value described below) and the rate at which the voltage drops to this value is optional. It is affected by resistance (R) 708.

Zener diodes are commercially available diodes that allow current to flow in the forward direction in the same way as an ideal diode, but also allow current to flow in the reverse direction when the voltage is above a certain value ("breakdown voltage"). Zener diodes are available with different breakdown voltages and may be selected based on the desired breakdown voltage value for a particular display. Zener diodes are nonlinear between voltage and current, but how they respond to voltage and current is predictable. Zener diodes drop the voltage quickly when the current is high, but when the breakdown voltage is reached, the current is shut off. This is another way to quickly drop the gate-on voltage value during the voltage decay phase. It may be desirable to use more than one Zener diode instead of the one shown in FIG. 7. It is common practice to use two or more Zener diodes in series to achieve the desired voltage through which a series of Zener diodes will conduct current. A series of Zener diodes may be employed to gain flexibility in selecting the voltage at which the voltage drops through conduction through the Zener diodes. In this case, the effective "breakdown voltage" of such a series of Zener diodes is the sum of the respective "breakdown voltage" of the constituent Zener diodes.

This circuit has an advantage over previous versions. In previous versions, SW2 is a "single pole, double throw" switch and relies on the capacitor value to achieve the desired voltage at the start of the discharge session after driving. In this version, SW2 is a much simpler "single pole, single throw" switch. A Zener diode is used to control the desired voltage, which gives more predetermined control of the voltage during the discharge phase than circuits employing a capacitor to control the voltage during the discharge phase. Resistance in the diagram is optional. Perhaps this example should be given, but it should also indicate that there is no resistance or that the resistance value may be zero.

In accordance with another embodiment of the invention, a power management circuit (eg, power management integrated circuit, PMIC) may be configured to actively control a gate-on voltage. During active update, the gate-on value may be set so that the pixels are sufficiently charged to the desired voltage for successful display operation. After active update, during the post-driving discharge time, the gate-on voltage may be set to a reduced value with a lower magnitude sufficient to achieve post-driving discharge. PMIC manages gate-on voltage control using a switch that switches the gate-on voltage output to the display between different voltage values for discharging after driving and voltage values for actively driving the display.

8A shows another embodiment in accordance with the subject matter presented herein. Figure 8a shows a gate on voltage line 804 coupled to a first switch ("SW1") 810 from a PMIC to a gate driver 806 of an active matrix display, where SW1 provides a first voltage to the display. And a first voltage source 812 configured to be coupled. Additionally, a second voltage source 816, which is generally a low voltage source, is also coupled to the gate on voltage line 804 via a second switch ("SW2") 814 and applies a second voltage to the active matrix display. It may be configured to provide. In addition, capacitor (C) 818 and resistor (R) 820 will be connected in parallel with reference to voltage line 804 and gate driver 806 to provide more control over the attenuation of the gate-on voltage. May be.

Fig. 8B shows the attenuation of the gate-on voltage as configured by the circuit shown in Fig. 8A. As shown, during active phase 840 (when SW1 is closed and SW2 is at position "a"), the PMIC drives the display with the active driving gate-on voltage value and charges the capacitor (C) 818. During the second active phase 842 (when SW1 is in position "b" and SW2 is closed), the PMIC drives the display to the voltage indicated by the second voltage source 816. In this second active phase 842, the display is driven to a voltage level approximating the voltage value supplied by the second voltage source 816, and the capacitor (C) 818 is thus It is charged or discharged based on the voltage value. Finally, during the discharge phase 844 (when SW1 is in position "b" and SW2 is in position "a"), the gate-on voltage is the combination of capacitor (C) 818 and resistor (R) 820 It is designed to attenuate at a rate determined by. This configuration allows for a faster initial reduction in the gate-on voltage, thereby speeding up the entire attenuation process and improving device reliability.

In use, as shown in FIG. 9, after long-term use (e.g., 100,000 updates), the configuration shown in FIG. 8A is more reliable than some conventional configurations (lines 906 and 908) ( Lines 902 and 904 are provided.

Transistors and typical charge ratio/transistor degradation

Accordingly, in some aspects, the subject matter described herein also provides methods of driving a bistable electro-optical display having a plurality of pixels in an active matrix array. Various types of active matrix transistors are commercially available, including in particular amorphous silicon, microcrystalline, polysilicon and organics. Transistors in active matrix displays are typically designed to support an on:off ratio of 1:1000 since most active matrix displays have about 1000 rows. For an n-channel ("n-type") amorphous silicon thin film transistor ("a-Si TFT") in an active matrix display, the transistor is in its on state when a positive voltage is present on the gate-to-source. (Low selected) and in its off state when there is a negative voltage on the gate-source. Thus, n-type thin film transistors typically experience a positive to negative charge ratio of 1:1000. For a p-channel ("p-type") a-Si TFT in an active matrix display, the voltage polarity is reversed. The p-type transistor is in its on state when there is a negative voltage on the gate-source, and in its off state when there is a positive voltage on the gate-source. Thus, p-type thin film transistors typically experience a negative to positive charge ratio of 1:1000. When the on:off ratio is changed so that the transistor is turned on more frequently than the normal ratio, the transistor deteriorates and may adversely affect the optical performance of the display. Amorphous silicon transistors are more prone to degradation due to amorphous charge biasing. One way to reduce this type of transistor degradation is to standardize the on:off ratio by turning the transistor to its off position, so that the on:off ratio is a typical value of 1:1000, as more fully described herein. You get closer to

It should be noted that the typical on:off ratio of an active matrix display may be different from the 1:1000 ratio and that aspects of the invention described herein still apply.

Charge based on reducing the residual voltage of the electro-optical display Biasing

Charge biasing may occur when a residual voltage is discharged from an electro-optical display according to techniques disclosed herein and more fully disclosed in U.S. Provisional Application No. 62/111,927 filed Feb. 4, 2015, the entire contents of which are Incorporated herein by reference. The residual voltage of the pixel of the electro-optical display may be discharged by activating the transistors of the pixel (i.e., turning on all transistors) and setting the voltages of the front and rear electrodes of the pixel to approximately the same value for a time period. The amount of the residual voltage discharged by the pixel during the residual voltage discharge pulse may depend, at least in part, on the rate at which the pixel discharges the residual voltage and the duration of the residual voltage discharge pulse. In some embodiments, the duration of the period during which the residual voltage discharge pulse is applied (in the on position) is at least 50 ms, at least 100 ms, at least 300 ms, at least 500 ms, at least 1 second, or any other suitable duration. May be.

For example, for all pixel transistors, the gate line voltage relative to the source line voltage is relatively conductive compared to the non-conductive state used to isolate the pixel from the source line as part of normal active matrix drive. It can also be brought into a state of conduction by making it the values that become For an n-type thin film pixel transistor, this may be achieved by making the gate line a value substantially higher than the source line voltage value. For p-type thin film pixel transistors, this may be achieved by bringing the gate line to a value substantially lower than the source line voltage value. In an alternative embodiment, all of the pixel transistors may be brought into a conductive state by bringing the gate line voltage to zero and the source line voltage to a negative (and for p-type transistor, positive) voltage.

Alternatively, a specially designed circuit may provide for the addressing of all pixels at the same time. In standard active matrix operation, the select line control circuit typically does not cause all gate lines to be of the value that achieves the above-mentioned conduction state for all pixel transistors. A convenient way to achieve this condition is a select line with an input control line that causes an external signal to impose a condition for all select line outputs to receive the voltage supplied to a select select driver to bring the pixel transistor into a conducting state. It is provided by the driver chip. By applying an appropriate voltage value to this particular input control line, all transistors may be in a conducting state. As an example, for a display with an n-type pixel transistor, some select drivers have a "Xon" control line input. By selecting a voltage value for input to the Xon pin input to the select driver, a "gate high" voltage is routed to all select lines and all transistors are turned ON.

When the residual voltage is dissipated using these techniques, the positive to negative charge ratio experienced by, for example, an n-type transistor may vary from about 1:1000 to about 1:10 or even 1:1. Such amorphous charge bias can lead to transistor degradation and reduced display performance. With increased atypical charge biasing and transistor degradation, over time, the current and voltage ("IV") curves of the display shift in value. If the IV curve shifts to a higher value, more voltage is required to activate the transistor switch. The effect of the shift in the IV curve may be represented by optically measuring the resulting gray tone shift and the ghost shift in the display reflectance (measured as an L-star value (L*)).

Gray tone shift / ghost shift

There are usually 256 transitions that switch the display from the 16 possible gray states currently displayed on the display (including extreme black and extreme white) to the same gray state in the next image to be displayed. Gray tone shift measures 16 of these transitions. Ghost shift measures the properties of the remaining 240 transitions.

The gray tone batch ("GTP") measures the optical state resulting from applying 16 transitions to all possible gray tones (including black and white) when starting with a white image. As shown in Fig. 1A, the gray tone batch shift is the absolute value of the maximum L* shift for 16 gray tones at time (k), which may be defined by the number of sequences minus the gray tone shift at time 0. . The GTP shift, referred to herein as the gray tone shift, may also be calculated using the following equation: GTP shift (k) = max|(GTP(k)-GTP(0))|, where GTP(0) is the initial GTP and GTP(k) is the GTP measurement at time (k). GTP shift is an absolute measure of 16 transitions.

Ghosting measures the remaining 240 transitions from all possible 16 gray tones except white to all possible 16 gray tones, and subtracts the GTP value for the final displayed gray tone. That is, the ghost measurement compares the optical state of the gray tone when transitioning from the non-white gray tone to the optical state of the same gray tone when transitioning from the white color. As shown in Fig. 1B, the ghost shift is the absolute value of maximum ghosting at time (k), which may be defined by ghosting at time zero minus the number of sequences. Ghost shift may also be calculated using the following equation: ghost shift (k) = max | (Ghost (k)-Ghost (0)) |, Ghost (0) in the food is the initial ghost measurement and ghost (k) is the ghost measurement at time (k). Ghost shift is a relative measure based on GTP values.

Before taking measurements for GTP shift and ghost shift, the display was cleared by switching the display to black, white, white, white from its current state, as shown in FIGS. 10A, 10B, 11A and 11B. . However, any display clearing technique may be used as long as it is consistent so that the measured values can be compared.

The various aspects described above, as well as additional aspects, will now be described in detail below. It should be appreciated that these aspects may be used alone, all together, or in any combination of two or more, to the extent that they are not mutually exclusive.

10A is an accelerated reliability test at 45° C. measuring the optical response shift by the maximum absolute gray tone shift over the number of updates (1002) and without residual voltage discharge (1004) with residual voltage discharge in accordance with some embodiments. It is a graph showing the results. Each year of use is assumed to have 50,000 updates. As shown in Figure 10A, the additional on time experienced by the transistor as a result of residual voltage discharge (atypical charge biasing) results in a significant gray tone change of about 2 L* after about 100,000 updates (or over about 2 years). Results.

10B is an accelerated reliability test at 45° C. that measures the optical response shift by a maximum absolute ghost shift over the number of updates (1006) and without residual voltage discharge (1008), according to some embodiments. It is a graph showing the results. Each year of use is assumed to have 50,000 updates. As shown in Fig.10b, the additional on time the transistor experiences as a result of residual voltage discharge (atypical charge biasing) results in a significant ghost shift of approximately 3 L* after approximately 100,000 updates (or over approximately 2 years). do.

11A shows the maximum absolute gray for the number of updates, with residual voltage discharge (1102), without residual voltage discharge (1104), and with residual voltage discharge (1110) with the on:off ratio, according to some embodiments. It is a graph showing the result of an accelerated reliability test at 45° C. measuring the optical response shift by tone shift. Each usage year is assumed to have 50,000 updates. 11A, the additional on-time experienced by the transistor as a result of residual voltage discharge 1102 (atypical charge biasing) is after approximately 100,000 updates (or approximately 2 years) compared to no discharge 1104 update. Over) resulting in a significant gray tone shift of approximately 2 L*. If the update by residual voltage discharge is offset or normalized by turning the transistor to the off position for an additional period of time (1110), the result of a graytone shift after approximately 100,000 updates is only about 0.25 compared to an update without discharge (1104). L *.

11B shows the maximum absolute ghost shift with respect to the number of updates, with residual voltage discharge (1106), without residual voltage discharge (1108), and with residual voltage discharge (1112) of the on:off ratio, in accordance with some embodiments. It is a graph showing the result of an accelerated reliability test at 45° C. measuring the optical response shift by. Each usage year is assumed to have 50,000 updates. As shown in Figure 11B, the additional on time that the transistor experiences as a result of residual voltage discharge 1106 (atypical charge biasing) is a significant ghost of approximately 3 L* after approximately 100,000 updates (or over approximately two years). Resulting in a shift. When the update by residual voltage discharge is offset or normalized by turning the transistor to the off position for an additional period (1112), the result of a ghost shift after approximately 100,000 updates is only about 0.75L* compared to an update without discharge (1108). to be.

12A is a schematic signal-timing diagram illustrating gate voltage over time, in accordance with some embodiments. 12A shows the applied gate voltage over time for one optical update including the active update period 1202-each positive and negative transition is a single frame in a series of multiple frames during the active update period, The residual voltage discharge (on state) period 1204 and the off state period are reflected in the active matrix display having n-type transistors. In the n-type transistor, a positive gate voltage is applied to achieve the on state 1204, while a negative voltage is applied to achieve the off state 1206. In one embodiment, the active update period may be 500 ms, the on period may be 1 second, and the off period may be 2 seconds. This period of time may vary depending on the display usage and/or the number of optical updates required within a defined time period, eg, per minute, per hour, etc. As shown, a residual voltage discharge pulse (on state) 1204 is executed after an active update (ie, optical update) 302 to drain the residual charge. The off state is executed after the on state to achieve an on:off ratio close to the normal 1:1000 ratio. A 1:1000 ratio may not be achieved, but even if it is only 1:10, an on:off ratio approaching the 1:1000 ratio will reduce transistor degradation.

12B is a schematic signal-timing diagram showing multiple voltages over time by a display turning on all transistors simultaneously using an Xon connection in accordance with some embodiments. 12B is an active matrix display having an n-type transistor, applied over time for one optical update including an active update period 1202, a residual voltage discharge (on state) period 1204, and an off state period. Show the voltage diagram. The four voltages shown are the high level gate line voltage ("VDDH") 1212, the low level gate line voltage ("VEE") 1218, the front electrode voltage ("VCOM") 1216 and the Xon voltage 1214. to be. Each voltage has a separate zero voltage axis, shown as a solid gray line. The voltage above the solid gray line represents the positive voltage, and the voltage below the solid gray line represents the negative voltage. In Fig. 12B, the total gate voltage shown in Fig. 12A is a combination of VDDH and VEE voltages. The gate driver output possible voltage ("VGDOE") (not shown) controls which gate voltage (ie, VEE or VDDH) is applied. When the Xon voltage goes to ground, it activates all transistors at the same time, which turns on all transistors during the discharge period 1204. During the off-state period 1206, VDDH goes to ground, and the transistor experiences an applied VEE (negative voltage), which is controlled to approach zero towards the end of the period. By turning the transistor to its off position for an additional period of time, the on:off ratio more closely reflects its typical value of 1:1000. It is desirable to keep the on:off ratio at 1:1000, but any on:off period that shifts the ratio to its usual value even if it is only 1:10, 1:50 or 1:100 may prevent transistor degradation have.

The off period adds time to each update. Thus, the off period may be pre-allocated in a predetermined amount of time, may be determined by the controller based on the update frequency, and/or may be stopped. The off period preferably occurs after the on period, but may also occur at other times, including before the active update period. The off period may range from 500 ms to 4 seconds, preferably from 1 second to 2 seconds. Depending on the optical update time and the number of optical updates over the time period, the off period may be extended up to 10 seconds.

Further description of some embodiments

It is to be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. Reference throughout the specification to “one embodiment” or “an embodiment” or “some embodiments,” the particular feature, structure, material, or characteristic described in connection with the embodiments is included in at least one embodiment, It is meant that the phrases “in one embodiment”, “in an embodiment”, or “in some embodiments” appearing in various places throughout the specification are not necessarily included in some embodiments. It does not refer to forms.

Unless otherwise expressly required by context, throughout the disclosure, the words “comprises”, “comprising”, etc. are in an inclusive or inclusive meaning as opposed to the exclusive or complete meaning, ie, in the sense of “including but not limited to”. It must be interpreted. Additionally, the words “in this specification”, “under this specification”, “above”, “below” and similar words do not refer to this application in its entirety and to any specific parts of this application. When the word "or" is used in reference to a list of two or more items, the word covers all of the following interpretations of the word: any of the items in the list; All of the items in the list; And any combination of items in the list.

Accordingly, having described some aspects of at least one embodiment of the technology, it should be understood that various changes, modifications, and improvements will readily occur to those skilled in the art. Such variations, modifications, and improvements are intended to be within the spirit and scope of the technology. Accordingly, the foregoing description and drawings provide only non-limiting examples.

Claims (21)

An apparatus for driving an electro-optical display, comprising:
A first switch configured to supply a voltage to the electro-optical display during a first driving phase;
A first resistor coupled to the electro-optical display to discharge the voltage during a second drive phase; And
A capacitor coupled to a second switch, wherein the second switch is configured to switch between a first position and a second position, and in the first position the second switch connects the capacitor to ground to discharge the capacitor. And the second switch in the second position drives an electro-optic display, including the capacitor, coupling the capacitor to the first resistor to control the discharge of the voltage during the second driving phase Device for doing. The method of claim 1,
An apparatus for driving an electro-optical display, wherein only one of the first and second switches is engaged during the first or second driving phase. delete The method of claim 1,
And a second resistor disposed in series with the capacitor to control discharge of the voltage during the second driving phase. The method of claim 1,
The apparatus for driving an electro-optical display, wherein the electro-optical display comprises an electro-optic material comprising a rotating bichromal member or an electrochromic material. The method of claim 1,
Wherein the first and second switches are dis-engageed during a third driving phase. delete delete delete delete delete delete delete delete delete An apparatus for driving an electro-optical display, comprising:
Capacitors;
First resistance;
A first switch configured to supply a voltage to the electro-optical display during a first driving phase; And
A second switch coupled to the capacitor and the first resistor to discharge the voltage during a second driving phase, the second switch configured to switch between a first position and a second position, the first position In the second switch connects the capacitor and the first resistor to ground to discharge the capacitor, and in the second position, the second switch is configured to discharge the voltage during the second driving phase and An apparatus for driving an electro-optical display comprising the second switch coupling the first resistor to the electro-optical display. The method of claim 16,
The device for driving an electro-optical display, wherein the capacitor and the first resistor are connected in parallel. The method of claim 17,
An apparatus for driving an electro-optical display, further comprising a second resistor connected in series with the capacitor. An apparatus for driving an electro-optical display, comprising:
A first resistor connected to a first capacitor, the first resistor and the first capacitor coupled to the electro-optical display;
A second capacitor coupled to the first capacitor and the first resistor;
A first switch configured to supply a voltage to the electro-optical display during a first driving phase; And
A second switch coupled to the second capacitor, wherein the second switch is configured to switch between a first position and a second position, and in the first position the second switch is configured to discharge the second capacitor Connecting the second capacitor to ground, and in the second position the second switch couples the second capacitor to the first resistor to control discharge of the voltage during a second driving phase. An apparatus for driving an electro-optical display comprising a switch. delete delete

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