KR102104979B1 - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register capable of preventing multi-output of a carry signal by maintaining a stable gate-off voltage for the carry signal, and a display device using the same, wherein a front end stage and a rear end portion sharing the QB nodes with each other in the shift register of the present invention Each stage includes a carry output unit; A scan output unit; Q node charging unit; It has a Q node discharge section. One of the front and rear stages further includes a QB_ODD charging unit for charging the QB_ODD node and a QB_ODD discharge unit for discharging the QB_ODD node in response to control of the Q node of the front and rear stages; The other stage further includes a QB_EVEN charging unit for charging the QB_EVEN node and a QB_EVEN discharge unit for discharging the QB_EVEN node in response to control of the Q node of the front and rear stages. The rear stage further includes a stabilization switch, and the stabilization switch is controlled by a charge control signal applied to the Q node charging section of the front stage, and when the Q node of the rear stage is precharged, the first gate is used as the carry signal of the rear stage. Supply off voltage.

Description

SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME

The present invention relates to a shift register, and more particularly, to a shift register capable of preventing multiple outputs of carry signals and a display device using the same.

The liquid crystal display device displays an image using electrical and optical characteristics of the liquid crystal. The liquid crystal has different anisotropy properties, such as refractive index and dielectric constant, depending on the major and minor axis directions of the molecule, and can easily adjust the molecular arrangement and optical properties. A liquid crystal display using the same displays an image by controlling the light transmittance through the polarizing plate by changing the arrangement direction of the liquid crystal molecules according to the size of the electric field.

The liquid crystal display device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix, a backlight unit that supplies light to the liquid crystal panel, a gate driver that drives the gate line of the liquid crystal panel, and a data driver that drives the data line of the liquid crystal panel. And a backlight driver for driving the backlight unit, a timing controller for controlling the driving of the drivers, and a power supply for supplying all the power required by the liquid crystal display.

The gate driver has a shift register that outputs scan pulses for sequentially driving the gate lines of the liquid crystal panel as a basic configuration. Recently, the gate driver is mainly formed using a thin film transistor (TFT) array, and thus a gate-in-panel (GIP) method embedded in a liquid crystal panel is mainly used.

The shift register of the gate driver has a plurality of stages connected to each other. The output of each stage is supplied as a scan pulse to each gate line, as well as a carry signal to other stages.

In each of the recent stages, the output node is separated for scanning and carry, thereby reducing the delay time (ie, rising time) of the carry signal, and the technique in which two adjacent stages share the QB node controlling the pull-down transistor with each other. Is being applied.

However, in one of the stages sharing the QB node, when the carry signal is a floating gate-off (gate low) voltage, the Q node is precharged and the carry signal is abnormally raised due to the parasitic capacitance of the pull-up transistor. There is a problem in that multi-output of a carry signal is generated.

Accordingly, the multi-output of a carry signal generated in one stage of a pair of stages sharing a QB node is different from the Q node in another stage that uses the carry signal as a discharge control signal and the other referred to as a charging control signal. By generating the voltage loss of the QB node on the stage, there is a problem in that a voltage deviation between gate lines occurs, resulting in deterioration of image quality such as flicker.

On the other hand, the above-described problems of the shift register may occur in the same way as other liquid crystal display devices, as well as other display devices using shift registers, for example, organic light emitting diode (OLED) display devices and electrophoretic display devices (EPDs).

The present invention has been devised to solve the above-described problems, and a problem to be solved by the present invention is to provide a shift register capable of preventing multi-output of a carry signal by maintaining a stable gate-off voltage and a display device using the same. Is to provide.

In order to solve the above problems, the shift register according to an embodiment of the present invention includes a plurality of stages sequentially outputting a plurality of scan signals and carry signals; Multiple stages are grouped into two units that share QB nodes with each other; A pair of stages sharing a QB node with each other has a front stage and a rear stage.

Each of the front and rear stages includes: a carry output unit that outputs an input clock signal as a carry signal in response to control of the Q node, and outputs a first gate-off voltage as a carry signal in response to control of the QB node; A scan output unit outputting an input clock signal as a scan signal in response to control of the Q node, and outputting a second gate-off voltage as a scan signal in response to control of the QB node; A Q node charging unit charging the Q node in response to a charge control signal using a carry signal output from one of the previous stages; And a Q node discharge unit for discharging the Q node in response to control of a discharge control signal using a carry signal output from one of the next stages. The QB nodes shared by the front and rear stages include QB_ODD nodes and QB_EVEN nodes that are alternately driven for each frame; One of the front and rear stages further includes a QB_ODD charging unit for charging the QB_ODD node and a QB_ODD discharge unit for discharging the QB_ODD node in response to control of the Q node of the front and rear stages; The other stage further includes a QB_EVEN charging unit for charging the QB_EVEN node and a QB_EVEN discharge unit for discharging the QB_EVEN node in response to control of the Q node of the front and rear stages. The rear stage further includes a stabilization switch, and the stabilization switch is controlled by a charge control signal applied to the Q node charging section of the front stage, and when the Q node of the rear stage is precharged, the first gate is used as the carry signal of the rear stage. Supply off voltage.

The scan output unit includes: a first pull-up transistor configured to output an input clock signal of the corresponding stage as a scan signal of the corresponding stage under control of a Q node of the corresponding stage; The first-first and first-second pull-down transistors output the second gate-off voltage as a scan signal of a corresponding stage under the control of each of the QB_ODD node and the QB_EVEN node.

A second pull-up transistor for outputting an input clock signal of the corresponding stage as a carry signal of the corresponding stage under control of a Q node of the corresponding stage; It is provided with 2-1 and 2-2 pull-down transistors that output the first gate-off voltage as a carry signal of the corresponding stage under the control of each of the QB_ODD node and the QB_EVEN node.

The stabilization switch of the rear stage supplies the first gate-off voltage to the output nodes of the 2-1 and 2-2 pull-down transistors of the rear stage.

The Q node charging unit includes a first transistor that supplies the gate-on voltage to the Q node by controlling the charge control signal.

The Q-node discharge section includes a 3-1 transistor that supplies a first gate-off voltage to the Q node under control of a discharge control signal; 3-3 and 3-3 transistors for supplying the first gate-off voltage to the Q node under the control of the QB_ODD node and the QB_EVEN node respectively; A third to fourth transistor may be further provided to supply the first gate-off voltage to the Q node in response to an external reset signal.

Each of the QB_ODD charging unit and the QB_EVEN charging unit includes a 4-1 transistor that supplies an AC gate-on voltage to a QB_ODD or QB_EVEN node; A 4-2 transistor connected in a diode type between the supply line supplying the AC gate-on voltage and the control node of the 4-1 transistor; A 4-3 transistor supplying a first gate-off voltage to the control node under control of a Q node of the corresponding stage; A fourth to fourth transistor is provided to supply the first gate-off voltage to the control node by controlling the Q node of the other stage except the corresponding stage among the pair of stages.

Each of the QB_ODD discharge unit and the QB_EVEN discharge unit includes a 5-1 transistor that supplies a first gate-off voltage to a QB_ODD or QB_EVEN node in response to a charge control signal applied to a front stage; And a 5-2 transistor for supplying the first gate-off voltage to the QB_ODD or QB_EVEN node under the control of the Q node of the corresponding stage.
In the turn-on period of the stabilization switch of the rear stage, before the carry signal of the rear stage outputs the gate-on voltage, the Q node charging section of the rear stage responds to the carry signal of the front stage to precharge the Q node of the rear stage. Overlaps with the period.

The display device according to the exemplary embodiment of the present invention drives the gate line of the display panel using the shift register.

The shift register according to the present invention and the display device using the same include a stable gate-off voltage for which a carry signal is stable by adding a stabilizing transistor that applies a gate-off voltage to a carry signal when the Q2 node is precharged to a rear stage of a stage sharing a QB node. By maintaining, it is possible to prevent the multi-output of the carry signal.

Accordingly, the present invention prevents voltage deviation due to abnormal carry signals in other stages using a carry signal as a control signal, thereby preventing voltage deviation between the gate lines driven by the front and rear stages, and preventing flicker and the like, thereby improving image quality. Improve it.

1 is a block diagram showing a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram showing a shift register of the gate driver shown in FIG. 1.
3 is a circuit diagram showing a pair of stages representing a shift register according to an embodiment of the present invention.
FIG. 4 is a driving waveform diagram of the pair stage shown in FIG. 3.
5A and 5B are waveform diagrams comparing and comparing carry signals before and after the stabilization transistor T6 is applied to the rear stage shown in FIG. 3.
FIG. 6 is a waveform diagram showing the comparison of Q node potentials before and after the stabilization transistor T6 is applied to the rear stage shown in FIG. 3.
7 is a waveform diagram showing a comparison of QB node potentials before and after the stabilization transistor T6 is applied to the rear stage shown in FIG. 3.
8 is a diagram showing the potential of the Q2 node according to the channel width size of the second pull-up transistor in the rear stage shown in FIG. 3.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

The display device shown in FIG. 1 includes a display panel 100, a gate driver 120, a data driver 130, a timing controller 140, and the like.

The display panel 100 includes gate lines GL and data lines DL intersecting each other, and a matrix pixel array. The display panel 100 includes a display area 110 displaying an image through a pixel array and a non-display area around the display area 110. Each pixel of the display area 110 usually implements a desired color with a combination of R (Red), G (Green), and B (Blue) subpixels, and additionally includes a W (White) subpixel for luminance enhancement. do.

A liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display (EPD), or the like may be used as the display panel 100. Hereinafter, for convenience, the case where the LCD is applied to the display panel 100 will be described as an example.

When the display panel 100 is an LCD, the upper substrate and the lower substrate are formed by bonding the liquid crystal layer therebetween. A color filter array is formed on one of the upper and lower substrates, and a thin film transistor array is formed on the other substrate. Polarizing plates are attached to the outer surfaces of the upper and lower substrates, respectively. An alignment film for setting a pretilt angle of the liquid crystal is formed on each of the inner surfaces of the upper and lower substrates that are in contact with the liquid crystal. Each sub-pixel of the display area 100A includes a TFT connected to the gate line GL and the data line DL, a liquid crystal capacitor connected to the TFT in parallel, and a storage capacitor. The liquid crystal capacitor charges a difference voltage between the data signal supplied to the pixel electrode through the TFT and the common voltage supplied to the common electrode, and drives the liquid crystal according to the charged voltage to adjust the light transmittance. The storage capacitor keeps the voltage charged in the liquid crystal capacitor stable. The liquid crystal layer is driven by a vertical electric field such as a twisted nematic (TN) mode or a vertical alignment (VA) mode, or a horizontal electric field such as an in-plane switching (IPS) mode or a fringe field switching (FSF) mode.

The timing controller 140 inputs a plurality of synchronization signals together with image data supplied from an external host set. The plurality of synchronization signals may include a dot clock and data enable signal, or may further include a horizontal synchronization signal and a vertical synchronization signal. The timing controller 140 corrects the data input from the host set using various data processing methods for improving image quality or reducing power consumption, and outputs the data to the data driver 130.

The timing controller 140 generates a data control signal for controlling the driving timing of the data driver 130 and a gate control signal for controlling the driving timing of the gate driver 120 using the synchronization signals. The data control signal includes a source start pulse and a source sampling clock that control the latch of the data signal, a polarity control signal that controls the polarity of the data signal, and a source output enable signal that controls the output period of the data signal. The gate control signal may include a gate start pulse and a gate shift clock to control scanning of the gate signal, and may further include a gate output enable signal to control the output period of the gate signal.

The data driver 130 supplies image data from the timing controller 140 to a plurality of data lines DL of the liquid crystal panel 100 in response to a data control signal from the timing controller 140. The data driver 130 converts data from the timing controller 140 to an analog data signal using a gamma voltage from a gamma voltage generator (not shown), and data signals each time each gate line GL is driven. To the data line DL. The data driver 130 is composed of at least one data IC, and is mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), or a flexible print circuit (FPC), and the TAB (tape) is applied to the liquid crystal panel 100 It may be attached by an Automatic Bonding (COG) method, or may be mounted on the liquid crystal panel 100 by a COG (Chip On Glass) method.

The gate driver 120 sequentially drives the gate lines GL of the liquid crystal panel 100 in response to the gate control signal from the timing controller 140. The gate driver 120 enables a scan pulse of the gate-on voltage (gate high voltage) in the scan period of each gate line GL to enable the gate line GL, and the gate-off voltage (gate low voltage) in the remaining periods. ) To disable the gate line GL. In the scan pulse supplied to each gate line GL, adjacent scan pulses and a portion of the pulse width may overlap each other.

The gate driver 120 may be formed in a GIP type embedded in the display panel 100 by being formed in a non-display region of the TFT substrate together with a TFT array formed in the display region 110 of the display panel 100. The GIP type gate driver 120 may be formed on one side of the display area 110 or may be formed on both sides of the display area 110 as shown in FIG. 1. Each of the GIP type gate drivers 120 formed on both sides of the display area 100 scans the gate lines GL by separating them into odd gate lines and even gate lines, or scanning the gate lines GL. You can scan the same on both sides.

The GIP type gate driver 120 includes a shift register, and a level shifter 150 may be additionally provided between the timing controller 140 and the gate driver 120. The level shifter 150 displays a gate control signal from the timing controller 140, that is, a start pulse and a TTL (Transistor Transistor Logic) voltage of multiple clocks, a gate high voltage (Vgh) and a gate for driving a TFT of the display panel 100 Level shifting is performed with a low voltage Vgl to supply a shift resistor that is the gate driver 120. The level shifter 150 may be built in the power supply IC.

Alternatively, the gate driver 120 is composed of at least one gate IC including a shift register and a level shifter, and is mounted on a circuit film such as TCP, COF, FPC, etc. to be attached to the liquid crystal panel 100 in a TAB method, or COG It may be mounted on the liquid crystal panel 100 in a manner.

2 is a block diagram illustrating a shift register according to an embodiment of the present invention applied to the gate driver shown in FIG. 1.

In FIG. 1, when both gate drivers 120 drive the gate lines by separating them into odd gate lines and even gate lines, the shift register SR configured in one side gate driver 120 may be odd gate lines or even gates. It may be composed of a plurality of stages (..., STn-4, STn-2, STn, STn + 2, ...; n is a natural number) for sequentially scanning lines. Alternatively, the shift register SR may be composed of a plurality of stages (..., STn-2, STn-1, STn, STn + 1, ...) for sequentially scanning all gate lines. .

At least two phase clock signals CLKn and CLKn + 2 having a phase difference are supplied to the shift register SR. As the two-phase clock pulses CLKn and CLKn + 2 alternate, one clock signal is supplied to each stage. Alternatively, one clock signal may be supplied for each stage while the four-phase clock signals alternate.

The shift register SR shown in FIG. 2 is set in accordance with the carry signal Cn-2 from the previous stage STn-2 in which the stage STn is set, and the next stage STn + 4 ; Not shown), it is reset according to the carry signal Cn + 2. However, the shift register according to the present invention can be applied even when an arbitrary stage is set by a carry signal of one of the previous stages and reset in response to a carry signal of any of the next stages.

The shift register SR according to the present invention has a structure in which a plurality of stages share QB nodes (QB_ODD and QB_EVEN nodes) that control a pull-down transistor in units of two. For example, the n-th stage STn-4 and the n-th stage STn-4 and STn-2 share the QB nodes with each other, and the n-th stage STn and the n + 2 stage ( STn, STn + 2) share QB nodes with each other.

3 is a circuit diagram showing a detailed configuration of a stage according to an embodiment of the present invention, and is a circuit diagram showing a detailed configuration of a pair of stages STn and STn + 2 sharing a QB node among a plurality of stages shown in FIG. 2. .

A pair of adjacent stages STn and STn + 2 output scan signals Vout (n) and Vout (n + 2) to two gate lines GLn and GLn + 2, respectively, and control other stages. The carry signals Cn and Cn + 2 used as signals are respectively output.

Each of the two stages STn and STn + 2 includes a control unit 10 that controls the Q nodes Q1 and Q2, and a QB node (QB_ODD and QB_EVEN), and a first output node N1 under control of the control unit 10 ), The scan output unit 30 for outputting the scan signal Vout, and the carry output unit 20 for outputting the carry signal C through the second output node N2 under the control of the control unit 10 It is provided. The adjacent pair of stages STn and STn + 2 share the QB_ODD nodes with each other and the QB_EVEN nodes with each other.

The scan output unit 30 outputs a scan signal Vout (n) to the first output node N1 in response to control of the Q nodes Q1 and Q2 and the QB nodes QB_ODD and QB_EVEN, and the scan signal (Vout (n)) is supplied to the gate line via the first output node N1. The scan output unit 30 includes a first pull-up transistor Tup1 that supplies a clock signal CLKn to the first output node N1 under the control of the Q nodes Q1 and Q2, and each of the QB_ODD node and QB_EVEN node. A 1-1 pull-down transistor Tpd11 and a 1-2 pull-down transistor Tpd12 are provided to supply the second low potential power supply VSS2 to the first output node N1 by control. Under the control of the QB_ODD node and the QB_EVEN node, the 1-1 pull-down transistor Tpd11 and the 1-2 pull-down transistor Tpd12 are alternately driven for each frame.

 The carry output unit 20 outputs a carry signal Cn to the second output node N2 in response to the control of the Q nodes Q1 and Q2 and the QB nodes QB_ODD and QB_EVEN, and the carry signal Cn is It is supplied as a control signal of another stage via the second output node N2. For example, the carry signal Cn output from one stage STn is supplied as a control signal for controlling the charging of the Q node of the next stage STn + 2, and the preceding stage STn-4 (not shown) ) Is supplied as a control signal to control the Q node discharge. The carry output unit 20 includes a second pull-up transistor Tup2 that supplies the clock signal CLKn to the second output node N2 under the control of the Q nodes Q1 and Q2, and each of the QB_ODD node and QB_EVEN node. A 2-1 pull-down transistor Tpd21 and a 2-2 pull-down transistor Tpd22 that supply the first low potential power supply VSS1 to the second output node N2 by control are provided. Under the control of the QB_ODD node and the QB_EVEN node, the 2-1 pull-down transistor Tpd21 and the 2-2 pull-down transistor Tpd22 are alternately driven for each frame.

The control unit 10 controls the Q node Q1, Q2, QB node (QB_ODD, QB_EVEN), the Q node charging unit 12, the Q node discharging unit 14, the QB node charging unit 16, and the QB node discharging unit (18).

The Q node charging unit 12 includes a first transistor T1, and the first transistor T1 supplies the high potential power supply VDD to the Q node Q1 by controlling the carry signal Cn-2 of the previous stage. , Q2) to charge the Q nodes Q1 and Q2 with the on voltage. The carry signal controlling the first transistor T1 is not limited to the carry signal Cn-2 of the previous stage, and a carry signal output from any one of the previous stages may be used. The first transistor T1 of the first stage (not shown) is controlled by a start pulse.

In contrast to the Q node charging unit 12, the Q node discharging unit 14 supplies the first low potential voltage VSS1 to the Q nodes Q1 and Q2 to discharge the Q nodes Q1 and Q2 to an off voltage. The Q-node discharge unit 14 includes a 3-1 transistor T31, a 3-2 transistor T32, a 3-3 transistor T33, and a 3-4 transistor T34 additionally. It can be provided.

The 3-1 transistor T31 supplies the first low potential voltage VSS1 to the Q nodes Q1 and Q2 in response to the carry signal Cn + 4 of the next stage. The carry signal controlling the 3-1 transistor T31 is not limited to the carry signal Cn + 4 of the multi-stage stage, and a carry signal output from any one of the following stages may be used. The 3-2 transistor T32 and the 3-3 transistor T33 supply the first low potential voltage VSS1 to the Q nodes Q1 and Q2 under the control of the QB_ODD and QB_EVEN nodes, respectively. The 3-4 transistor T34 supplies the first low potential voltage VSS1 to the Q nodes Q1 and Q2 by controlling the reset signal RST supplied from frame to frame.

The QB node charging unit 16 is a QB_ODD node charging unit 16_O that supplies the odd AC power (VDD_O) to the QB_ODD node in the odd frame, and a QB_EVEN node charging unit (16_E) that supplies the even AC power (VDD_E) in the even frame to the QB_EVEN node. ). Since the pair of stages STn and STn + 2 share the QB_ODD node and the QB_EVEN node, the QB_ODD node charging unit 16_O is formed on one of the pair of stages STn and STn + 2, The QB_EVEN node charging section 16_E is formed on another stage. In other words, the QB_ODD node charging unit 16_O provided in one stage STn is commonly connected to the QB_ODD nodes of the two stages STn, STn + 2, and the QB_EVEN node charging unit provided in the other stage STn + 2. (16_E) is commonly connected to the QB_EVEN nodes of the two stages STn and STn + 2.

The QB_ODD node charging unit 16_O controls the 4-1 transistor T41_0 and the 4-1 transistor T41_0 supplying the odd AC power supply VDD_O to the QB_ODD nodes of the two stages STn, STn + 2. 4-2 transistors (T42_O), 4-3 transistors (T43_O), and 4-4 odd transistors (T44_O) are provided.

The 4-1 transistor T41_O supplies the odd AC power supply VDD_O to the QB_ODD nodes of the two stages STn and STn + 2 under the control of the control node N_O.

The 4-2 transistor T42_O is connected in a diode type between the supply line of the odd AC power supply VDD_O and the control node N_O to supply the odd AC power supply VDD_O to the control node N_O.

The 4-3 transistor T43_O supplies the first low potential power source VSS1 to the control node N_O under the control of the Q1 node of the front end stage STn.

The 4-4th transistor T44_O supplies the first low potential power source VSS1 to the control node N_O under the control of the Q2 node of the rear stage STn + 2.

The QB_EVEN node charging unit 16_E controls the 4-1 transistor T41_E and the 4-1 transistor T41_E that supply the even AC power supply VDD_E to the QB_EVEN node of the two stages STn, STn + 2. 4-4 transistors (T42_E), 4-3 transistors (T43_E), and 4-4 transistors (T44_E) are provided.

The 4-1 transistor T41_E supplies the even AC power supply VDD_E to the QB_EVEN nodes of the two stages STn and STn + 2 under the control of the even control node N_E.

The 4-2 transistor T42_E is connected in a diode type between the supply line of the even AC power supply VDD_E and the control node N_E to supply the even AC power supply VDD_E to the control node N_E.

The 4-3 transistor T43_E supplies the first low potential power source VSS1 to the control node N_E by controlling the Q2 node of the rear stage STn + 2.

The 4-4 transistor T44_E supplies the first low potential power source VSS1 to the control node N_E by controlling the Q1 node of the front end stage STn.

The QB node discharge unit 18 includes a QB_ODD node discharge unit 18_O that supplies the first low potential power VSS1 to the QB_ODD node, and a QB_EVEN node discharge unit that supplies the first low potential power VSS1 to the QB_EVEN node. 18_E). Since the pair of stages STn and STn + 2 share the QB_ODD node and the QB_EVEN node, the QB_ODD node discharge unit 18_O is formed on one of the two stages STn and STn + 2, The QB_EVEN node discharge section 18_E is formed on another stage. In other words, the QB_ODD node discharge unit 18_O provided in one stage STn is commonly connected to the QB_ODD nodes of the two stages STn, STn + 2, and the QB_EVEN node provided in the other stage STn + 2. The discharge section 18_E is commonly connected to the QB_EVEN nodes of the two stages STn, STn + 2.

The QB_ODD node discharge unit 18_O includes a 5-1 transistor T51_0 that supplies the first low potential power supply VSS1 to the QB_ODD nodes of the two stages STn and STn + 2 under the control of the Q1 node, and 2 Among the stages STn and STn + 2, the first low potential power supply VSS1 is divided into two stages STn by the control of the carry signal Cn-2 which controls the first transistor T1 of the preceding stage STn. , 5th transistor T52_0 to be supplied to the QB_ODD node of STn + 2).

The QB_EVEN node discharge unit 18_E includes a 5-1 transistor T51_E that supplies the first low potential power supply VSS1 to the QB_ODD nodes of the two stages STn, STn + 2 under the control of the Q2 node, and 2 Among the stages STn and STn + 2, the first low potential power supply VSS1 is divided into two stages STn by the control of the carry signal Cn-2 which controls the first transistor T1 of the preceding stage STn. , 5th transistor T52_E to be supplied to the QB_EVEN node of STn + 2).

Particularly, the shift register according to the present invention has a pair of stages STn, STn + 2, and a rear stage STn + 2 has a gate-off voltage when the carry signal Cn-2 is floating when the Q2 node is precharged. In order to prevent this, the first low potential power supply VSS1 is applied to the second output node N2 by the control of the carry signal Cn-2 that controls the first transistor T1 of the front end stage STn. A stabilizing transistor T6 to be supplied is provided. Accordingly, the second output node N2 is not floated by the stabilizing transistor T6 in the period in which the Q2 node is precharged in the rear stage STn + 2 and the stable first low potential power source VSS1 is carried by the carry signal ( With the gate-off voltage of Cn-1) By outputting, it is possible to prevent multiple outputs of the carry signal Cn-1.

4 is a diagram showing driving waveforms of the two stages STn and STn + 3 shown in FIG. 3.

Two-phase clock signals CLKn and CLKn + 2 are supplied to the two stages STn and STn + 3, respectively. For example, the two-phase clock signals CLKn and CLKn + 2 have a period of 6H, and the gate-on voltage Von of the 3H period and the gate-off voltage Voff1 of the 3H period are alternately repeated. In the two-phase clock signals CLKn and CLKn + 2, the 1H period of the gate-on voltage Von overlaps each other, and the 1H period of the gate-off voltage Voff also overlaps each other.

In FIG. 3, the high potential power VDD and the high potentials of the AC power sources VDD_O and VDD_E may correspond to the gate-on voltage Von. The first and second low potential power sources VSS1 and VSS2 may correspond to the first and second gate off voltages Voff1 and Voff2, respectively, and the second low potential power source VSS2 is the first low potential power source VSS1. It may be a lower voltage.

In the two stages STn, STn + 3, the front stage STn is charged with the ON voltage by the carry signal Cn-2 from the previous stage STn-2, and the clock signal CLKn is charged. One pulse is output as the scan signal Vout (n) and the carry signal Cn. In the rear stage STn + 2, the Q2 node is charged with the on voltage by the carry signal Cn from the front stage STn, and scans one pulse of the clock signal CLKn + 1 (Vout (n + 2) )) And carry signal (Cn + 2). The scan signal Vout (n + 2) output from the rear stage STn + 2 and the scan signal Vout (n) from which the gate-on voltage Von of the carry signal Cn + 2 is output from the previous stage STn + 2 )) And the gate-on voltage Von of the carry signal Cn overlap with the 1H period.

Hereinafter, an operation process of the two stages STn and STn + 3 will be described in detail with reference to FIGS. 3 and 4. Referring to FIG. 4, the QB nodes QB_ODD and QB_EVEN are turned off only in the enable period EN in which the Q1 and Q2 nodes of the two stages STn and STn + 3 are charged with the on voltage, and in the remaining periods It can be seen that the voltage is on.

In the first period (t1), the previous-stage carry signal the first transistor (T1) of the front end stage (STn) of the two stages (STn, STn + 2) by a gate-on voltage (Von) in the (Cn-2) , The 5-1 odd transistor T51_O and the 5-1 even transistor T51_E of the rear stage STn + 2 are turned on. Accordingly, the Q1 node is precharged with the on voltage, and the QB_ODD node and the QB_EVEN node are discharged from the previous on voltage to the off voltage.

The first and second pull-up transistors Tup1 and Tup2 of the front end stage STn are turned on by the control of the precharged Q1 node, so that the gate-off voltage Voff1 of the clock signal CLKn is first and second. The output signals N1 and N2 are output to the scan signal Vout (n) and the carry signal Cn of the front end stage STn, respectively.

The 4-3 odd transistor T43_0 and the 4-3 even transistor T43_E are turned on by the control of the precharged Q1 node, so that the 4-1 odd transistor T41_0 and the 4-1 even transistor (T41_E) is turned off, and the 5-1 odd transistor T51_O and the 5-1 even transistor T51_E are turned on, so that the QB_ODD node and the QB_EVEN node are discharged from the previous on voltage to the off voltage, so that the full- The down transistors Tpd11, Tpd12, Tpd21, Tpd22 are turned off.

The rear stage STn + 2 outputs the scan signals Vout (n + 2) and the carry signals Cn + 2 of the gate-off voltages Voff2 and Voff1 as before.

In the second period t2 , since the gate-on voltage Von of the previous carry signal Cn-2 is maintained, the front-end stage STn operates in the same manner as the first period t1 to gate off. The scan signal Vout (n) and the carry signal Cn of the voltage Voff1 are output.

The rear stage STn + 2 outputs the scan signals Vout (n + 2) and the carry signals Cn + 2 of the gate-off voltages Voff2 and Voff1 as before.

In the third period ( t3 ) , the previous-stage carry signal Cn-2 maintains the gate-on voltage Von, and the gate-on voltage Von of the clock signal CLKn supplied to the previous stage STn. The on-voltage of the Q1 node is amplified by bootstrapping, so that the gate-on voltage Von of the clock signal CLKn is stably turned on through the first and second pull-up transistors Tup1 and Tup2 that are stably turned on. ) Are output as scan signals Vout (n) and carry signals Cn, respectively.

In the third period t3, since the gate-on voltage Von of the front-end carry signal Cn and the gate-low voltage Voff1 of the clock signal CLKn + 2 are supplied to the rear stage STn-2, the above In the same manner as the operation of the front end stage STn in the first period t1, the Q2 node is precharged with the on voltage. Since the QB_ODD node and the QB_EVEN node are in an off voltage state, the pull-down transistors Tpd11, Tpd12, Tpd21, Tpd22 of the rear stage STn-2 are turned off. For this reason, the carry signal Cn + 2 of the rear stage STn-2 is floating at the gate-off voltage Voff1.

At this time, the gate low voltage Voff1 of the carry signal Cn + 2 floating by the parasitic capacitance Cgs of the second pull-up transistor Tpd21 while the Q2 node of the rear stage STn-2 is precharged. When the phosphorus rises abnormally, a multi-output of the carry signal Cn + 2 may occur as shown in FIG. 5A.

However, in the present invention, the stabilizing transistor T6 is additionally provided in the rear stage STn-2, so that the previous stage carry signal supplied to the front stage STn in the third period t3 when the Q2 node is precharged ( When the stabilization transistor T6 is turned on by Cn), the first low potential power supply VSS1 is stably supplied as the carry signal Cn + 2 of the second output node N2 as shown in FIG. 5B. . As a result, the rear stage STn-2 is able to stably maintain the gate low voltage Voff1 of the carry signal Cn + 2 as shown in FIG. 5B by the stabilization switch T6 even when the Q2 node is precharged. Can improve the multi output of.

In the fourth time period (t4), the previous stage is a carry signal (Cn-2) supplied to the gate-off voltage (Voff1) the first transistor (T1) is turned off, the result Q1 node clock signal (CLKn) Floating by the amplified on-voltage state according to the gate-on voltage Von of the scan signal Vout () through the first and second pull-up transistors Tup1 and Tup2 of the front stage STn maintaining the turn-on state. n)) and the carry signal Cn maintain the gate-on voltage Von of the clock signal CLKn.

The pull-down transistors Tpd11, Tpd12, Tpd21, Tpd22 are turned off by the off voltages of the QB_ODD node and the QB_EVEN node.

In the fourth period t4, since the gate-on voltage Von of the front-end carry signal Cn and the gate low voltage Voff1 of the clock signal CLKn + 2 are supplied to the rear-stage STn-2, the rear-stage stage (STn-2) operates in the same manner as the front end stage STn in the second period t2 to scan the scan signal Vout (n + 2) and the carry signal Cn + 2 of the gate-off voltage Voff1. Output.

In the fifth period ( t5 ) , the Q1 node of the front stage STn maintains a floating state of the amplified on voltage in the same manner as the fourth period t4, so that the scan signal Vout () of the front stage STn is maintained. n)) and the carry signal Cn maintain the gate-on voltage Von of the clock signal CLKn as in the fourth period t4.

In the fifth period t5, the rear stage STn-2 operates in the same manner as the previous stage STn in the third period t3 and has a gate-on voltage Von of the clock signal CLKn + 2. The scan signal Vout (n + 2) and the carry signal Cn + 2 are output.

In the sixth period t6 , the Q1 node of the front end stage STn is in a floating state of the on voltage, and the gate off voltage Voff1 is supplied to the clock signal CLKn, so that the first and second pull-up transistors Tup1 , The gate-off voltage Voff1 of the clock signal CLKn is output to the scan signal Vout (n) and the carry signal Cn through Tup2, respectively. Then, the floating Q1 node is discharged along the gate-off voltage Voff1 of the clock signal CLKn.

In the sixth period t6, the rear stage STn-2 operates in the same manner as the previous stage STn in the fourth period t4, and thus the scan signal Vout (n + 2) of the gate-on voltage Von. ) And carry signal (Cn + 2).

In the seventh period (t7), the next scan signal (Vout (n)) of the front end stage (STn) is reset gate-off voltage (Voff1) by the carry signals (Cn + 4) from the single stage and a carry signal Each of (Cn) is output, and the rear stage STn-2 operates in the same manner as the previous stage STn in the fifth period t5 to scan signal Vout (n + 2) of the gate-on voltage Von. )) And carry signal (Cn + 2).

Since the Q1 and Q2 nodes are discharged to the off voltage after the seventh period t7, the fourth-3 transistors T43_O, T43_E and the fourth-4 transistors T44_O, T44_E are turned off, and accordingly, the turned-on node Since the QB node (QB_ODD, QB_EVEN) is charged to the on voltage through the 4-1 transistors (T41_O, T41_E), the scan signal of the front end stage (STn) through the turned-on pull-down transistors (Tpd11, Tpd12, Tpd21, Tpd22) (Vout (n)) and the carry signal Cn, and the scan signal Vout (n + 2) and the carry signal Cn + 2 of the rear stage STn + 2 determine the gate-off voltages Voff1 and Voff2. To maintain.

At this time, since the QB_ODD node and the QB_EVEN node alternately for each frame by the alternating current alternating power (VDD_O) and even alternating power (VDD_E) alternating high potentials in units of frames, the 1-1, 2-1 pulldown transistor ( Tpd11, Tpd21, and the 1-2, 2-2 pull-down transistors Tpd12, Tpd22 are alternately driven for each frame to minimize characteristic changes due to stress of the pull-down transistors Tpd11, Tpd12, Tpd21, Tpd22. You can.

5A and 5B are waveform diagrams comparing and comparing carry signals Cn + 2 before and after the stabilization transistor T6 is applied to the rear stage STn + 2 shown in FIG. 3.

Referring to FIG. 5A, when the stabilization transistor T6 is not applied to the rear stage STn + 2, the carry signal Cn + 2 of the rear stage STn-2 in the period t3 is the gate-off voltage Voff1. In the floating state, the gate low voltage Voff1 of the carry signal Cn + 2 is abnormally raised by the Q2 node due to the parasitic capacitance Cgs of the precharging and pull-up transistor Tpd21, and thus the carry signal Cn It can be seen that multi-output of +2) occurs.

Referring to FIG. 5B, when the stabilization transistor T6 is applied to the rear stage STn-2 in the present invention, the second is performed by the stabilization transistor T6 turned on by the previous stage carry signal Cn in a period t3. Since the first low potential power supply VSS1 is stably supplied to the output node N2, even if the Q2 node is precharged, the carry signal Cn + 2 maintains the gate low voltage Voff1 stably to multi-output the carry signal. It can be seen that this has been improved.

FIG. 6 is a waveform diagram showing a comparison of Q node potentials before and after the stabilization transistor T6 is applied to the rear stage STn + 2 shown in FIG. 3.

Specifically, FIG. 6 shows the Q2 node potential of the preceding stage STn-2 to which the carry signal Cn + 2 output from the rear stage STn + 2 is applied as a discharge control signal, and the preceding stage STn. -2) shows the Q1 node potential of the stage (STn-4) sharing the QB node.

Referring to FIG. 6, when the stabilization transistor T6 is not applied to the rear stage STn + 2, as described above, when the Q2 node of the subsequent stage STn + 2 precharges, the rear stage STn + A multi-output occurs in the carry signal Cn + 2 output from 2), and the multi-output of the carry signal Cn + 2 is a front-end stage in which the carry signal Cn + 2 is applied as a discharge control signal. By influencing the Q2 node of (STn-2), it can be seen that the potential of the Q2 node of the preceding stage STn-2 is lost.

However, when the stabilization transistor T6 is applied to the rear stage STn-2 in the present invention, the carry signal Cn + 2 output from the rear stage STn + 2 is stabilized by the gate-off voltage without multi-output, thereby In the front-end stage STn-2 to which the carry signal Cn + 2 is applied, it can be seen that the Q2 node potential is stabilized without voltage loss. Therefore, it is understood that the voltage deviation between the Q2 node of the front-end stage STn-2 and the Q1 node of the stage STn-4 sharing the front-end stage STn-2 and the QB node can be prevented. You can.

7 is a waveform diagram showing a comparison of QB node potentials before and after the stabilization transistor T6 is applied to the rear stage STn + 2 shown in FIG. 3.

Specifically, specifically, FIG. 6 shows the potential of the QB node of the next stage STn + 4 to which the carry signal Cn + 2 output from the rear stage STn + 2 is applied as a control signal for charging.

Referring to FIG. 7, when the stabilizing transistor T6 is not applied to the rear stage STn + 2, as described above, when the Q2 node of the subsequent stage STn + 2 precharges, the rear stage STn + Multi-output occurs in the carry signal (Cn + 2) output from 2), and the multi-output of the carry signal (Cn + 2) is the next stage where the carry signal (Cn + 2) is applied as a charging control signal. By influencing (STn + 4), it can be seen that the potential of the QB node is lost in the next stage STn + 4.

However, when the stabilization transistor T6 is applied to the rear stage STn-2 in the present invention, the carry signal Cn + 2 output from the rear stage STn + 2 is stabilized by the gate-off voltage without multi-output, thereby It can be seen that the QB node potential is stabilized without voltage loss in the next stage stage STn + 4 where the carry signal Cn + 2 is applied as a charging control signal.

FIG. 8 is a diagram showing the potential of the Q2 node according to the channel width size of the second pull-up transistor Tup2 in the rear stage STn + 2 shown in FIG. 3.

Referring to FIG. 8, when the stabilizing transistor T6 is applied to the rear stage STn-2, the Q2 node when the channel width of the second pull-up transistor Tup2 in the rear stage STn + 2 is 350 μm or more It can be seen that the high potential (52.1V) of is similar to the high potential (52.3V) of the Q1 node of the front end stage (STn).

In this way, the shift register according to the present invention and the display device using the same are stable in the carry signal by adding a stabilizing transistor that applies a gate-off voltage to the carry signal when the Q2 node is precharged to the rear stage among the stages sharing the QB node. Since the gate-off voltage is maintained, multiple outputs of the carry signal can be prevented.

Accordingly, the present invention prevents voltage deviation due to abnormal carry signals in other stages using a carry signal as a control signal, thereby preventing voltage deviation between the gate lines driven by the front and rear stages, and preventing flicker and the like, thereby improving image quality. Improve it.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 110: display area
120: gate driver 130: data driver
140: timing controller 150: level shifter
DL: Data line GL #: Gate line
SR: Shift register ST #: Stage
C #: Carry signal Vout (#): Scan signal
10: control unit 20: carry output unit
30: scan output 12: Q node charging
14: Q node discharge unit 16_O, 16_E: QB node charging unit
18_O, 18_E: QB node discharge

Claims (7)

A plurality of stages sequentially outputting a plurality of scan signals and carry signals;
The multiple stages are grouped into two units that share QB nodes with each other;
The pair of stages sharing the QB nodes with each other has a front stage and a rear stage;
Each of the front and rear stages is
A carry output unit outputting an input clock signal as a carry signal in response to control of the Q node, and outputting a first gate-off voltage as the carry signal in response to control of the QB node;
A scan output unit outputting the input clock signal as a scan signal in response to control of the Q node, and outputting a second gate-off voltage as the scan signal in response to control of the QB node;
A Q node charging unit charging the Q node in response to a charge control signal using a carry signal output from one of the previous stages;
A Q node discharge unit for discharging the Q node in response to control of a discharge control signal using a carry signal output from one of the next stage stages;
The QB nodes shared by the front and rear stages include QB_ODD nodes and QB_EVEN nodes that are alternately driven for each frame;
One of the front and rear stages further includes a QB_ODD charging unit for charging the QB_ODD node and a QB_ODD discharge unit for discharging the QB_ODD node in response to control of the Q node of the front and rear stages;
The other stages of the front and rear stages further include a QB_EVEN charging unit for charging the QB_EVEN node and a QB_EVEN discharge unit for discharging the QB_EVEN node in response to control of the Q node of the front and rear stages;
The rear stage further includes a stabilization switch, and the stabilization switch is controlled by the charging control signal applied to the Q node charging portion of the front stage, and when the Q node of the rear stage is precharged, A shift register, characterized in that the first gate-off voltage is supplied with a carry signal. The method according to claim 1,
The scan output unit
A first pull-up transistor that outputs an input clock signal of the corresponding stage as a scan signal of the corresponding stage under control of a Q node of the corresponding stage;
And a 1-1 and 1-2 pull-down transistor configured to output the second gate-off voltage as a scan signal of a corresponding stage under control of each of the QB_ODD node and QB_EVEN node;
The carry output unit
A second pull-up transistor that outputs an input clock signal of the corresponding stage as a carry signal of the corresponding stage under control of a Q node of the corresponding stage;
And 2-1 and 2-2 pull-down transistors outputting the first gate-off voltage as a carry signal of a corresponding stage under control of each of the QB_ODD node and the QB_EVEN node;
The shift register of the post-stage stabilization switch is characterized in that it supplies the first gate-off voltage to the output node of the 2-1 and 2-2 pull-down transistors of the rear stage. The method according to claim 1,
The Q node charging unit
A first transistor supplying a gate-on voltage to the Q node under control of the charge control signal;
The Q node discharge unit
A 3-1 transistor supplying the first gate-off voltage to the Q node under control of the discharge control signal;
3-3 and 3-3 transistors for supplying the first gate-off voltage to the Q node under control of each of the QB_ODD node and the QB_EVEN node;
And a 3-4 transistor for supplying the first gate-off voltage to the Q node in response to an external reset signal together with the 3-1, 3-2, and 3-3 transistors. Shift register. The method according to claim 1,
Each of the QB_ODD charging unit and the QB_EVEN charging unit
A 4-1 transistor supplying an AC gate-on voltage to the QB_ODD or QB_EVEN node;
A 4-2 transistor connected in a diode type between a supply line supplying the AC gate-on voltage and a control node of the 4-1 transistor;
A 4-3 transistor supplying the first gate-off voltage to the control node under the control of the Q node of the corresponding stage;
And a 4-4 transistor for supplying the first gate-off voltage to the control node under the control of a Q node of a stage other than the corresponding stage among the pair of stages. The method according to claim 1,
Each of the QB_ODD discharge section and the QB_EVEN discharge section
A 5-1 transistor supplying the first gate-off voltage to the QB_ODD or QB_EVEN node in response to a charge control signal applied to the front stage;
And a 5-2 transistor for supplying the first gate-off voltage to the QB_ODD or QB_EVEN node under the control of the Q node of the corresponding stage. The method according to claim 1,
In the turn-on period of the stabilization switch, before the carry signal of the rear stage outputs the gate-on voltage, the Q node charging unit of the rear stage responds to the carry signal of the front stage to set the Q node of the rear stage. A shift register characterized by overlapping with a precharging period. The method according to claim 1,
A display device driving the gate line of the display panel using the shift register.

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