KR102090265B1 - Pattern generator for memory semiconductor test and method thereof - Google Patents

Abstract

According to the present invention, provided is a pattern generating apparatus, which comprises: an input unit receiving test vectors or parameters; a vector compiler unit compiling a plurality of test vectors described in a script form; a sequence controller unit delivering parameters as a vector pointer in real time; and a pattern generation unit combining a pre-stored data memory with a compiled test vector based on a parameter which is first in and first out from the vector pointer, and generating a pattern for testing a memory semiconductor in real time.

Description

Pattern generation device and method for memory semiconductor test {PATTERN GENERATOR FOR MEMORY SEMICONDUCTOR TEST AND METHOD THEREOF}

An apparatus and method for generating a pattern for testing a memory semiconductor are provided.

In order to test a memory semiconductor, a tester must generate an electrical signal conforming to a memory standard and transmit it to a device under test (DUT).

Here, the electrical signal is largely composed of a pattern, a timing, and a level, and among them, an algorithmic pattern generator is mainly used to generate a pattern inside a memory tester.

On the other hand, in response to the increase in the speed of memory, the memory tester is also required to have high speed and high precision. In particular, since the test time increases as the memory capacity increases, the test must be rapidly performed to reduce the test cost.

Therefore, currently, a hardware-based algorithm pattern generator capable of rapidly generating patterns in real time to test a memory semiconductor is mainly used.

However, these algorithm pattern generators require very large equipment size and power, and are very complex and expensive hardware configuration, which is difficult for real engineers to use.

In addition, since the hardware-based algorithm pattern generator provides only fixed program variables and test languages, it is difficult to apply various and flexible programming desired by real users.

Accordingly, there is a need for a pattern device for testing a memory semiconductor in a manner that combines a simple hardware configuration capable of generating a pattern in real time with a variety of flexible programmable software configurations.

One embodiment of the present invention is to enable a user to easily program a pattern for testing a memory semiconductor in a flexible programming environment.

In addition to the above tasks, it can be used to achieve other tasks not specifically mentioned.

The pattern generating apparatus according to an embodiment of the present invention includes an input unit that receives test vectors or parameters, a vector compiler unit that compiles a plurality of test vectors described in a script form, and a sequence controller unit that delivers parameters in real time as a vector pointer. And a pattern generation unit that combines a pre-stored data memory with a compiled test vector based on parameters that are first in, first out from the vector pointer, and generates a pattern for memory semiconductor testing in real time.

The input unit may receive a parameter including one of an index of a vector memory that stores a test vector, an index of a data memory, and address offset information through a programming language.

The pattern generator may automatically insert a refresh command between the combined test vectors by generating a time interrupt every predetermined period.

The pattern generator can generate patterns in real time by combining memory addresses and command addresses based on the test vector, including command and control signals, address signals, write data signals, read data signals, and refresh signals, in the order of parameters. have.

Receiving a parameter including one of an index of a vector memory, an index of a data memory, or address offset information through a programming language according to an embodiment of the present invention, and passing the received parameter to a vector pointer in real time , Combining a vector memory and a data memory stored in advance based on first-in, first-out parameters from the vector pointer, generating a vector stream, command and control signals, address signals, write data signals, read data signals, and refresh according to the vector stream And real-time generating a pattern for a memory semiconductor test in which a memory operation including a signal and an address address are combined.

One embodiment of the present invention provides a programming pattern through a general programming language without using a test language specialized for a tester, thereby improving flexibility in terms of a program of a user programming various general language techniques and designing And it is easy to evaluate can provide convenience.

In addition, one embodiment of the present invention is easy to expand in the process of updating or maintaining equipment in response to a new semiconductor.

In addition, one embodiment of the present invention can minimize the cost and space constraints by enabling small and inexpensive equipment to be manufactured with a simple hardware configuration and software combination.

1 is a configuration diagram of a pattern generating apparatus according to an embodiment of the present invention.
2 is an overall block diagram illustrating a pattern generating apparatus according to an embodiment of the present invention.
3 is a flowchart illustrating a pattern generation process of a pattern generation device according to an embodiment of the present invention.
4 is an embodiment of implementing a script and a tester vector input from a user of a pattern generating apparatus according to an embodiment of the present invention.
5 is an exemplary view showing a packet structure of data according to an embodiment of the present invention.
6 is an exemplary diagram illustrating a pattern generation process of a device of a pattern generation device according to an embodiment of the present invention as a flow of data.
7 is an embodiment of hardware implementation of a pattern generating apparatus according to an embodiment of the present invention.

The embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. In the drawings, parts not related to the description are omitted in order to clearly describe the present invention, and the same reference numerals are used for the same or similar elements throughout the specification. In the case of well-known technology, detailed description thereof will be omitted.

Throughout the specification, when a part “includes” a certain component, it means that the component may further include other components, not to exclude other components, unless otherwise stated.

Hereinafter, a pattern generating apparatus composed of software and hardware according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a configuration diagram of a pattern generating apparatus according to an embodiment of the present invention, and FIG. 2 is an overall block diagram for explaining a pattern generating apparatus according to an embodiment of the present invention.

As shown in FIG. 1, the pattern generation device 100 includes an input unit 110, a vector compiler unit 120, a sequence controller unit 130, and a pattern generation unit 140.

First, the input unit 110 may receive a test vector or parameter through communication with a user terminal (not shown), and may receive an input through a server in addition to the user terminal.

Here, the communication network may include any type of communication network that transmits data, such as a wired communication network, a short-range or long-range wireless communication network, and a network in which they are mixed.

In addition, the input unit 110 may receive test vectors and parameters through a general programming language. Therefore, input test vectors and parameters may include general language techniques such as variable declaration or conditional branching, iteration, and use of functions and classes.

In addition, depending on the situation, the input unit 110 may be input through a test language specialized for interlocked equipment.

Next, the vector compiler unit 120 compiles a plurality of test vectors described in a script form.

Here, the test vector represents an operation to be performed in a preset clock unit.

In addition, the vector compiler unit 120 may compile the test vector in binary format, and may also compile the data memory in binary format in advance.

In addition, the vector compiler unit 120 may store the compiled test vector in the vector memory and the contents of the compiled data memory in the data memory.

The vector compiler 120 may store the contents of the compiled test vector and the compiled data memory through a high speed bus in a vector memory and a data memory, respectively, to perform fast communication.

Next, the sequence controller 130 transmits the parameters to the vector pointer in real time.

At this time, the sequence controller 130 may transmit the vector pointer through a high speed bus to perform fast communication, but is not limited thereto.

Next, the pattern generation unit 140 combines the pre-stored data memory with the test vector compiled based on the parameters, and generates a pattern for the memory semiconductor test in real time.

Here, the pre-stored data memory is compiled and stored, and the pattern generator 140 may sequentially combine various test vectors according to the order of input parameters to generate patterns in real time through a combination of various memory operations and various addresses.

On the other hand, as shown in 2, the pattern generating apparatus 100 according to an embodiment of the present invention can be largely divided into a hardware area and a software area.

In FIG. 2, a processor is a software area, and may include an input unit 110 (user input), a vector compiler unit 120, and a sequence controller unit 130.

Such a software area compiles a test vector described in the form of a script received from a user terminal or a server, and combines a plurality of test vectors to transmit parameters to a hardware area to create various memory operations and various address combinations.

On the other hand, a non-memory semiconductor (FPGA, Programmable Logic) is a semiconductor that can re-engrave the circuit several times, and can be divided into hardware areas.

The hard air area represents a pattern generator 140 that generates a pattern in real time using various information. In addition, in the hardware area, a memory part including a vector pointer 150 (VECTOR POINTER), a vector memory and a data memory (DATA MEMORY), which contains parameters such as an index of the vector memory and an index and address offset of the data memory. It may further include (160).

Here, the vector memory (Vector Memory) stores a test vector (Vector) generated in every clock (Clock) unit, the data memory (DATA MEMORY) to write and read the data to be read and written to the device under test (DUT: Device Under Test) I am saving it.

In addition, the hardware area is a physical interface (PHY) that converts the memory timing from the high-speed bus and the pattern generator 140 to quickly communicate with the software area according to the actual device under test (DUT) memory specification. ) May be further included.

And, as described above, a pattern can be generated in real time based on parameters received through close communication between a software area and a hardware area.

Meanwhile, the pattern generating device 100 may be a server, a terminal, or a combination of these.

The terminal is a device having a computational processing capability by having a memory and a processor, respectively. For example, there are personal computers, handheld computers, personal digital assistants (PDAs), cell phones, smart devices, tablets, and the like.

The server is a processor in which a plurality of modules are stored, and a processor that is connected to the memory and reacts to a plurality of modules and processes service information provided to a terminal or action information for controlling service information, communication And means for displaying a user interface (UI).

Memory is a device that stores information, such as high-speed random access memory (high-speed random access memory, magnetic disk storage, flash memory device, other non-volatile solid-state memory device) It may include various types of memory such as volatile memory.

The communication means transmits and receives service information or action information to the terminal in real time.

The UI display means outputs service information or action information of the system in real time. The UI display means may be an independent device that directly or indirectly outputs or displays the UI, or may be a part of the device.

Hereinafter, a process of generating a user's input pattern according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6.

3 is a flowchart illustrating a pattern generation process of a pattern generation device according to an embodiment of the present invention, and FIG. 4 implements a script and a tester vector input from a user of the pattern generation device according to an embodiment of the present invention This is one example.

As illustrated in FIG. 3, the pattern generation device 100 receives parameters through a programming language (S310).

Here, the programming language does not represent a program variable and a test language limited to a conventional memory tester, but includes all of a variety of commonly used programming languages.

For example, a programming language designed to be used in virtually any computer system such as C / C ++ language, but is not limited thereto, and a test language specialized for interlocking special equipment may be used.

The pattern generating apparatus 100 receives parameters written in a programming language from a user terminal or a server. Here, the parameter may include one or more of an index of vector memory, an index of data memory, or address offset information.

In addition, the pattern generation device 100 may receive parameters in the form of a test script. For example, the pattern generating apparatus 100 may call a test vector using functions, conditional branching, repetition, and classes provided in a general programming language, and receive a sequence including a changed address as a parameter.

4 shows an embodiment in which a sequence script is written and an actual vector for testing a real dynamic random access memory (DRAM) memory is described.

4 (a) is an exemplary view showing a test script input to the pattern generating apparatus 100, and (b) is an exemplary diagram showing a test vector input to the pattern generating apparatus 100.

In the test vector of FIG. 4 (b), a clock unit vector (Command, Address, Data) is described, and in the sequence script of (a), the test vector is called each time and the address is increased by rotating the Address increment Loop. Shows an example of actual implementation by applying the concept of the present invention in a manner of passing as a parameter.

As described above, the pattern generating apparatus 100 may receive data in a variable form used through a general programming language, or in a script form using conditional branching, repetition, functions, and classes.

Meanwhile, the pattern generating apparatus 100 may receive a plurality of test vectors described in a script form from a user terminal or a server, as shown in FIG. 4B.

Here, the test vector is a preset clock unit vector (command, address, data).

In addition, the pattern generation device 100 may compile the test vector in a binary format and store it in a vector memory in advance, and compile the data memory in a binary format and store it in the data memory in advance.

As described above, the pattern generating apparatus 100 may receive a test vector before step 310, compile it, store it in a vector memory, compile the data memory, and store it in the data memory in advance.

Next, the pattern generating apparatus 100 transmits the parameters to the vector pointer 150 in real time (S320).

Here, the vector pointer 150 contains parameters including the received vector index, data index, and address information, and is configured in the form of first in first out (FIFO) to sequentially deliver the received parameters. have.

5 is an exemplary view showing a packet structure of data according to an embodiment of the present invention.

5 is an example of implementing a detailed packet structure of a vector pointer, vector memory, and data memory as an example of a pattern generator for testing DRAM memory.

As illustrated in FIG. 5, various parameters received are sequentially stored in the vector pointer 150, and the parameter is an index (Vector ID) of a vector memory storing a test vector, CMD, BA, RA, CA, It includes an index (DATA) of the data memory, and address offset information.

A plurality of test vectors is stored in the vector memory, and each test vector has HW CMD and HW ARG values. In addition, the data memory contains data to be written and read. Since the vector memory and the data memory are strongly required in real time, they are precompiled into binaries and loaded into the memory unit 160 in advance.

Next, the pattern generating apparatus 100 generates a vector stream by combining the stored vector memory and data memory based on first-in-first-out parameters (S330).

6 is an exemplary diagram illustrating a pattern generation process of a device of a pattern generation device according to an embodiment of the present invention as a flow of data.

As illustrated in FIG. 6, the vector memory in which the test vector compiled by the vector compiler unit 120 is stored and the data memory (not shown) compiled and stored are stored in advance before generating a vector stream. Is set. This is to improve real-time performance, which means that the vector memory and data memory are stored in advance.

On the other hand, the pattern generation device 100 receives parameters in real time (On-line) through the sequence controller 130 and stores them in a vector pointer.

In addition, the pattern generation unit 140 of the pattern generation device 100 may sequentially access the vector pointer 150 to read parameters in a first-in, first-out manner, and analyze parameters. Accordingly, the pattern generating apparatus 100 generates a vector stream in real time in the order programmed from the user terminal or the server.

As shown in FIG. 6, when the execution order of the test vectors is sequentially confirmed by V1, V2, V3, V4, and V5, a vector stream is generated according to the order.

On the other hand, a semiconductor memory such as DRAM is periodically requested to be refreshed. Accordingly, the pattern generating apparatus 100 may generate an auto refresh (R) without being programmed separately.

In FIG. 6, it can be seen that the refresh R is inserted between the test vector V1 and the test vector V2, and the test vector V3 and the test vector V4 are repeatedly repeated according to a preset period. It can be seen that the refresh (R) is inserted between.

In other words, the pattern generating apparatus 100 may generate a time interrupt every predetermined period to automatically insert a refresh command between vector lines allowed by the user.

With this principle, the vector (the timing of the command, address, and data combination) finally programmed by the user sequentially generates a vector stream.

Next, the pattern generating apparatus 100 generates a pattern in which the memory operation and the address address are combined in real time (S340).

The pattern generating apparatus 100 in real time performs a pattern for testing memory semiconductors in which memory addresses including command and control signals, address signals, write data signals, read data signals, and refresh signals and address addresses are combined according to the vector stream. Can be created.

7 is an embodiment of hardware implementation of a pattern generating apparatus according to an embodiment of the present invention.

7 shows an embodiment in which hardware of an actual pattern generator is implemented based on the overall configuration of FIG. 2. FIG. 7 briefly shows the software area as a ZYNQ Processor, and shows the hardware area in detail below.

The program for executing the method according to one embodiment of the present invention may be recorded on a computer-readable recording medium.

Computer-readable media may include program instructions, data files, data structures, or the like alone or in combination. The media may be specially designed and constructed, or may be known and usable by those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs, DVDs, magnetic-optical media such as floptical discs, and ROM, RAM, flash memory, etc. Hardware devices specifically configured to store and execute the same program instructions are included. Here, the medium may be a transmission medium such as an optical or metal line, a waveguide including a carrier wave that transmits a signal specifying a program command, a data structure, or the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, etc., as well as machine language codes made by a compiler.

In the above, one preferred embodiment of the present invention has been described in detail, but the scope of the present invention is not limited to this, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims. It belongs to the scope of the present invention.

100: pattern generating device 110: input unit
120: vector compiler section 130: sequence controller section
140: pattern generator 150: vector pointer
160: memory unit

Claims (6)

Input unit that receives test vectors or parameters,
A vector compiler that compiles a plurality of test vectors described in script form,
Sequence controller unit for transmitting the parameters in real time as a vector pointer, and
A pattern generation unit that combines pre-stored data with a compiled test vector based on the parameters that are first in, first out from the vector pointer, and generates a pattern for memory semiconductor testing in real time.
Pattern generation device comprising a.
In claim 1,
The input unit,
A pattern generation device that receives a parameter including one of an index of a vector memory, an index of a data memory, and address offset information storing the test vector through a programming language.
In claim 1,
The pattern generation unit,
A pattern generation device that automatically inserts a refresh command between the combined test vectors by generating a time interrupt every preset period.
In claim 1,
The pattern generation unit,
A pattern generation device that generates patterns in real time by combining memory addresses and command addresses based on the test vector, including a control signal, an address signal, a write data signal, a read data signal, and a refresh signal, in the order of the parameters. .
Receiving a parameter including one of an index of a vector memory, an index of a data memory, or address offset information through a programming language,
Passing the input parameter in real time to a vector pointer,
Generating a vector stream by combining a pre-stored vector and pre-stored data based on the first-in, first-out parameter from the vector pointer,
Generating a pattern for a memory semiconductor test combining a memory operation including an address address with a command signal, a control signal, an address signal, a write data signal, a read data signal, and a refresh signal according to the vector stream, in real time,
Pattern generation method of the pattern generating apparatus comprising a.
In claim 5,
Receiving a plurality of test vectors described in a script form,
Compiling the test vector in binary format and storing it in vector memory,
In the vector stream, generating a time interrupt every predetermined period to automatically insert a refresh command.
The pattern generation method of the pattern generation device further comprising a.

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