KR102075355B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: data lines, gate lines crossing the data lines, a first common line parallel to the data lines and across a center of a pixel array; And a display panel parallel to the gate lines and having a second common line crossing the center of the pixel array. The pixel array includes first to fourth pixel groups divided by the first and second common lines. Left and right neighboring pixel groups have a symmetrical pixel structure, and up and down neighboring pixel groups have a symmetrical pixel structure.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device.

Flat display devices include Liquid Crystal Display Devices (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Display Devices (OLEDs), Electrophoretic Display Devices: EPD) and the like. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to the data voltage. Active matrix type liquid crystal display devices are widely used in almost all display devices, from small mobile devices to large televisions, due to the low price and high performance due to the development of process technology and driving technology.

Manufacturers of flat panel displays have made various attempts to implement narrow bezels. Narrow bezel technology can reduce the size of the bezel in which an image is not displayed at the edge of the display panel to increase the size of an effective screen on which an image is displayed on the same sized display panel. In general, gate drive integrated circuits (ICs) are disposed at left and right edges of the display panel. Accordingly, the left and right edges of the display panel should have a region to which the gate drive IC is bonded and a gate link region connecting the gate drive IC to the horizontal gate lines of the pixel array. Due to the structural problem of such a flat panel display device, it is difficult to implement a narrow bezel.

In the LCD, the pixel electrode and the common electrode may be formed as transparent electrodes. Indium Tin Oxide (ITO) is the most widely used transparent electrode. Since the transparent electrode has a relatively high resistivity, when the screen of the display panel is enlarged, a voltage drop may occur, which may cause a problem of luminance uniformity between pixels. Since the resistance of the transparent electrode increases in proportion to the area of the transparent electrode, the larger the display panel, the larger the resistance.

As the display panel grows, a method of compensating for high resistivity of the transparent electrode by using a highly conductive metal in contact with the transparent electrode is used. However, most of the highly conductive metals are opaque metals, which lowers the aperture ratio and transmittance of the pixels. The highly conductive metal may be connected to the transparent electrode at every display line of the pixel array. As the pixels per inch (PPI) of the display panel increase, the pixel size decreases. Therefore, when the opaque metal is brought into contact with the transparent electrode on every display line of the pixel array, the aperture ratio and transmittance of the pixel become smaller.

In a liquid crystal display (IPS) mode, a pixel electrode and a common electrode are formed on the same substrate. In the IPS mode liquid crystal display, liquid crystal molecules are driven by a horizontal electric field applied between the pixel electrode and the common electrode. Common electrodes formed on the plurality of pixels are commonly connected to a horizontal common line. The horizontal common line is parallel to the gate line and is formed of a gate metal such as a gate line. Due to this horizontal common line, the aperture ratio of the pixels is lowered. If the number of horizontal common lines formed in the display panel is reduced, the aperture ratio may be increased. However, an increase in the resistance of the horizontal common line may cause the common voltage Vcom applied to the common electrodes of the display panel to be uneven.

The present invention provides a liquid crystal display device capable of reducing the resistance of the common line and increasing the aperture ratio and transmittance of the pixel.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: data lines, gate lines crossing the data lines, a first common line parallel to the data lines and crossing a center of a pixel array; And a display panel parallel to the gate lines and having a second common line crossing the center of the pixel array. The pixel array includes first to fourth pixel groups divided by the first and second common lines. Left and right neighboring pixel groups have a symmetrical pixel structure, and up and down neighboring pixel groups have a symmetrical pixel structure.

The present invention reduces the resistance of the common line by electrically connecting the first and second common lines to the common electrodes of the pixels, and mirrors the four divided pixel groups with the first and second common lines between them in the pixel array. It is possible to increase the aperture ratio and transmittance of the pixels by forming a pixel structure.

1 illustrates a pixel array of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a cross-sectional view illustrating a connection structure between a horizontal common line and a common electrode of a pixel.
3 is a cross-sectional view illustrating a connection structure between a vertical common line and a common electrode of a pixel.
4 is a diagram illustrating an example in which a width of a black matrix becomes thick due to a plurality of vertical common lines.
FIG. 5 is a diagram illustrating an example in which the thickness of a black matrix is reduced due to one horizontal common line and one plurality of vertical common lines as shown in FIG. 1.
6 and 7 illustrate a liquid crystal display of a narrow bezel structure.
FIG. 8 is a diagram illustrating a structure of a chip on film (COF) illustrated in FIG. 7.
9 is a diagram illustrating an example in which ICs are distributedly disposed on an upper end and a lower end of a display panel.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

1 to 4, the liquid crystal display of the present invention includes a display panel and a display panel driving circuit.

The display panel may be implemented in a liquid crystal mode having any known structure such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS). The display panel includes an upper plate and a lower plate bonded together with a sealant with a liquid crystal layer interposed therebetween. In the display panel, image data is displayed on a pixel array in which pixels are arranged in a matrix form. The pixel array includes a thin film transistor (TFT) array formed on the lower plate, and a color filter array formed on the upper plate.

The display panel driver circuit writes data of an input image into pixels. The display panel driving circuit includes a source drive integrated circuit (IC), a gate drive IC, and a timing controller. The source drive IC converts digital video data into an analog gamma compensation voltage using a digital-to-analog converter (ADC) to generate a data voltage, and transmits the data voltage to the data lines Di to Di + n. Supply. The gate drive IC sequentially supplies gate pulses (or scan pulses) synchronized with the data voltages to the gate lines Gj to Gj + n. The timing controller controls the operation timing of the source drive IC and the gate drive IC, and transmits digital video data of the input image to the source drive IC.

The TFT array includes data lines Di to Di + n, gate lines Gj to Gj + n orthogonal to the data lines Di to Di + n, and data lines Di to Di + n. A TFT formed at an intersection of the lines Gj to Gj + n, a pixel electrode (FIGS. 6 and 1) of the liquid crystal cell Clc connected to the TFT, and a storage capacitor (FIGS. 6 and Cst) connected to the pixel electrode. do. The TFT supplies the data voltage from the data lines Di to Di + n to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulses from the gate lines Gj to Gj + n. In addition, the TFT array includes a vertical common line VC parallel to the data lines Di to Di + n, and a horizontal gate line HC parallel to the gate lines Gj to Gj + n. In the case of the transverse electric field mode such as the IPS mode or the FFS mode, the common electrode (Figs. 6 and 2) to which the common voltage Vcom is applied is formed in the TFT array.

The common voltage Vcom is supplied to the horizontal common line HC and the vertical common line VC from a power supply circuit (not shown). The horizontal common line HC and the vertical common line VC are connected to the common electrodes 2 of the pixels as shown in FIGS. 2 and 3 to supply the common voltage Vcom to the common electrodes 2.

The horizontal common line HC is formed as a single line formed along an imaginary horizontal line crossing the center of the display panel PNL. The pixel array is divided into two vertically with the horizontal common line HC interposed therebetween. The vertical common line VC is formed as a single line formed along an imaginary vertical line that crosses the center of the display panel PNL.

The color filter array includes a color filter and a black matrix. Polarizing plates are attached to each of the upper and lower plates of the display panel, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The pixel array is divided into two left and right with a vertical common line VC interposed therebetween. Therefore, the pixel array may be divided into four divisions by the vertical common line VC and the horizontal common line HC to be divided into first to fourth pixel groups CELL1 to CELL4.

The first pixel group CELL1 is disposed in the left half portion of the upper half of the pixel array. The second pixel group CELL2 includes pixels that are disposed at the right half of the upper half of the pixel array and are symmetrical with respect to the pixels of the first pixel group CELL1. In the pixels of the first pixel group CELL1, data lines are formed on the left side of the pixel. In the pixels of the second pixel group CELL2, data lines are formed on the right side of the pixel. Therefore, the pixel structure of the first pixel group CELL1 is symmetrical with respect to the pixel structure of the second pixel group CELL2. Due to this symmetrical structure, there is no data line at the boundary between the first pixel group CELL1 and the second pixel group CELL2 and a vertical common line VC is formed at the position.

The first pixel group CELL1 is disposed in the left half portion of the upper half of the pixel array. The third pixel group CELL3 includes pixels that are disposed in the left half of the lower half of the pixel array and are vertically symmetrical with respect to the pixels of the first pixel group CELL1. Gate lines in the pixels of the first pixel group CELL1 are formed on the upper side of the pixel. In the pixels of the third pixel group CELL3, gate lines are formed below the pixel. Therefore, the pixel structure of the first pixel group CELL1 is up and down symmetric with respect to the pixels of the third pixel group CELL2. Due to this vertically symmetrical structure, there is no gate line at the boundary between the first pixel group CELL1 and the third pixel group CELL3, and a horizontal common line HC is formed at a position thereof.

The fourth pixel group CELL4 is disposed at the right half of the lower half of the pixel array. The pixel structure of the second pixel group CELL2 is symmetrical with respect to the pixels of the first pixel group CELL1, and is symmetric with the pixel structure of the fourth pixel group CELL4. The pixel structure of the third pixel group CELL3 is vertically symmetrical with respect to the pixels of the first pixel group CELL1, and is symmetrical with the pixel structure of the fourth pixel group CELL4. The pixel structure of the fourth pixel group CELL4 is vertically symmetrical with respect to the pixels of the second pixel group CELL2, and is also symmetrical with respect to the pixels of the third pixel group CELL3.

Due to the symmetrical structure of the four-divided pixel array, one vertical line is formed between the left and right neighboring pixels. One vertical line may be a data line or a vertical common line VC. One horizontal line is formed between up and down neighboring pixels. One horizontal line may be a gate line or a horizontal common line HC. Therefore, the present invention can reduce the width of the black matrix (BM) formed at the boundary between the pixels, thereby increasing the aperture ratio and the transmittance of the pixels.

The present invention can reduce the resistance of the common lines VC and HC as compared with the case where one horizontal common line is formed in the display panel. In addition, the present invention can increase the aperture ratio and the transmittance of the pixels by designing a pixel structure of the pixel groups divided into four through the common lines VC and HC in a symmetrical structure.

2 is a cross-sectional view illustrating a connection structure between a horizontal common line and a common electrode of a pixel. 3 is a cross-sectional view illustrating a connection structure between a vertical common line and a common electrode of a pixel.

2 and 3, the TFT includes a gate electrode GE formed on the substrate SUBS, a gate insulating film GI covering the gate electrode GE, an active layer ACT formed on the gate insulating film GI, A source electrode SE and a drain electrode DE formed on the active layer ACT are included. The active layer ACT is formed of a semiconductor. The first passivation layer PAS1 and the passivation layer PAC cover the TFTs. The gate electrode GE of the TFT is connected to the gate line. The drain electrode DE of the TFT is connected to the data line, and the source electrode SE of the TFT is connected to the pixel electrode PXL.

The gate electrode GE of the TFT, the gate line, the lower electrode LP2 of the gate pad, and the horizontal common line HC are formed of first metal patterns formed on the substrate SUBS. The source and drain electrodes SE and DE of the TFT, the data line, the lower electrode LP1 of the data pad, and the vertical common line VC are formed of the second metal formed on the gate insulating layer GI and the active layer ACT. It is formed into patterns.

The gate pads are connected to the output terminals of the gate drive IC to which the gate pulses are output. Gate pads are connected to the gate lines. The data pads are connected to output terminals of a source drive integrated circuit (IC) to which a data voltage is output. Data pads are connected to the data lines.

The pixel electrode PXL, the common electrode COM, the upper electrode UP2 of the gate pad, and the upper electrode UP1 of the data pad are formed of a transparent electrode material such as ITO.

The second passivation layer PAS2 is formed between the pixel electrode PXL and the common electrode COM. The gate insulating layer GI and the passivation layers PAS1 and PAS2 may be formed of an inorganic insulating material such as silicon nitride (SiNx). The passivation layer PAC may be formed of an organic insulating material such as photo acryl.

The common electrode COM is connected to the horizontal common line HC through a contact hole penetrating through the gate insulating layer GI, the first passivation layer PAS1, and the passivation layer PAC. In addition, the common electrode COM is connected to the vertical common line VC through a contact hole passing through the first passivation layer PAS1 and the passivation layer PAC.

As shown in FIG. 1, when the pixel structure of neighboring pixel groups is symmetric with each other and divided into four horizontal boundaries with one horizontal common line HC and one vertical common line VC, the aperture ratio of the pixels is small. In contrast, when the number of vertical common lines or horizontal common lines is increased, the aperture ratio of pixels is lowered. This can be easily seen through the comparison of FIGS. 4 and 5.

When a plurality of vertical common lines VC are formed in the TFT array as illustrated in FIG. 4, two data lines may be formed at a boundary between neighboring pixel groups CELLn and CELLn + 1. When two data lines DLn and DLn + 1 are formed at the boundary between the pixels, the width of the black matrix BM is increased, so that the aperture ratio of the pixels is reduced and the transmittance is lowered. On the contrary, when the pixel array is divided into four as shown in FIGS. 1 and 5, since one vertical line and one horizontal line are formed at neighboring pixels at any position of the pixel array, the aperture ratio of the pixels is increased.

The present invention consists of gate lines consisting of vertical gate lines and horizontal gate lines 1: 1 connected to the vertical gate lines, and by connecting the gate drive IC to the gate pads of the vertical gate lines, FIGS. 6 and 7. As described above, the bezel of the display panel can be minimized.

6 and 7 illustrate a liquid crystal display of a narrow bezel structure.

6 and 7, the TFT array includes vertical wirings and horizontal wirings. The vertical lines are formed along the vertical direction (y-axis direction) of the display panel PNL. The horizontal lines are formed along the horizontal direction (x-axis direction) of the display panel PNL to be perpendicular to the vertical lines.

The vertical lines include data lines VD, vertical gate lines VG, and a vertical common line VC. Data voltages are supplied to the vertical data lines VD, and gate pulses synchronized with the data voltages are supplied to the vertical gate lines VG. The common voltage Vcom is supplied to the vertical common line VC.

The horizontal lines include horizontal gate lines HG and horizontal common lines HC. The horizontal gate lines HG are connected to the vertical gate lines VG to receive gate pulses through the vertical gate lines VG. The common voltage Vcom is supplied to the horizontal common line HC.

The pixel array of the display panel PNL is divided into four by bordering one horizontal common line HC and one vertical common line VC. The pixel structure of neighboring pixel groups is symmetric with each other.

The TFT supplies the data voltage from the vertical data line VD to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HG. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common voltage Vcom is applied to the common electrode 2 of all pixels through the vertical common line VC and the horizontal common line HC. The storage capacitor Cst is connected to the pixel electrode 1 of the liquid crystal cell Clc to maintain the voltage of the liquid crystal cell Clc for one frame period.

The display panel driver circuit 10 writes data input from the timing controller 12 to pixels of the display panel. The display panel driver circuit 10 includes a source drive IC (SIC) for outputting a data voltage and a gate drive IC (GIC) for outputting a gate pulse.

The source drive IC (SIC) and the gate drive IC (GIC) may be mounted together on a flexible circuit board such as a chip on film (COF) as shown in FIG. 8. The input terminal of the COF is bonded to a printed circuit board (PCB), and the output terminal of the COF is bonded to a TFT array substrate of the display panel PNL. In the COF, an insulating layer is provided between the wires connected to the source drive IC (SIC) (FIG. 8, dotted line) and the wires connected to the gate drive IC (GIC) (FIG. 8, solid line) so as to be electrically separated. Is formed. The source drive IC SIC and the gate drive IC GIC may be separately disposed on the upper bezel and the lower bezel of the display panel PNL as shown in FIG. 9. The source drive IC (SIC) and the gate drive IC (GIC) may be directly bonded on the substrate of the display panel PNL by a chip on glass (COG) process.

The source drive IC (SIC) samples the digital video data of the input image under the control of the timing controller 12 and then latches and converts the digital video data into data of a parallel data system. The source drive IC (SIC) converts digital video data into an analog gamma compensation voltage using a digital-to-analog converter (ADC) under the control of the timing controller 12 to generate a data voltage and convert the data voltage into vertical data lines ( VD). The gate drive IC GIC sequentially supplies a gate pulse (or scan pulse) synchronized with the data voltage from the first vertical gate line to the nth vertical gate line under the control of the timing controller 12.

The source drive IC SIC and the gate drive IC GIC are disposed above or below the display panel PNL. As a result, the gate drive IC GIC does not need to be bonded or embedded in the left and right bezel regions of the display panel PNL, and the gate link line connects the horizontal gate lines HG and the gate drive IC GIC. You do not need. Accordingly, the present invention can minimize the left bezel BZ and the right bezel BZ of the display panel PNL.

The timing controller 12 transmits digital video data of the input image received from the host system 14 to the source drive ICs SIC. The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable (DE), and a main clock CLK from the host system 14. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 uses a timing signal Vsync, Hsync, DE, and CLK to control a source timing control signal for controlling the operation timing of the source drive ICs SIC, and an operation timing of the gate drive ICs GIC. Generates a gate timing control signal for controlling the signal.

The host system 14 may be implemented as one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. have. The host system 14 converts the digital video data RGB of the input image into a format suitable for the display panel PNL. The host system 14 transmits timing signals Vsync, Hsync, DE, and MCLK together with the digital video data of the input image to the timing controller 12.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

10: display panel drive circuit 12: timing controller
14: host system PNL: display panel
VD: vertical data line VG: vertical gate line
VC: vertical common line HG: horizontal gate line
HC: horizontal common line

Claims (3)

Data lines, gate lines crossing the data lines, a first common line parallel to the data lines and across a center of a pixel array; And a display panel parallel to the gate lines and having a second common line crossing the center of the pixel array.
The pixel array includes first to fourth pixel groups divided by the first and second common lines,
The pixel groups adjacent to the left and right have no data line at the boundary, the first common line is formed at a position thereof, and has a pixel structure symmetrical with each other about the first common line.
Up and down neighboring pixel groups have no gate line at a boundary, the second common line is formed at a position thereof, and has a pixel structure symmetric with each other about the second common line.
And the first common line and the second common line are connected to a common electrode of each pixel to supply a common voltage. The method of claim 1,
The pixel array
A first pixel group disposed in a left half portion of the upper half of the pixel array;
A second pixel group disposed at a right half of the upper half of the pixel array and including pixels having left and right symmetrical structures compared with pixels of the first pixel group;
A third pixel group disposed at a lower half of a left side of the pixel array and including pixels having a vertically symmetrical structure compared to pixels of the first pixel group; And
A fourth pixel group disposed at a right half of the lower half of the pixel array, and having a left-right symmetrical structure compared to pixels of the second pixel group, and having left-right symmetrical pixels compared to pixels of the third pixel group; Liquid crystal display device characterized in that. The method of claim 2,
In the pixels of the first pixel group, the data lines are formed on the left side of the pixel, and in the pixels of the first pixel group, the gate lines are formed on the upper side of the pixel,
In the pixels of the second pixel group, the data lines are formed on the right side of the pixel, and in the pixels of the second pixel group, the gate lines are formed on the upper side of the pixel,
In the pixels of the third pixel group, the data lines are formed on the left side of the pixel, and in the pixels of the third pixel group, the gate lines are formed below the pixel,
And the data lines are formed at the right side of the pixel in the pixels of the fourth pixel group, and the gate lines are formed at the bottom of the pixel in the pixels of the fourth pixel group.

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