KR102050828B1 - Method for accelerating open virtual switch using parallel computation and open virtual switch using the same - Google Patents

Abstract

Disclosed are an accelerating method of an open virtual switch using parallel calculation and an open virtual switch using the same which can increase a data processing amount of an entire network. According to an embodiment of the present invention, the accelerating method of an open virtual switch using parallel calculation is a packet processing method performed by an open virtual switch. The accelerating method comprises: a step of performing parallel masking on n (n is a natural number higher than or equal to 2) packets received from the outside to generate one or more vectors; a step of applying a hash function to the vectors to derive n hash values; and a step of looking up the hash values in a hash table to derive n matching rules mapped to the hash values.

Description

TECHNICAL FOR ACCELERATING OPEN VIRTUAL SWITCH USING PARALLEL COMPUTATION AND OPEN VIRTUAL SWITCH USING THE SAME}

The present invention relates to a virtual switch, and more particularly, to an acceleration method of an open virtual switch using parallel operation and an off-virtual switch using the same, in which a plurality of packets are operated in parallel to improve operation efficiency.

The contents described in this section merely provide background information on the present invention and do not constitute a prior art.

As new IT technologies, such as big data, the Internet of Things (IOT), and cloud computing, emerge, and as mobile devices proliferate, the amount of traffic that needs to be handled in a network is too geometric to handle in a hardware-centric network architecture. It is increasing in water supply.

To solve this problem, Software Defined Network (SDN), a next-generation networking technology that can easily handle network routing, control, and complex operation management through software programming, has been removed from the conventional hardware-oriented network structure. It is introduced.

The function of network routing in a software defined network is performed by Open vSwitch (OvS), which is an open source based virtual switch. The general configuration and data processing flow for this OvS is shown in FIG.

As shown in FIG. 1, the OvS 500 may generally include an Exact Match Cache 510, a Megaflow Cache 520, and an Open Flow Table 530. When a packet is input from a physical or virtual interface, the unique identifier of the input packet is the Exact Match Cache 510, which provides the fastest processing for a limited number of table entries, and the Megaflow Cache, which implements wildcard matching. 520 and the Open Flow Table 530 in order.

First, in the EMC 510, if the identifier of a packet matches or hits exactly the entry of every field in this table, the packet is sent to a preset destination; otherwise (Miss ) Is passed to the Megaflow Cache 520.

The identifier of the packet transmitted to the Megaflow Cache 520 is determined by matching with a plurality of sub-tables existing in the Megaflow Cache 520 through a wildcard matching method.

As a result, if a match is transmitted, the corresponding packet is transmitted to a predetermined destination. If not, the corresponding packet is transmitted to the Open Flow Table 530 to determine whether an additional match is made.

In the megaflow cache 520, the determination of a match is performed through a one-to-one comparison between any one of a plurality of subtables and an identifier of a packet. Therefore, when a plurality of packets are input to the OvS 500, a one-to-one comparison between each of the plurality of packets and each of the plurality of subtables is performed until the matching determination for all the packets is completed, so that a lot of time is spent in the matching determination process. This can take a while.

Furthermore, the resources required to determine whether a packet is matched in the megaflow cache 520 occupy a large part of the overall CPU cycle of the OvS 500, and this increase in the time required causes the OvS 500 to perform a switching function. The time required to do this also increases, which may cause a problem of lowering the data throughput of the entire network.

An embodiment of the present invention provides an open virtual switch and a method for accelerating packet processing in a megaflow cache by applying parallel operation processing to a plurality of packets, thereby increasing data throughput of the entire network. The main purpose is to provide.

According to an embodiment of the present invention, as a packet processing method performed in an open virtual switch, parallel masking is performed on n (n is a natural number of two or more) packets received from the outside. masking to generate one or more vectors; Deriving the n hash values by applying a hash function to the vector; And deriving the n matching rules mapped to each of the hash values by looking up each of the hash values in a hash table. Provide an acceleration method.

According to another embodiment of the present invention, as an open virtual switch, one or more parallel masking is performed on n (n is a natural number of two or more) packets received from the outside. A vector generator for generating a vector; A first hashing unit configured to derive the n hash values by applying a hash function to the vector; And a second hashing unit configured to lookup each of the hash values with respect to one or more hash tables to derive the n matching rules mapped to each of the hash values. Provide an open virtual switch.

As described above, the present invention is configured to reduce the time required to process a plurality of packets in the megaflow cache by applying parallel operation processing on the plurality of packets, so that the packet processing speed of the virtual switch and the overall network It can increase data throughput.

In addition, considering that resources consumed in the megaflow cache occupy a large part of the CPU cycle of the virtual switch, the efficiency of the above effects provided by the present invention can be further increased.

1 is a diagram illustrating a general configuration and data processing flow of a conventional OvS.
2 is a block diagram schematically showing the configuration of the OvS according to the present invention.
3 is a flowchart illustrating an embodiment of the present invention for processing a packet by using the configuration of the OvS shown in FIG. 2.
4 is a diagram illustrating an example of a packet miniflow and a mask miniflow utilized for vector generation.
5 is a view for explaining an example of the present invention for vector generation.
6 is a flowchart for explaining an embodiment of the present invention for vector generation.
7 is a diagram for explaining an embodiment of the present invention for a hash table query.
8 is a flowchart illustrating an embodiment of the present invention for a hash table query.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are assigned to the same components as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

In addition, in describing the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are only for distinguishing the components from other components, and the nature, order or order of the components are not limited by the terms. Throughout the specification, when a part is said to include, 'include' a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated. . In addition, as described in the specification. The terms 'unit' and 'module' refer to a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software.

2 is a block diagram schematically showing the configuration of an open virtual switch (hereinafter referred to as a "virtual switch") 100 according to the present invention, Figure 3 is a configuration of the virtual switch 100 shown in FIG. A flowchart for describing an embodiment of the present invention for processing a packet by using the present invention.

Hereinafter, with reference to Figures 2 and 3 with respect to the configuration of the virtual switch 100 according to the present invention and a method for the virtual switch 100 of the present invention to process a plurality of packets in parallel using these configurations. This will be explained in detail.

As shown in FIG. 2, the virtual switch 100 of the present invention may include a vector generator 110, a first hashing unit 120, a second hashing unit 130, and a verification unit 140. The vector generation unit 110 of the present invention may include a selection unit 111, a calculation unit 113, and a generation unit 115, and the second hashing unit 130 of the present invention may include a first unit. The rod unit 131, the second rod unit 133, and the lead unit 135 may be configured to be included.

In FIG. 2, the Open Flow Table 200 is represented as being located outside the virtual switch 100, but this indicates that each of the internal components of the present invention shown in FIG. 2 is located in the Megaflow cache of the virtual switch 100. It is an expression to bet.

That is, as described above, the present invention aims to speed up the conventional virtual switch by allowing the self-function of the Megaflow cache to be performed more quickly, so that each internal configuration of the present invention shown in FIG. 2 is located in the Megaflow cache. It is desirable to see that.

First, n packets are received from the outside to the vector generator 110 of the present invention (S310). Here, the present invention corresponds to the invention for improving the time efficiency for packet processing by processing a plurality of packets in parallel, n means a natural number of two or more.

The vector generator 110 of the present invention generates one or more vectors by performing parallel masking on the received n packets (S320). The number of generated vectors is the same as the number of bits indicating the presence of a mask value in a mask miniflow to be described later, which will be described later.

As will be described later, masking means a method of deriving a packet value arranged at a desired position by calculating each of the n packet values and the mask value. In addition, the vector refers to an array, a frame or a stream in which the values of masking are arranged one-dimensionally.

Based on the general megaflow cache, the result values obtained by performing masking may correspond to integer values having a data size of 64 bits.

When one or more vectors are generated, the first hashing unit 120 of the present invention derives n hash values by applying a predetermined hash function to each of the one or more vectors (S330). Since the hash function is applied to the vector to derive the hash value, the above-described vector may be regarded as a hash key.

When the hash value is generated, the second hashing unit 130 of the present invention inquires a hash key matching the hash value derived from the first hashing unit 120 among the hash keys stored in one or more hash tables. lookup) and n matching rules are mapped or associated with each matching hash key (S340).

When the matching rule is derived, the verification unit 140 of the present invention checks whether the matching rule matches the hash key that is actually matched (S350), performs an action when it matches (S370), and does not match. The packet may be transferred to the Open Flow Table 200 so that packet processing is performed in the Open Flow Table 200 (S360), or it may be transferred to another hash table to perform an additional inquiry by itself (S365).

Here, Action means transmitting the packet to a preset destination. Hereinafter, an Action is used to indicate that a specific packet is transmitted to a predetermined destination of the specific packet.

4 is a diagram illustrating an example of a packet miniflow and a mask miniflow utilized for vector generation, FIG. 5 is a diagram for explaining an example of the present invention for vector generation, and FIG. A flowchart for explaining an embodiment of the present invention for vector generation.

Hereinafter, an embodiment of the present invention for generating one or more vectors by performing parallel masking on n packets will be described in detail with reference to FIGS. 4 to 6.

In order to generate one or more vectors, the vector generator 110 of the present invention may include a selector 111, a calculator 113, and a generator 115, as shown in FIG. 2.

First, the selector 111 of the present invention selects one or more mask bits having a first bit value from a mask miniflow. If it can be distinguished from other bit values that do not correspond to the screening target, the first bit value corresponding to the screening target may be one of 1 or 0. In the following description, an embodiment in which the first bit value corresponding to the selection target is 1 will be described.

Since the miniflow means a compressed form of the flow structure, the mask miniflow corresponds to the compressed form of the mask flow structure, and the packet miniflow described later corresponds to the compressed form of the packet, that is, the packet header structure.

In addition, each miniflow may be in the form of a bit map as shown in FIG. 4, where 0 bits indicate that a corresponding field is set to 0 (not present) in a flow structure, and 1 bit is a flow. It may indicate that the corresponding field in the structure is set to a non-zero value.

Therefore, the miniflow may perform a function of indicating whether a value other than 0 exists in a field corresponding to each bit constituting the miniflow in the flow structure.

Referring to FIGS. 4 and 5, an example of a miniflow will be described. In the case of a mask miniflow, a total of four bits are represented by one bit in a right-to-left direction (FIG. 4). As expressed at the top of 5, a non-zero value (Mask value 0 to Mask value 3) in the left to right direction may be arranged as a mask value.

In addition, in case of packet miniflow 0, a total of 5 bits are represented by 1 bit from the right to the left direction (FIG. 4), and thus, a value other than 0 from the left to the right direction is expressed as shown at the top of FIG. 5. It may be arranged in a value (Packet value 0-0 to Packet value 0-4).

In the state in which the miniflow is configured in this way, the selector 111 of the present invention determines whether the k-th (k is an integer equal to 0 or less than the number of bits of the mask miniflow) of the mask miniflow corresponds to 1 ( S610).

If the kth bit is 0, this means that there is no mask value corresponding to the kth miniflow bit (0) (since the kth miniflow bit does not correspond to the first bit value), so that the selection of the present invention The unit 111 performs determination on the next bit (S620).

When the mask miniflow bit (mask bit) corresponding to 1 bit is selected by repeatedly performing this process (S630), the selector 111 of the present invention is the same position as the mask bit among the bits of the n packet miniflows. Selects the packet bit among the packet miniflow bits arranged in the.

Specifically, the selector 113 of the present invention first determines whether a packet miniflow bit arranged at the same position as the mask bit has a 1-bit value that is the same bit value as the mask bit (S640), and selects a 1-bit value. The branched packet miniflow bits are selected as packet bits (S650).

When bit selection is completed, the operation unit 113 of the present invention performs a parallel AND operation on the mask value mapped to the mask bit and the packet value mapped to the packet bit (S660), and the generation unit 115 of the present invention. Sequentially arranges the result of the parallel AND operation and 0 to generate one or more vectors (S680).

0 used for vector generation means that a corresponding position of the vector is set to 0 when a packet miniflow bit arranged at the same position as the mask bit has a zero bit value that is a bit value not equal to the mask bit.

Based on the general Megaflow cache (when the result values derived from the AND operation are integer values each having a 64-bit data size), the vector may consist of 64 * n bits in which n 64-bit integer values are arranged. .

According to an embodiment, if one wishes to construct a vector defined as 32 * n bits, the results of AND operations that can be arranged in a single 64 * n bit vector can be arranged in two 32 * n bit vectors.

A parallel AND operation process and a vector generation process will be described with reference to FIGS. 4 and 5 as follows.

First, based on the right to left direction, since the mask miniflow has one bit value (first bit value) in the seventh, tenth, eleventh, and thirteenth bits, these bits are selected as mask bits.

In addition, bits having a bit value (first bit value) of the seventh, tenth, eleventh, and thirteenth bits of the packet miniflow, respectively (the tenth and eleventh bits in the case of packet miniflow 0, and the packet miniflow 1). In the case of the 7th and 11th bits, and the 13th bit in the case of Packet miniflow 15), the packet bits are selected.

 Next, as shown in FIG. 5, a mask value mapped to the first mask bit (the seventh mask miniflow bit) (Mask value 0) and a packet value mapped to the mask bit that is the seventh bit of packet miniflow 1 are mapped. The AND operation is performed on (Packet value 1-1), the result of the AND operation is arranged in the second slot of Vertor 0, and 0 is arranged in the remaining slots.

In addition, a mask value (Mask value 1) mapped to the second mask bit (the tenth mask miniflow bit) and a packet value mapped to the mask bit (the packet value 0-2) mapped to the tenth bit of the packet miniflow 1 are targeted. The AND operation is performed, and the result of the AND operation is arranged in the first slot of Vertor 1, and 0 is arranged in the remaining slots.

Furthermore, the mask value (Mask value 2) mapped with the 3rd mask bit (the 11th mask miniflow bit) and the packet value (Packet value 0-3) mapped with the mask bit which is the 11th bit of packet miniflow 0 are targeted. The AND operation is performed, and the result of the AND operation is arranged in the first slot of Vertor 2.

At the same time, the mask value mapped to the 3rd mask bit (the 11th mask miniflow bit) (Mask value 2) and the packet value mapped to the mask bit (11th bit of packet miniflow 1) (Packet value 1-2) The AND operation is performed on), the result of the AND operation is arranged in the second slot of Vertor 2, and 0 is arranged in the remaining slots of Vector 2.

Furthermore, the mask value (Mask value 3) mapped with the fourth mask bit (13th mask miniflow bit) and the packet value (Packet value 15-3) mapped with the mask bit, which is the 13th bit of packet miniflow 15, are mapped. The AND operation is performed on the object, and the result of the AND operation is arranged in the fourth slot of Vertor 3, and 0 is arranged in the remaining slots of Vector 3.

This process is performed in parallel (simultaneously) for packet values 0-15, resulting in vectors as shown at the bottom of FIG. 4 and 5 correspond to a diagram illustrating a parallel AND operation process and a vector generation process on the assumption that a total of 16 packets (n = 16) are input. Therefore, the number of slots in the vector shown at the bottom of FIG. 5 may vary according to the number of input packets.

As represented in FIGS. 4 and 5, the number of generated vectors is equal to the number of 1-bit values included in the mask miniflow, that is, the number of first bits. Therefore, when the number of first bits included in the mask miniflow is different from the number of first bits included in the figure, the number of generated vectors may also be different.

As described above, the first hashing unit 120 of the present invention is configured to derive n hash values by applying a hash function (as a hash key) to the vector generated by the vector generation unit 110.

Therefore, considering that the number of vectors can be varied, the hash function is preferably made of a murmur hash function that is adaptive to the change in the number of hash keys (which can lower hash collisions).

As described above, the present invention is configured such that the AND operation process and the vector generation process are performed in parallel (simultaneously), thereby providing a higher acceleration effect than the conventional virtual switch which performs the processing on a plurality of packets in series. Can be.

In addition, the present invention can accelerate the Megaflow cache that occupies most of the resources of the virtual switch 100 through parallel operation, thereby further increasing the effect of the acceleration effect.

7 is a diagram illustrating an embodiment of the present invention for a hash table query, and FIG. 8 is a flowchart illustrating an embodiment of the present invention for a hash table query. Hereinafter, an embodiment of the present invention for hash table inquiry will be described in detail with reference to FIGS. 7 and 8.

One or more hash tables are stored in the second hashing unit 130 of the present invention, and the one or more rules P1, P2, P3, P4 and P5 and one or more hash tables are shown in FIG. Hash values for each rule can be arranged.

The hash values for each rule may have the same values as the hash values derived from the first hashing unit 120, and the rules are mapped to the hash values matching the rules.

In FIG. 7, K4 input to the hash table (inquired in the hash table) represents one hash value corresponding to the search object among the n hash values derived from the first hashing unit 120. Hereinafter, a hash value corresponding to an inquiry target among n hash values is referred to as a target hash value K4.

As shown in FIG. 7, the first load unit 131 of the present invention loads the target hash value K4 into all slots of a first vector (frame in which K4 is arranged in all slots) including a plurality of slots. (S810). In other words, the target hash value K4 is arranged in all slots constituting the first vector.

In addition, the second rod 133 of the present invention includes a plurality of slots including buckets K1, K2, K3, K4, and K5 including a target hash value K4 among one or more buckets included in the hash table. It is loaded in the second vector consisting of (S820).

In this case, the second rod unit 133 sequentially loads the buckets K1, K2, K3, K4, and K5 from the slots at the right end of the second vector, as shown in FIG. Load sequentially from the left end of the slot (S820).

The reason for loading the buckets K1, K2, K3, K4, K5 from the right or left end slot of the second vector is to accurately grasp the relative position of the target hash value K4.

In this configuration, the derivation unit 135 of the present invention first selects a target slot that is a slot having the same value (hash value) as the slot included in the first vector among the slots included in the second vector ( S830).

As described above, since the target hash value K4 is loaded in all slots in the first vector, and the buckets K1, K2, K3, K4, and K5 are loaded in the second vector, they are arranged in the same position. Comparing the slots of the first vector and the slots of the second vector, the bit map shown in FIG. 7 may be configured.

In this bitmap, a zero bit value means that a non-identical value is arranged in a slot of a first vector and a slot of a second vector arranged at the same position, and a one bit value is a zero value arranged in the same position. It means that the same value is arranged in the slot of the 1 vector and the slot of the second vector. Accordingly, the derivation unit 135 of the present invention may select a target slot using a slot in which a 1-bit value is arranged in the bitmap.

When the target slot is selected, the derivation unit 135 of the present invention selects a matching rule corresponding to the index information of the target slot from the hash table (S840). The index information of the target slot means a relative position where the target slot is arranged in the first vector, the second vector, or the bit map.

As shown in FIG. 7, since the target slot is arranged in the fourth slot or bit of the bit map in the right-to-left direction, the derivation unit 135 of the present invention is the fourth in the left-to-right direction of the hash table. The rule P4 located in the slot is selected as a matching rule (S840). When the matching rule is selected, the derivation unit 135 of the present invention returns the selected matching rule P4 (S850) to complete the matching rule derivation process.

As described above, since the present invention is configured to derive a matching rule corresponding to the target hash value through a single query using the target hash value loading and the bucket loading, the hash table is searched a plurality of times to select a value matching the target hash value. Computation efficiency can be increased as compared to the conventional method.

The efficiency of this operation leads to the acceleration of the Megaflow cache itself, and the present invention can provide a higher acceleration effect in that the resources consumed in the Megaflow cache occupy a large part of the total resources of the virtual switch 100. .

In FIGS. 3, 6 and 8, the processes S310 to S370, the S610 to S680, and the S810 to S850 are sequentially executed. However, the technical idea of the exemplary embodiment of the present invention is exemplarily described. It is only. In other words, one of ordinary skill in the art to which an embodiment of the present invention belongs may execute the process by changing the order described in FIGS. 3, 6 and 8 without departing from the essential characteristics of the embodiment of the present invention. Since one or more of S310 to S370, S610 to S680, and S810 to S850 may be applied in various modifications and modifications in parallel, FIG. 6 is not limited to the time series order.

Meanwhile, the processes illustrated in FIGS. 3, 6, and 8 may be implemented as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. That is, the computer-readable recording medium may be a magnetic storage medium (for example, a ROM, a floppy disk, a hard disk, etc.), an optical reading medium (for example, a CD-ROM, DVD, etc.) and a carrier wave (for example, the Internet Storage medium). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The above description is merely illustrative of the technical idea of the present embodiment, and those skilled in the art to which the present embodiment belongs may make various modifications and changes without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of the present embodiment but to describe the present invention, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present embodiment.

100: virtual switch
110: vector generation unit 120: first hashing unit
140: verification unit 130: second hashing unit
111: selection unit 113: calculation unit
115: generation unit 131: first load unit
133: second rod portion 135: derivation portion

Claims (8)

A packet processing method performed in an open virtual switch,
Generating at least one vector by performing parallel masking on n (n is a natural number of two or more) packets received from the outside;
Deriving n hash values by applying a hash function to the vector; And
Looking up each of the hash values in at least one hash table to derive n matching rules mapped to each of the hash values,
Deriving the matching rule,
Loading a target hash value corresponding to an inquiry target among the hash values into all slots of a first vector including a plurality of slots;
Among the one or more buckets included in the hash table, the bucket including the target hash value is loaded into a second vector consisting of a plurality of slots, and sequentially loaded from slots located at right or left ends of the second vector. Doing; And
Selecting a target slot having the same value as the slot of the first vector among the slots of the second vector, and deriving the matching rule corresponding to the index information of the target slot from the hash table. Acceleration method of open virtual switch using parallel operation. The method of claim 1, wherein generating the vector comprises:
Selecting one or more mask bits having a first bit value from a mask miniflow, and each of the packet bits having the first bit value among the bits arranged at the same position as the mask bit in each of the n packet miniflows Screening;
Performing a parallel AND operation on each of the packet values mapped to the packet bits and a mask value mapped to the mask bits; And
And arranging the results of the parallel AND operations sequentially to generate the one or more vectors. The method of claim 2, wherein the hash function,
Acceleration method of an open virtual switch using parallel operation, characterized in that the murmur hash function. delete As an Open Virtual Switch,
A vector generator for generating one or more vectors by performing parallel masking on n (n is a natural number of two or more) packets received from the outside;
A first hashing unit configured to derive n hash values by applying a hash function to the vector; And
A second hashing unit for looking up each hash value to one or more hash tables to derive n matching rules mapped to each of the hash values,
The second hashing unit,
A first load unit which loads a target hash value corresponding to a search target among the hash values into all slots of a first vector including a plurality of slots;
Among the one or more buckets included in the hash table, the bucket including the target hash value is loaded into a second vector consisting of a plurality of slots, and sequentially loaded from slots located at right or left ends of the second vector. A second rod unit; And
Selecting a target slot having the same value as the slot of the first vector among the slots of the second vector, and including a derivation unit for deriving the matching rule corresponding to the index information of the target slot from the hash table Open virtual switch based on parallel operation. The method of claim 5, wherein the vector generation unit,
Selecting one or more mask bits having a first bit value from a mask miniflow, and each of the packet bits having the first bit value among the bits arranged at the same position as the mask bit in each of the n packet miniflows Selection unit for selecting the;
An operation unit configured to perform a parallel AND operation on each of the packet values mapped to the packet bits and a mask value mapped to the mask bits; And
And a generator configured to sequentially arrange the results of the parallel AND operation to generate the at least one vector. The method of claim 6, wherein the hash function,
Open virtual switch based on parallel operation, characterized by a murmur hash function. delete

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