KR102020935B1 - Display device having touch sensors and control method of gate driving circuit thereof - Google Patents
Display device having touch sensors and control method of gate driving circuit thereof Download PDFInfo
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- KR102020935B1 KR102020935B1 KR1020120144156A KR20120144156A KR102020935B1 KR 102020935 B1 KR102020935 B1 KR 102020935B1 KR 1020120144156 A KR1020120144156 A KR 1020120144156A KR 20120144156 A KR20120144156 A KR 20120144156A KR 102020935 B1 KR102020935 B1 KR 102020935B1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention relates to a display device having touch sensors and a method for controlling a gate driving circuit thereof, the display device comprising: a display panel including a pixel array and touch sensors; A gate driving circuit including a shift register in which stages are cascadedly connected; And a timing controller configured to control the gate driving circuit by supplying a gate start pulse and a gate shift clock to the gate driving circuit. The timing controller is configured to high logic a voltage of a gate shift clock supplied to a pull-up transistor of a stage I (I is a positive integer of 2 or more) connected to a gate line at which a display period starts after the touch sensor period. While maintaining the level, the gate shift clock supplied to the pull-up transistors of the stages other than the I stage is kept at the low logic level.
Description
The present invention relates to a display device having touch sensors and a method of controlling a gate driving circuit thereof.
A user interface (UI) enables communication between a person (user) and various electric and electronic devices, so that the user can easily control the device as desired. Representative examples of the user interface include a keypad, a keyboard, a mouse, an On Screen Display (OSD), a remote controller having infrared communication or radio frequency (RF) communication. User interface technology continues to evolve in the direction of increasing user sensitivity and ease of operation. In recent years, user interfaces have evolved into touch UIs, voice recognition UIs, 3D UIs, and the like.
Touch UI is being adopted to portable information devices, and it is being applied to home appliances. The capacitive touch sensing system has the advantage that the touch screen structure has higher durability and clarity than the conventional resistive method, and can be applied to various applications. Recently, touch screens are mostly implemented in a capacitive manner.
The touch sensors of the touch screen may be disposed on or embedded in the display device. The driving circuit of the display device includes a data driving circuit for generating a data voltage and a gate driving circuit for generating a gate pulse (or scan pulse) in synchronization with the data voltage. When touch sensors of a touch screen are embedded in the display device, since touch sensors and pixels of the display device are disposed close to each other, noise is introduced into the touch sensors due to a driving signal of the display device when data is written to the pixels of the display device. Easy to be When touch sensors are embedded in the display device, a period of writing data into the display device and a period of driving the touch screen are time-divided. For example, one frame period is divided into two, data is written into pixels during one of the periods, and the touch sensors are driven during the remaining periods.
Recently, the screen of the display device is divided into a plurality of pixel blocks B 1 to B N and a touch screen is divided into a plurality of sensor blocks S 1 to S M as shown in FIG. A method of alternately driving the blocks B 1 to B N and the touch sensor blocks S 1 to S M has been proposed. For example, the first pixel blocks (B 1), the first touch sensor block (S 1), a second pixel block (B 2), the second touch sensor block (S 2) in order of pixel blocks (B 1 ~ B N ) and the touch sensor blocks S 1 to S M are alternately driven. In FIG. 1, Vsync is a vertical synchronization signal that defines one frame period. In this driving scheme, the gate driving circuit outputs a gate pulse while the pixel blocks are driven, and should not output the gate pulse during the period in which the touch sensor block is driven. Therefore, there is a need for a control method that can temporarily stop and resume the output of the gate driving circuit.
The present invention provides a display device and a method for controlling the gate driving circuit having touch sensors capable of temporarily stopping the output of the gate driving circuit during the touch sensor section and resuming the output to resume the display section without changing the luminance.
According to an exemplary embodiment of the present invention, a display device having touch sensors includes: a display panel including a pixel array and touch sensors; A gate driving circuit including a shift register in which stages are cascadedly connected; And a timing controller configured to control the gate driving circuit by supplying a gate start pulse and a gate shift clock to the gate driving circuit.
The pixels of the pixel array of the display panel are driven in the display driving section, and the touch sensors are driven in the touch sensor section.
The timing controller is configured to supply a voltage of a gate shift clock supplied to a pull-up transistor of a stage I (I is a positive integer of 2 or more) connected to a gate line at which the display period starts after the touch sensor period during the touch sensor period. While maintaining the high logic level, the gate shift clock supplied to the pull-up transistors of the stages other than the I stage is maintained at the low logic level.
The first clock of the gate shift clock supplied to the pull-up transistor of the first stage connected to the first (I is a positive integer of 2 or more) gate line at which the display period starts is maintained at a high logic level during the touch sensor period. .
The method of controlling a gate driving circuit of the display device may include driving pixels of a pixel array of the display panel in a display driving section and driving the touch sensors in a touch sensor section; And a high logic level during the touch sensor period, the voltage of the gate shift clock supplied to a pull-up transistor of a stage I (I is a positive integer of 2 or more) connected to the gate line where the display period starts after the touch sensor period. While maintaining the gate shift clock supplied to the pull-up transistors of the stages other than the I stage, at a low logic level.
The present invention maintains the clock supplied to the pull-up transistor of the stage of the gate driving circuit that outputs the first gate pulse at a specific logic level during the touch sensor period when the display period is resumed. As a result, the display device of the present invention can resume the display section without line noise when resuming the output after temporarily stopping while the touch sensor block is being driven.
FIG. 1 is a diagram illustrating an example in which pixel blocks and touch sensor blocks are alternately driven within one frame period.
2 is a diagram illustrating a touch sensing system according to an embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of the touch screen shown in FIG. 2.
4 to 6 illustrate various combinations of a display panel and a touch screen.
7 is a diagram illustrating an example in which GIP circuits are disposed on both sides of a display panel.
FIG. 8 is a block diagram illustrating an exemplary shift register configuration of the GIP circuit of FIG. 7.
FIG. 9 is a diagram illustrating a circuit configuration of the stage illustrated in FIG. 8.
10 is a timing diagram illustrating an example of maintaining gate shift clocks at a low logic level in a touch sensor period.
FIG. 11 is a waveform diagram illustrating noise that appears at a timing of inverting to a high logic level immediately after the gate shift clocks are maintained at a low logic level as shown in FIG. 10.
12 is a waveform diagram illustrating a control method of a gate driving circuit according to an exemplary embodiment of the present invention.
The touch sensing system of the present invention may be implemented as a capacitive touch screen that senses a touch input through a plurality of capacitive sensors. The capacitive touch screen includes a plurality of touch sensors. Each of the touch sensors includes a capacitance when viewed in equivalent circuitry. The capacitive touch screen may be divided into self capacitance and mutual capacitance. The self capacitance is formed along a single layer of conductor wiring formed in one direction. Mutual capacitance is formed between two orthogonal conductor wires. In the following embodiments, a mutual capacitive touch screen is illustrated, but is not limited thereto.
The display device of the present invention is a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode display (Organic Light Emitting Display) , OLED), and electrophoretic display devices (Electrophoresis, EPD). In the following embodiments, a liquid crystal display device is described as an example of a flat panel display device, but is not limited thereto.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
1 to 5, the display device of the present invention includes a display panel PNL, a display driving circuit, a touch screen TSP, a touch screen driving circuit, and the like.
The display panel PNL includes a liquid crystal layer formed between two substrates. The pixel array of the display panel PNL is formed by m (m is a positive integer) data lines D1 to Dm and n (n is a positive integer) gate lines G1 to Gn. M x n pixels formed in the defined pixel region. Each of the pixels is connected to TFTs formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, a pixel electrode to charge a data voltage, and a pixel electrode. Storage capacitors (Cst) for maintaining the voltage and the like.
Black matrices, color filters, and the like are formed on the upper substrate of the display panel PNL. The lower substrate of the display panel PNL may be implemented as a color filter on TFT (COT) structure. In this case, the black matrix and the color filter may be formed on the lower substrate of the display panel PNL. The common electrode supplied with the common voltage may be formed on the upper substrate or the lower substrate of the display panel PNL. Polarizing plates are attached to each of the upper and lower substrates of the display panel PNL, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on an inner surface of the display panel PNL. A column spacer is formed between the upper substrate and the lower substrate of the display panel PNL to maintain a cell gap of the liquid crystal cell.
The backlight unit may be disposed under the rear surface of the display panel PNL. The backlight unit is implemented as an edge type or direct type backlight unit to emit light to the display panel PNL. The display panel PNL may be implemented in any known liquid crystal mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, or fringe field switching (FFS) mode.
The display driving circuit includes the
The
The
The
The gate timing control signal includes a gate start pulse (GSP), a gate shift clock, a gate output enable signal (GOE), and the like. The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and the like. The gate start pulse GSP is input to the shift register to control the start timing of the shift resist. The gate shift clock GSC is input to the shift register to control the output shift timing of the shift resist. In the shift register of the
The
As shown in FIG. 1, the display device of the present invention sequentially drives the pixel blocks and the touch sensor blocks within one frame period, and alternately drives the pixel blocks and the touch sensor blocks. For example, as shown in FIG. 1, the pixel blocks in the order of the first pixel block B 1 , the first touch sensor block S 1 , the second pixel block B 2 , and the second touch sensor block S 2 . B 1 to B N and touch sensor blocks S 1 to S M are alternately driven. The method of alternately driving the pixel block and the touch sensor block within one frame period may be applied by the method proposed through Korean Patent Application No. 10-2012-0078146 (July 18, 2012) filed by the present applicant. This time division method is controlled by the
The touch screen TSP is bonded on the upper polarizing plate POL1 of the display panel PNL as shown in FIG. 3, or formed between the upper polarizing plate POL1 and the upper substrate GLS1 of the display panel PNL as shown in FIG. 4. Can be. In addition, the touch sensors Cts of the touch screen TSP may be embedded in the lower substrate in an in-cell type together with the pixel array in the display panel PNL as shown in FIG. 5. 3 to 5, "PIX" means a pixel electrode of a liquid crystal cell, "GLS2" means a lower substrate, and "POL2" means a lower polarizer, respectively.
The touch screen TSP includes Tx lines (Tx1 to Txj, j is a positive integer smaller than n), and Rx lines (Rx1 to Rxi and i are positive amounts smaller than m) intersecting the Tx lines (Tx1 to Txj). Integer), and i × j touch sensors Cts formed at intersections of the Tx lines Tx1 to Txj and the Rx lines Rx1 to Rxi. Each of the touch sensors Cts includes mutual capacitance.
The touch screen driving circuit includes a
The
The
The
The
The
FIG. 7 is a diagram illustrating an example in which the GIP circuits GIP_L and GIP_R are disposed on both sides of the display panel PNL. FIG. 8 is a block diagram illustrating an exemplary shift register configuration of the GIP circuit of FIG. 7. FIG. 9 is a diagram illustrating a circuit configuration of the stage illustrated in FIG. 8.
7 to 9, each of the GIP circuits GIP_L and GIP_R disposed on both sides of the pixel array includes a gate start pulse GSP and a gate shift clock GCLK1-L to GCLK4-L and GCLK1-R to GCLK4. -R) includes a shift register for sequentially inputting a gate pulse. The gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R exemplify four-phase clocks, but are not limited to four-phase clocks because two- or six-phase clocks are possible.
The first GIP circuit GIP_L is disposed outside the left side of the pixel array. The first first GIP circuit GIP_L is connected to the odd-numbered gate lines G1, G3, ... Gn-1 of the pixel array and connected to the gate lines G1, G3, ... Gn-1. Gate pulses are output sequentially. The second GIP circuit GIP_R is disposed outside the right side of the pixel array. The shift register of the second GIP circuit GIP_R is connected to the even-numbered gate lines G2, G4, ... Gn of the pixel array to apply gate pulses to the gate lines G2, G4, ... Gn. Output sequentially. In FIG. 7, GCLK1-L to GCLK4-L are four-phase gate shift clocks applied to the first GIP circuit GIP_L, and GCLK1-R to GCLK4-R are four-phase gate shifts applied to the second GIP circuit GIP_R. It is a clock. The gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R partially overlap each other. The GIP circuits GIP_L and GIP_R generate an output in synchronization with the rising edges of the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R. Therefore, the Nth (N is a positive integer of 2 or more) gate pulse output from the GIP circuits GIP_L and GIP_R overlaps the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R. The width overlaps with the rear part of the N-th gate pulse.
Each of the GIP circuits GIP_L and GIP_R includes a plurality of stages S (N-1) to which gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are input and connected in a dependent manner. S (N + 4)).
Each of the stages S (N-1) to S (N + 1) includes a first transistor T1, a second transistor T2, a third transistor T3, and the like. T3) may be implemented as an n type MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
The N-th stay S (N) receives the first, second, and fourth clocks GCLK1, GCLK2, and GCLK4, and outputs Vout of the N-th stage S (N-1). (N-1)) and the output Vout (N + 1) of the N + 1th stage S (N + 1). The output Vout (N-1) of the N-th stage S (N-1) is supplied as a gate pulse to the N-th gate line and the start pulse of the N-th stage S (N). It is input to the terminal.
In the Nth stage S (N), the first transistor T1 outputs the output Vout (N-1) of the N-1st stage S (N-1) in response to the first clock GCLK1. The Q node Q (N) is charged with the voltage of. When the second transistor T2 is supplied with the second clock GCLK2 generated after the first clock GCLK1 when the Q node Q (N) is charged, the second transistor T2 supplies the voltage of the second clock GCLK2. It is a pull-up transistor that supplies an output node and raises the voltage Vout (N) of the output node. The third transistor T3 is a pull-down transistor that discharges the voltage of the output node in response to the fourth clock GCLK4.
Hereinafter, a period during which the pixel blocks are driven will be referred to as a display period, and a period during which the touch sensor blocks are driven will be referred to as a touch sensor period. The
Referring to FIG. 10, the display periods Td1, Td2, and Td3 and the touch sensor periods Tt1, Tt2, and Tt3 are time-divided within one frame period. Assume an example in which each of the pixel blocks B 1 to B N includes pixels arranged in 19 lines. In this example, one pixel block includes nineteen gate lines. During the first display period Td1, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are normally generated in one horizontal period so that the first to nineteenth gate lines G1 to G19. Gate pulses are supplied sequentially. Subsequently, during the first touch sensor period Tt1, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are maintained at a low logic level. Subsequently, the clocks GCLK2-R and GCLK3-L are inverted to a high logic level to start the second display period Td2. The clock GCLK2-R is applied to the second transistor T2 of the Nth stage S (N) of the right GIP circuit GIP_R in FIG. 9 to output a gate pulse from the Nth stage S (N). At the same time, the voltage is applied to the gate of the first transistor T1 of the N + 1th stage S (N + 1) to change the voltage of the Q node Q (N + 1), and as a result, the second The gate-source voltage of transistor T2 is raised to cause an unwanted output from N + 1th stage S (N + 1). Similarly, the clock GCLK3-L is applied to the second transistor T2 of the N + 1th stage S (N + 1) of the left GIP circuit GIP_L in FIG. 9 so that the N + 1st stage S is shown in FIG. 9. The gate pulse is output from (N + 1), and is applied to the gate of the first transistor T1 of the N + 2th stage S (N + 2) to be applied to the Q node Q (N + 2). ), And as a result, the gate-source voltage of the second transistor T2 is raised to cause an unwanted output from the N + 2th stage S (N + 2). Therefore, when the second display period Td2 starts, gate pulses are sequentially supplied to the 20th and 21st gate lines G20 and G21 so that data is normally addressed and the 22nd and 23rd gate lines G22, A
In order to prevent the luminance fluctuation of two lines generated when the display section is resumed, the
Referring to FIG. 12, the display periods Td1, Td2, and Td3 and the touch sensor periods Tt1, Tt2, and Tt3 are time-divided within one frame period. Assume an example in which each of the pixel blocks B 1 to B N includes pixels arranged in 19 lines. In this example, one pixel block includes nineteen gate lines. During the first display period Td1, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are normally generated in one horizontal period so that the first to nineteenth gate lines G1 to G19. Gate pulses are supplied sequentially. Subsequently, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are maintained at one logic level during the first touch sensor period Tt1. During the first touch sensor period Tt1, the right second clock GCLK2-R and the left third clock GCLK3-L are maintained at a high logic level and the other clocks GCLK1-L, GCLK2-L, and GCLK4- are maintained. L, GCLK1-R, GCLK3-R, and GCLK4-R) remain at the logic level. The right second clock GCLK2-R and the left third clock GCLK3-L are supplied to the second transistor T2 of the stages that generate an output at the same time as the first display period Td1 starts and the outputs of the stages are output. Is the timing clock.
When the second clock GCLK2-R maintains a high logic level during the first touch sensor period Tt1, the drain of the second transistor T2 of the Nth stage S (N) of the right GIP circuit GIP_R is maintained. The voltage is held at a high logic voltage so that the gate pulse is held at a high voltage. If the second clock GCLK2-R maintains the high logic level during the first touch sensor period Tt1, the Q node Q of the N + 1th stage S (N + 1) of the right GIP circuit GIP_R (N + 1)) voltage is maintained at a high logic level so that the output of the N + 1th stage S (N + 1) does not vary. When the third clock GCLK3-L maintains a high logic level during the first touch sensor period Tt1, the second transistor of the N + 1 stage S (N + 1) of the left GIP circuit GIP_L Since the drain voltage of T2 is maintained at the high logic voltage and the voltage at the Q node Q (N) is kept low, the gate pulse is maintained at the high voltage from the N + 1th stage S (N + 1). . If the third clock GCLK3-L maintains the high logic level during the first touch sensor period Tt1, the Q node Q of the N + 2th stage S (N + 2) of the left GIP circuit GIP_L (N + 2)) voltage is maintained at a high logic level so that the output of the N + 1th stage S (N + 1) does not vary.
When the second display period Td2 is resumed, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are normally generated in one horizontal period so that the 20th to 38th gate lines G20, The stages connected to 38 output sequentially gate pulses. Therefore, when only one side of the GIP circuit is viewed, the I clock supplied to the second transistor T2 of the I stage connected to the first (I is a positive integer of 2 or more) gate line at which the display period starts is high during the touch sensor period. Maintaining the logic level can prevent abnormal output of the I + 1 stage when the display section is resumed.
Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
DIS: Display panel TSP: Touch screen
12: data driving circuit 14: gate driving circuit
20: timing controller 30: touch sensing circuit
32: Tx drive unit 34: Rx sensing unit
36: algorithm execution unit 38: timing generator
Claims (5)
A gate driving circuit including a shift register in which stages are cascadedly connected; And
A timing controller configured to control the gate driving circuit by supplying a gate start pulse and a gate shift clock to the gate driving circuit;
Pixels of the pixel array of the display panel are driven in a display driving section, and the touch sensors are driven in a touch sensor section.
The timing controller,
During the touch sensor period, the voltage of the gate shift clock supplied to the pull-up transistor of the I (I is a positive integer of 2 or more) stage connected to the gate line where the display period starts after the touch sensor period is set to a high logic level. While maintaining the gate shift clock supplied to the pull-up transistors of the stages other than the I stage at a low logic level.
The timing controller,
The display device having touch sensors, wherein the gate shift clock is generated in one horizontal period period during the display period.
Driving pixels of a pixel array of the display panel in a display driving section and driving the touch sensors in a touch sensor section; And
During the touch sensor period, the voltage of the gate shift clock supplied to the pull-up transistor of the I (I is a positive integer of 2 or more) stage connected to the gate line where the display period starts after the touch sensor period is set to a high logic level. And maintaining, at a low logic level, a gate shift clock supplied to pull-up transistors of stages other than the I stage.
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KR101963389B1 (en) * | 2012-07-25 | 2019-03-28 | 엘지디스플레이 주식회사 | Display Device Having Embedded Gate Driver And Driving Method Thereof |
KR101572378B1 (en) | 2014-08-04 | 2015-11-27 | 엘지디스플레이 주식회사 | Display device having touch sensors |
KR102235497B1 (en) * | 2014-10-20 | 2021-04-05 | 엘지디스플레이 주식회사 | Display device |
KR102293151B1 (en) * | 2014-12-01 | 2021-08-23 | 엘지디스플레이 주식회사 | Touch display device |
KR102259565B1 (en) * | 2014-12-24 | 2021-06-04 | 엘지디스플레이 주식회사 | Display Device Having a Touch Sensor and Driving Method thereof |
KR102298488B1 (en) * | 2014-12-30 | 2021-09-08 | 엘지디스플레이 주식회사 | Display device having touch sensors and gate driving circuit thereof |
KR102390982B1 (en) * | 2015-01-30 | 2022-04-28 | 엘지디스플레이 주식회사 | Display device, and driving device and method thereof |
KR102357769B1 (en) * | 2015-10-27 | 2022-02-03 | 엘지디스플레이 주식회사 | Display with touch screen and driving circuit |
KR102456790B1 (en) * | 2015-10-30 | 2022-10-21 | 엘지디스플레이 주식회사 | Gate driver, display panel and display device |
KR102539856B1 (en) | 2016-07-28 | 2023-06-08 | 엘지디스플레이 주식회사 | Display and gate driving circuit thereof |
CN111403437B (en) * | 2020-03-16 | 2023-04-11 | 京东方科技集团股份有限公司 | Flexible substrate and display device |
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KR101503103B1 (en) * | 2011-03-25 | 2015-03-17 | 엘지디스플레이 주식회사 | Touch sensor integrated type display and driving method therefrom |
KR101778731B1 (en) * | 2011-04-01 | 2017-09-27 | 엘지디스플레이 주식회사 | Display having touch sensor and driving method thereof |
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JP2007139817A (en) | 2005-11-14 | 2007-06-07 | Sharp Corp | Display apparatus with touch panel, and apparatus and method for driving display apparatus |
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