KR101999210B1 - method of testing 3D type multi layer semiconductor device in the process of stacking chip - Google Patents

Abstract

After the stacking process step of performing the upper chip stacking process on the lower chip in the process of manufacturing the three-dimensional stacked semiconductor device, a pattern inspection device having an auto-focus function with the upper chip stacked, Detecting a change in height position of the upper chip surface by performing optical inspection while relatively moving the position on the upper chip position and determining a chip stacking failure at the upper chip position based on the detected result, An interim inspection method for a semiconductor device chip stacking process is disclosed.
According to the method of the present invention, in the step of forming a three-dimensional laminated semiconductor device, a portion of a defective chip, which may cause a defective vertical connection, is identified through optical inspection of a portion exposed to the outside while stacking chips, It is possible to reduce the process burden and the cost, and to reduce the defective ratio of the completed three-dimensional stacked semiconductor device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of testing a multi-layer semiconductor device,

The present invention relates to an inspection method in an intermediate stage of a semiconductor device, and more particularly, to an intermediate inspection method for a chip stacking process for fabricating a three-dimensional stacked semiconductor device.

The three-dimensional stacked semiconductor device is a semiconductor device which is formed by stacking chips vertically and connecting them in a circuit, and can be said to be a type of semiconductor device in the form of a multi-chip package (MCP). In such a three-dimensional stacked semiconductor device, the upper and lower chips are connected to each other through a silicon via electrode (TSV: Through Silicon Via: 3) as shown in FIG. 1 formed on each chip 1, . At the upper and lower ends of the silicon penetrating electrode, there are solder layers 5 and 7 for circuit connection between the upper and lower chips.

In order to form such a three-dimensional stacked semiconductor device, a chip must first be formed through wafer processing. In a state in which chips are formed, the lower chip and the upper chip are placed so as to overlap each other, It is necessary that the upper chip circuit part and the lower chip circuit part are combined with each other to form an integrated circuit as a whole.

This is because many chips are required to be overlapped and electrically coupled in order to increase the circuit formation efficiency of the semiconductor device. In such a semiconductor device configuration, in order for a completed semiconductor device to perform its full function, a chip constituting each layer must be completely formed, and any pair of upper and lower pairs of chips must be vertically coupled The electrode terminals of the upper chip and the electrode terminals of the corresponding lower chip must be well aligned and electrically connected well.

In any of the upper and lower chip pairs, horizontal misalignment or tilting of the chip plane occurs due to errors in electrode alignment or thickness of the solder or the like as shown in Figs. 2 and 3, so that electrical connection can not be normally performed. The entire semiconductor device stacked up and down becomes defective and can not be used. Therefore, it is important that the individual chips are formed well, but in the three-dimensional stacked semiconductor device, it is required that the electrical coupling between all the chip pairs including the upper layer and the lower layer is accurately performed.

However, in order to determine whether the coupling between the chip pairs is correctly performed, it is desirable to confirm that the function is performed by applying electricity to the terminal. However, in the middle of the process of manufacturing the semiconductor device, There is a problem that electrical inspection such as checking the performance is not usually possible.

Particularly, if there is a problem between the lower layers in the process of stacking the chips one by one, the process may become meaningless after the chips are stacked up and electrical connection is made, which may be waste of the chips used in the subsequent process.

Therefore, in the step of forming such a three-dimensional laminated semiconductor device, if it is possible to carry out the inspection for confirming the defective factor which is externally revealed at every step of connecting the upper and lower chips while stacking the chips, or at least one of the steps, It is highly desirable to reduce the defective rate of the completed three-dimensional stacked semiconductor device and to reduce the burden on the process and reduce the cost because no further process is performed on the chip already confirmed as defective in the inspection process.

On the other hand, in a semiconductor device pattern inspection apparatus, a pattern inspection is performed while an object for inspection is precisely focused to obtain an accurate pattern image.

This focus must be done automatically as well as automatically. Most of the inspection equipments are equipped with a calculation algorithm and a processor based on basic algorithms such as Fourier transform to realize fast autofocus function. By analyzing the image formed on the image pickup device and finding the accurate focal distance, it obtains an accurate focus pattern image while changing the distance between the optical element such as the objective lens and the object to be inspected and the arrangement between the optical elements according to the focal distance. And the semiconductor device test is continued based thereon.

The autofocus is an active mode in which the equipment sends an ultrasound or a light beam to the subject to sense the distance and reflects the object, a manual mode in which the light is reflected naturally from the object, and a dual mode The TTL method using the light coming through the objective lens or the camera lens of the inspection equipment used for photographing is often used. In the contrast detection method, which is one of the manual methods and used frequently in video cameras and compact digital cameras, the contrast of the main part of the image is continuously calculated while moving the lens and it is determined that the focus is achieved when the contrast becomes maximum do. In the phase difference detection method, which is often used in DSLR cameras, the light coming through the lens is divided and compared to judge whether or not the light is focused.

By using such an autofocus function, it is possible to obtain a precise focus image while overcoming a deviation of a wafer from a focal plane of several nanometers to several tens of nanometers.

For example, the pattern image is acquired while changing the position of the table in the plane on which the wafer is placed, and also the height change of the wafer surface due to the planar position change is sensed. Thus, the table is moved in the wafer thickness direction or the height direction, Is placed at a position spaced from the focal plane position or intentionally by a certain distance from the focal plane, and a pattern image at the plane position is obtained.

According to one example of the semiconductor pattern inspection equipment for performing auto-focus, there is provided an image pickup device for pattern image to obtain a pattern image and an image pickup device for auto-focus for auto-focus. Of course, according to another example, one imaging element may serve as both a pattern image and an auto focus in accordance with the automatic focusing method, but here, the imaging element has a separate imaging element.

Then, while changing the position on the plane of the wafer with respect to the image optical system, the focus plane position is continuously determined through the auto-focus imaging device, and when the wafer surface is out of focus, the position of the wafer table is continuously adjusted A pattern image is obtained with the image pickup device for pattern image with respect to the position on the plane, and it is confirmed whether the pattern image is a normal pattern.

In order to perform this action quickly and continuously, the signals of the autofocus imaging device are input to a computer device and the image processing program for image analysis is used to determine how far the wafer surface in the current plane position is spaced from the focal plane of the imaging optical system The computer device gives a signal to the table to automatically calculate and move the table in the height direction by this distance.

Of course, the auto focus method of the pattern inspection apparatus for manufacturing a semiconductor device can be various, and the auto focus method follows the movement of the wafer table corresponding to the focal distance in any way.

An apparatus for capturing an image electronically, an apparatus for estimating a focal distance from a camera to an object, a method for automatically estimating a camera-object focus depth, and a computer-readable medium Korean Patent No. 10-1640914: focus position adjustment method and inspection method Korean Patent Registration No. 10-1113602: Wafer defect detection system

An object of the present invention is to alleviate the problems in manufacturing the above-described three-dimensional stacked type semiconductor device, in which an upper chip is placed on a lower chip and an electrical terminal having a lower TSV exposed on the back surface of the upper chip is connected to a corresponding terminal And then checking whether or not the connection between the upper chip and the lower chip is well performed after connecting the semiconductor chip to the lower chip.

The present invention relates to a three-dimensional stacked semiconductor device chip stacking process in which an upper chip is placed on a lower chip, a physical connection is made to allow electricity to pass therethrough, and an efficient check of connection between the upper chip and the lower chip The present invention also provides a method for inspecting a semiconductor device.

In the process for forming a three-dimensional stacked semiconductor device according to the present invention, at least one of the steps of stacking chips and connecting upper and lower chips is carried out, and it is possible to reduce burden and cost in the manufacturing process, And an object of the present invention is to provide an inspection method for a three-dimensional stacked semiconductor device chip stacking process capable of reducing the defective rate of a three-dimensional stacked semiconductor device to be fabricated.

According to an aspect of the present invention, there is provided an intermediate stage inspection method for a three-dimensional stacked semiconductor device chip stacking process,

After the lamination process step of performing the upper chip laminating process on the lower chip in the process of manufacturing the three-dimensional laminated semiconductor device,

(Z direction) of the upper chip surface by performing optical inspection while relatively moving the position on the plane (xy plane) between the inspection optical system and the object by using the inspection equipment having the auto focus function while the upper chip is stacked, Detecting a position change and determining a chip stacking failure at the upper chip position based on the detected result.

In the present invention, the lowermost chip among the stacked chips may be a chip in a wafer state before sowing. In this case, the normal level of the upper chip surface is calculated based on the thickness of each element part of the lower chip and the upper chip with respect to the entire wafer, and a normal level of the upper chip surface is calculated, It is possible to perform processing for judging the upper chip as a lamination failure.

In the present invention, the inspection may be performed on the upper chip unit, or may be performed on a part of the upper chip.

In the present invention, the inspection based on the upper chip may be based on the position of one part of the upper chip surface, and the upper chip surface in the inspection part may be within a certain range from the reference. At this time, the portion to be inspected may be all the parts to be inspected for the pattern inspection in the normal pattern inspection apparatus, and may be limited to a few limited portions distributed on the upper chip for quick inspection, for example, It may be nine parts, including four parts, the center, and the center of each side.

In the present invention, it is possible to find a case where two inspection target portions on the upper chip plane within a certain distance or more are inclined at a certain height difference or more than a certain height, It can be judged.

In the present invention, the auto focus function of the inspection equipment may be a method of determining the surface of the portion with the largest luminance in the sensed image of the image sensing device as the focus plane.

In the present invention, a method of judging whether or not the upper chip is parallel moving (planar direction movement) or rotational movement in the plane on the plane is detected together with the positional change in the thickness direction of the upper chip surface, .

According to the method of the present invention, in the step of forming a three-dimensional laminated semiconductor device, a defective chip portion can be identified through an optical appearance inspection of a portion exposed to the outside every time the upper and lower chips are connected while stacking the chips.

Therefore, according to the present invention, it is possible to reduce the process burden and cost by preventing the process step from continuing in the defective chip portion, and to reduce the defective rate of the completed three-dimensional stacked semiconductor device.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a side sectional view showing an example of an installation form of a silicon penetration electrode (TSV) used for electrical connection between a lower chip and an upper chip in a semiconductor device,
FIG. 2 is a conceptual side sectional view showing a state in which the upper chip surface is entirely separated from the normal focal plane by a certain height due to the mismatch between the electric terminals in a state where the upper chips are stacked on the lower chip;
FIG. 3 is a conceptual side view showing a state in which an upper chip stacked on a lower chip is not placed in a correct position as shown in FIG. 2 and mismatching occurs between an electrical terminal of the lower chip and an electrical terminal of the upper chip, Sectional view.
4 is a side cross-sectional view showing important steps of a process of bonding an upper chip on a lower chip,
5 is a structural conceptual diagram showing an embodiment of a pattern inspection apparatus having an autofocus function that can be used in the present invention.
6 is a diagram showing an example of a line-spacing target image obtained from an auto-focus imaging device,
FIG. 7 is a graph showing the sharpness according to the pixel position as it progresses laterally at one end of the imaging element,
8 is a conceptual diagram showing a state in which a level of an upper chip surface is inspected while a top chip is stacked on a lower chip position of the wafer using a pattern inspection apparatus having an auto focus function,
FIG. 9 is a conceptual diagram for explaining a concept in which inspection is performed in another auto focus type inspection equipment;
Fig. 10 is a graph showing the intensity value according to the pixel position of the imaging element,
FIG. 11 is a conceptual diagram showing an example of a type in which an error occurs in which the focus position is out of the normal range, and the conceptual configuration of another inspection equipment for the level inspection of the present invention is simplified.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

4 is a side cross-sectional view illustrating a detailed step of laminating an upper chip on a lower chip according to an embodiment of the method of the present invention.

4 (a), a lower chip is formed on the wafer 10 through a semiconductor device manufacturing process. Although the lower chip is not clearly shown, a plurality of lower chips are formed on the wafer 10 together and are prepared with the lower chip not yet divided by sawing.

Here, the lower chip may be a controller die of a high bandwidth memory (HBM), and the upper chip may be a DRAM chip stacked on a wafer including a lower chip.

The electric terminals 11 are exposed on the surface of the lower chip for each position for electrical connection with the TSV of the upper chip to be stacked thereon. In this state, the upper chip 20 corresponding to the lower chip of the wafer 10 is placed as shown in FIG. 4 (b) to form a layered structure. The upper chip 20 laminated on the lower chip can be formed on the wafer together with the lower chip by the semiconductor device manufacturing process.

However, unlike the lower chip, the upper chip 20 is a chip in which the entire thickness is reduced through the backside CMP in a state in which the upper chip circuit is formed on the wafer, and then separated into individual chips through sawing. When the backside CMP is used for the wafer, the upper chip may be formed by thinly polishing the wafer to a thickness of about 50 micrometers. In the soaking process, chips are cut along the scribe line of the wafer to separate chips formed in the entire wafer area.

At this time, the upper chip 20 has a plurality of TSVs 21 installed in the chip inside area. As shown in FIG. 1, the upper end 211 and the lower end 213 of the TSV 21 are provided with a plurality of upper chips (not shown) to be stacked on the upper part of the chip and a lower chip A solder metal layer having a low melting point is provided so as to be advantageous in a surface mounting type fusion welding process.

Even if only one of a large number of terminals to be connected to each other between the upper chip 20 and the lower chip is not connected, a functional problem arises in the three-dimensional stacked semiconductor device to be formed including these chips, It is needless to say that accurate positioning of the lower chip and precise mechanical movement of the robot for transporting the upper chip 20 are necessary.

Referring to FIG. 4C, the upper chip 20 is placed on the lower chip through the entirety of the lower wafer 10 through the entire surface of the lower chip 10, The solder layer of the lower end 213 of the TSV 21 of the upper chip 20 which is in contact with the upper chip 20 is melted and changed into a fused portion 213 ' Electrical connection is made.

In order to confirm whether there is a defect in the connection between the lower chip of the wafer subjected to the physical stacking and electrical connection and the upper chip placed thereon, the present invention is characterized in that the optical inspection of the entire wafer with the upper chip connected Conduct.

Referring to FIG. 5, an example of a pattern inspection apparatus having an autofocus function which can be used in the present invention is shown. Although the light source is not explicitly shown, incident illumination light 200 consists of green and UV, which are the second and third harmonics of the Nd: YAG laser, respectively. The illumination light is incident on the wafer 100 through the illumination beam splitter 202 and the objective lens 201. The light reflected from the wafer passes through the objective lens 203 and is divided into two components by the dichroic filter 204. The UV light is reflected and forms an image on the imaging device 205 for pattern inspection, which is an image used in wafer pattern inspection. The green light is transmitted through the dichroic mirror 204 and forms an image on the autofocus imaging element 206, which is the image used in the autofocus process.

The autofocus imaging element 206 tilts at an angle? To the optical axis 207, so that only a portion of the image may be in the correct focus position. When the image in the pattern inspection imaging device 205 is focused, a part of the focused image in the auto focus imaging device 206 is aligned in the center of the imaging device. This is the starting position where the basic focus adjustment between the optical system and the object to be inspected is made.

Although the use of two wavelengths as the light source is illustrated above, the use of different wavelengths for the imaging and autofocus functions can be used to reduce the contrast and brightness obtained in the dark field mode used for surface defect detection Is less suitable for use in autofocus applications because it is lower than that obtained in bright field mode and in a preferred embodiment the autofocus function operates at one wavelength in light field illumination mode .

When the surface to be inspected moves by the vertical distance z with respect to the objective lens 201, the position of the correction focal point in the autofocus imaging element 206 is given by z '= z * m, From the original focus position along the optical axis 207, where m is the optical magnification of the side of the pair of lenses 201 and 203. Because of the angle with the optical axis of the autofocus imaging element 206, the prefocused image on the imaging element 206 is no longer in the center of the detector, but the lateral distance from the center is z '/ sin? Is an inclination angle formed by an axis perpendicular to the detector 206 with respect to the optical axis 207. [

Once the clearest part of the image is determined, the lateral distance can be measured as the value of the pixel, z ', i.e., the calculated z value. The motor 208 connected to the wafer chuck is driven by a closed loop control system or computer device 209 such that the wafer moves vertically by a distance z to adjust the focus to its correction position.

The exact focal position adjustment of the image is determined by the image processing algorithm, which occurs each time an image is formed on the imaging element 206. Preferably, the algorithm operates to extract the position of the edge in the image by use of an edge detector such as Sobel. Then, for each line of the detector, the maximum edge sharpness value is selected. This is averaged over several edges to facilitate measurement, and a graph of edge values is shown as a function of position. The maximum value of the graph represents the sharpest part of the image and the area with a certain contrast.

This process can be described with reference to Figs. 6 and 7. Fig. 6 is a view of an image of a line-spacing target obtained from an auto-focus imaging device. As obtained in the image, the left and right extreme portions of the image appear blurred, and only the center of the image is focused.

Here, a predetermined number of pixels are bundled in the horizontal (x) axis direction to form a stripe in the vertical (y) axis direction. In the case where the surface of the upper chip is uniformly and evenly arranged and the focal plane is at the same level, a plurality of stripes in the image deviate from the focus in the + direction toward the left and toward the right in the image, The rate of change is also constant.

The edge sharpness analysis of such an image can be represented by a focus curve as shown in Fig. 7, where the horizontal axis represents the number of lateral pixels on the detector and the vertical axis represents the sharpness of the measured image per pixel. The peak of the curve is determined by a polynomial optimal algorithm, as shown by the line through the individual measurement points around the peak of the curve.

In the sample curve shown in FIG. 7, the best focused position of the imaging element pixel (pixel) array occurs around 1100th pixel. At the pixel, the distance between the best-focused pixel location and the nominally-calibrated pixel location, as set through the calibration process, is translated by the control system (a computer device including hardware and software) to the required focal distance travel of the wafer.

For reference, when this image pickup element is desirable to monitor the output of the light source, a change in the average output level of the light source may be used to compensate the imaging system. For example, when the type of measuring the average power (output) or pulse energy output from the light source is selected and the output of the light source falls in this measurement, the digital image processing circuit operates so that the wafer image to be inspected is kept sharp , An adjustment can be made to the gray-scale level of the digital image processing circuit.

FIG. 8 is a schematic block diagram showing a basic configuration concept of an example of a semiconductor device pattern inspection equipment for carrying out the present invention.

The overall configuration of the apparatus is similar to that of FIG. 5, but here, the reflection and scattered light from the wafer portion is input to the optical sensor and is sensed to form a white field-like viewing mode as a whole, A splitter is used instead of a dichroic filter.

The wafer 10 in which a plurality of lower chips are formed and not separated from each other is placed on the inspection table 40 of the inspection equipment and an objective lens 61, An optical system including optical elements such as splitters 63 and 69, a reflector 65 and a focusing lens 67 and an optical sensor including an image pickup device 71 for pattern inspection and an image pickup device 73 for auto focus are provided . Thus, the image for the portion of the wafer 10 is transmitted to these imaging elements through the optical system. The pattern inspection imaging device 71 has a plane perpendicular to the optical axis, and the autofocus imaging device 73 is provided so as to be inclined with respect to the optical axis.

Light 50 is typically required for optical sensing and light originating from reflected or scattered light from the wafer 10 reaches the autofocus imaging device and pattern inspection imaging devices 71 and 73 through the optical system And these imaging elements transmit optical or visual information about the portion of the wafer 10 to the computer device 80 of the equipment connected to these imaging elements. The computer device 80 has a processor, a storage device, and a self-display device, such as a typical computer, and stores information received from the image pickup devices 71 and 73 in a predetermined calculation And the resultant screen can be displayed on its own display device screen.

According to a typical pattern inspection process, the optical system moves the inspection table 40 on which the wafer is placed in order in the x-axis direction and the y-axis direction on the plane in a fixed state, So that it can acquire all of the images of FIG. At this time, the individual unit images obtained through the image pickup device and transmitted to the computer device are obtained at predetermined time intervals or at regular intervals. Through the time intervals, the inspection target moves the next image pickup target area of the wafer to a position immediately below the objective lens, So that an image of the area is displayed on the image pickup device. The illumination may be continuous, but it may be in the form of a pulse only if the area to be imaged of the wafer is in the immediate lower position.

However, the image formed on the imaging device through the optical system includes not only the area to be inspected but also the peripheral area as well as the area to be inspected at the position. In the automatic focusing device, the image in the peripheral area is transmitted to the computer device, The computer device determines that the next inspection target area deviates from the focal plane so that if the next imaging target area deviates from the focal plane, While the inspection table is moved in the z-axis direction so that the next imaging target area is located at a position that is in the focal plane or does not deviate from a certain range of deviation in the focal plane.

However, in the present embodiment, the inspection of the pattern of the upper chip is already performed in the step of forming the upper chip, and the image data formed on the pattern inspection imaging device is not transferred to the computer device, The focus plane of the next imaging object region is moved in the z direction with respect to the reference focal plane or in any direction in comparison with the focal plane of the immediately preceding imaging object region, And then repeats this process for the next imaging area.

Therefore, compared to the general pattern inspection, it is possible to speed up the inspection process by reducing the calculation burden and the z-axis movement burden. The above embodiment refers to the case where the wafer chuck does not move in the z axis, but the level of the upper chip surface can be cumulatively calculated while moving along the z axis.

As shown in FIG. 9, when d (z), which is a positional change in the vertical direction of the focal plane relative to d (xy) in the planar direction of the inspection table, is above a certain range, the upper chip at the position is stacked on the wafer It is determined that there is a stacking failure, and the wafer is moved to the position of the next chip and the same inspection is repeated. In this way, the determination of the upper chips of the entire wafer is made.

10 is an example of a graph showing a change in the contrast measure according to the pixel position of the auto-focus imaging device, similar to FIG. In this case, the position at which the luminance value becomes maximum or maximum deviates considerably from the center, and substantially represents the separation distance between the surface of the area to be imaged and the plane that is in focus. Using this graph, do.

On the other hand, in the configuration shown in Fig. 8, the lower chip among the chips stacked is a chip in the wafer state before the sowing is performed, and one upper chip is stacked thereon. In this case, the relationship between the upper chip and the lower chip can be newly set for each of the chips, and when the chips are stacked, Can be determined.

When inspecting the stacking fault in each step, the actual level (height position) of one upper chip can be measured and set as a reference level, and the thickness and solder amount of the lower chip and upper chip, , The normal level of the upper chip surface is calculated, and it is determined that the upper level chip has a portion deviated by more than a micrometer unit from the reference level while determining it as the reference level.

In general, the change in the height of the inner surface of the chip due to the pattern characteristics and the pattern density in the upper chip is often in the order of tens of nanometers, and the overall level is also in a range not greatly different. However, The overall inclination and the level deviation of the upper chip when the lamination failure occurs due to defective or bad terminal patterns are remarkable in the unit of micrometers and it is very effective to judge the lamination failure of the upper chip through the level inspection as in the present invention .

In the present invention, the level inspection may be performed on the upper chip unit, or may be performed on a part of the upper chip. The inspection based on the upper chip may be based on the position of one part of the upper chip surface and the upper chip surface in the inspection part may be within a certain range from the reference. At this time, the certain range may be set to any range determined to be suitable for the bad judgment.

The portion to be inspected may be all the target portions to be inspected for pattern inspection in a normal pattern inspection apparatus, and may be divided into several limited portions distributed on the upper chip for quick inspection, for example, four corners Part, or nine parts including four corners, the center, and the center position of each side. In this case, it is not necessary for the pattern inspection apparatus to continue the imaging shot continuously for the pattern inspection, and only the level measurement for the predetermined position of each upper chip is performed under the assumption that the position of the entire upper chip is already recognized the inclination or level in the x direction, the y direction, or the diagonal direction may be checked by a computer device in accordance with a program and a determination may be made.

In the present invention, it is possible to find a case where two inspection target portions on the upper chip plane within a certain distance or more are inclined at a certain height difference or more than a certain height, It can be judged.

In the present invention, whether or not the upper chip is parallel moved (moved in the plane direction) or rotated in a plane on the upper surface of the upper chip together with the level inspection is detected along with the positional change in the thickness direction of the upper chip surface, As shown in FIG. Various methods can of course be used to determine the position of the upper chip. For example, by using an image pickup device for pattern inspection, the image can be judged as an image. By utilizing the fact that the level difference between the wafer surface with the lower chip and the upper chip surface is dramatically generated, It is also possible to grasp the edges.

More specifically, it is difficult to simultaneously grasp the lower chip area (or contour) and the upper chip area (or contour) in the inspection equipment because the lower chip and upper chip have different depths in different planes. Embodiments are also conceivable.

In this embodiment, an optical image is acquired while scanning the entire wafer area using an inspection equipment. Through the imaging of the entire area of the wafer, the lower chip area within the wafer can be grasped and the equipment computer can perform image processing through the processor and the adapted program so that the lower chip area or position can be recorded as information or stored as an image.

Then, the upper chip area is picked up while moving the entire area of the wafer with the inspection system in a state in which the upper chips are stacked, and the upper chip area can be grasped by using the equipment computer to record information or image form.

Next, by using these pieces of information or images together, an alignment state between the lower chip and the upper chip stacked thereon is represented through information linkage or image combining, and rotation movement angle and parallel movement distance are detected through image processing, The rotational movement angle and the parallel movement distance may be calculated through direct calculation processing of information.

At this time, the position on the wafer can be determined by using a common reference point such as the center point of the wafer and the flat zone, and the matching operation can be performed using the contour line or position data based on the common reference.

When a wafer process for forming a semiconductor device is performed, a method for grasping the alignment of the structure on the wafer and the structure formed in the subsequent process may be various methods such as using an overlay pattern. The method of confirming the alignment between the lower chips may also use various methods for confirming the alignment of the structures on the wafers before and after the known process, so that the embodiments are not limited to the above-described specific methods.

11 is a conceptual diagram of level inspection schematically showing an example of another equipment configuration for implementing the inspection method of the present invention.

Here, the upper chip 20 of the portion of the wafer 10 to be inspected is illuminated using a narrow-band, straight-line light source, for example, a light beam emitted from the laser 90, and the reflected light is arranged as pixels of a plurality of unit- The position of the unit optical element in the region of the detector (optical sensor) 95 that is detected most strongly is detected and the sensitivity is grasped. In this case, the laser may be a spot laser whose shape is a point of laser light that is formed on the object, or a line laser whose shape is a laser light that is formed on the object. In this case, You can check whether the surface is in the normal level range.

In the inspection equipment, when the upper chip 20 is properly stacked and connected to the lower chip formed on the wafer 10, a lens optical system constituting the optical system is set so that the upper chip surface is in the focal plane of the optical system of the inspection equipment .

As a result, whether the upper chip of the wafer portion is correctly placed on the focal plane or moved up and down in the focal plane, whether the reflected light from the focal plane and the focal plane lies at a position deviating from the reference position O of the detector, It is possible to ascertain the level (level) of the upper chip placed on the wafer and determine whether the chip is out of the normal level.

The apparatus for inspecting the focal distance in the inspection equipment includes a laser (laser generator) 90 and an upper chip 20 as illumination for irradiating the surface of the upper chip 20 laminated on the lower chip portion of the wafer 10, And a detector 95 in which a plurality of unit light receiving elements for detecting light reflected from the surface are arranged on the pixels.

As shown in FIG. 11A, the laser light is irradiated with the laser light by being inclined at a certain angle with the waterline of the plane of the upper chip 20, and the detector 95 is also installed in a state of being inclined at a certain angle from the horizontal. When the unit light receiving element at the middle (reference position: O) of the detector 95 detects reflected light of the maximum light intensity, the upper chip portion is spaced at a uniform distance from the lower chip plane and is at a normal level, It will be at the focus surface in the equipment setting.

As shown in FIG. 11B, when the surface of the upper chip moves parallel to the lower chip plane by a distance D, the reflected light of the laser is deviated from the reference position O of the detector to illuminate the R point. If the distance S out of the original position is greater than the predetermined separation distance in consideration of the functional defect, the upper chip on which the laser is currently illuminated is marked as defective and the wafer is prevented from further processing in this position.

The parallel movement as shown in FIG. 11B can be illustrated through the same drawing as FIG. The lower terminal of the silicon penetration electrode 121 of the upper chip 120 to be placed on the upper terminal of the silicon penetration electrode 111 of the lower chip 110 is not positioned in the correct position and the upper chip is moved horizontally . As a result, the bottom chip of the silicon chip penetrating electrode of the upper chip is parallel moved from the normal level downward by the distance D protruding from the upper chip bottom surface, and the distance between the lower chip surface and the upper chip surface is larger than the normal position The reflected light is converged at the R position lower than the reference position O of the detector 95 by the tilted laser light and the inclined detector arrangement as shown in FIG.

11 (c), when the surface of the upper chip is inclined at a certain angle (?) From the lower chip plane, the reflected light of the laser 90 is deviated by twice a certain angle from the original reflected light direction, It is reflected off the position (O) to the point R '. When the distance from the original position or the size of the rotation angle is larger than a predetermined distance or size in consideration of the malfunction, the upper chip 20 currently illuminated by the laser 90 displays a defect and the position of the wafer 10 So that the subsequent process is no longer carried out.

The inclined arrangement as shown in FIG. 11C can be illustrated through the same drawing as FIG. The lower terminal of the silicon penetration electrode 121 of the upper chip 120 to be placed on the upper terminal of the silicon penetration electrode 111 of the lower chip 110 is not placed in the correct position. As a result, the upper chip Are stacked at an angle to the chip (lower chip surface).

As a result, as shown in FIG. 11C, the reflected light from the inclined upper surface of the chip together with the tilted laser light and the tilted detector is formed at the position R 'lower than the reference position O of the detector 95 .

In the above description, the upper chip and the lower chip which are directly connected to each other are inspected for each lamination at each step. However, the lower chip is not separated from the wafer, and the upper chip is an upper chip It is also possible to carry out alignment inspection and level inspection on the basis of the present invention.

Although the semiconductor device pattern inspecting apparatus has been described above, it is not necessarily limited to the pattern inspecting apparatus. If the inspecting apparatus is a semiconductor device inspecting apparatus having an auto focus function, the method of the present invention can be implemented, .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. .

Claims (5)

After the lamination process step of performing the upper chip laminating process on the lower chip in the process of manufacturing the three-dimensional laminated semiconductor device,
Optical inspection is performed while the position on the plane (xy plane) between the inspection optical system and the object is relatively moved by using the inspection equipment having the auto focus function in a state in which the upper chip is stacked, ) Position,
And determining a chip stacking failure at the corresponding upper chip position based on the detected result. The method according to claim 1,
The lower chip is a chip in a wafer state before sowing is performed,
(Z-direction) positional change of the surface of the upper chip by using the inspection equipment having the auto-focus function, the thickness of the upper chip surface and the upper chip surface Wherein the reference level is determined by calculating a normal level. The method according to claim 1,
The process of determining the chip stacking fault
(X, y) direction and a diagonal direction on the xy plane of the upper chip in a state in which the height level of each part of the upper chip is obtained by detecting a change in position in the height direction And the stacking failure of the upper chip is judged when the level change between the portions at a certain distance is equal to or larger than a predetermined size, that is, when the slope is a certain degree or more. . The method according to claim 1,
Wherein the automatic focus function of the inspection equipment having the auto focus function is performed by a method of determining that the surface of the portion with the largest luminance in the image picked up by the image pickup device is a plane in which the focused image is focused. Intermediate step test method. The method according to claim 1,
Wherein the upper chip-stacking failure is judged in a comprehensive manner by detecting whether the parallel movement or the rotational movement of the upper chip on the xy plane is performed at a predetermined position together with the change in position in the thickness direction of the upper chip surface. Intermediate inspection method for semiconductor device chip stacking process.

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