KR101980964B1 - Physically uncloable function device based on counter and method for acquiring challenge-response thereof - Google Patents

Abstract

A counter-based physical copy protection function device capable of efficiently improving the reliability of a delay-based PUF is provided. The PUF apparatus includes a multiplexer array configured by connecting one or more multiplexers, wherein the multiplexer includes at least two input terminals and at least two output terminals corresponding to at least two delay paths, and a challenge input terminal; A feedback loop connecting each of the final output terminals of the multiplexer array to the initial input terminals of the multiplexer array and a plurality of counters connected to the most significant bits of the two or more counters, And an arbiter for outputting different responses according to the arrival sequence of the signals corresponding to the delay paths. Therefore, the area and power consumption required for the conventional reliable PUF configuration can be greatly reduced.

Description

TECHNICAL FIELD [0001] The present invention relates to a counter-based physical copy prevention function device and a challenge-response acquisition method using the same.

The present invention relates to a physical unclonable function (PUF), and more particularly, to an apparatus and method for improving the reliability of a delay-based PUF.

A physical unclonable function (hereinafter referred to as " PUF ") function, which is used for security purposes, for example, in device authentication or secret key generation, ) Has emerged. PUF is a type of function that is implemented on the hardware, which is called a challenge and an output is called a response. In order to use the PUF for security purposes, several conditions must be met. One of the indicators that can evaluate the operational stability of the PUF is reliability. Reliability can be a measure of whether a response is consistent when the same challenge is repeatedly entered.

In this regard, since the PUF utilizes the analog characteristics of the hardware, if the ambient environment such as temperature or supply voltage changes, a different response may be output even if the same challenge is input. However, in order to use the PUF for security purposes, the same response should always be output when the same challenge is entered. It is important to improve the reliability of the PUF. In order to solve this problem in the past, a method has been proposed that includes an additional circuit (post processing logic) for correcting the change due to the surrounding environment in addition to the PUF circuit. However, this method is inefficient because it occupies a large area and consumes a lot of power compared to the PUF circuit.

Korean Patent Registration No. 10-1408619 (" Capacity Displacement Based Physical Copy Protection System ", Chungbuk National University Industry & University Collaboration Foundation)

SUMMARY OF THE INVENTION An object of the present invention is to provide a counter-based physical copy prevention function device capable of effectively improving the reliability of a delay-based PUF while occupying a small area.

Another object of the present invention is to provide a challenge-response acquisition method using a physical copy protection function that can efficiently improve the reliability of a delay-based PUF while occupying a small area.

It should be understood, however, that the present invention is not limited to the above-described embodiments, but may be variously modified without departing from the spirit and scope of the invention.

According to an aspect of the present invention, there is provided a counter based PUF (Physically Unclonable Function) device, comprising: at least one multiplexer, wherein the multiplexer includes at least two input terminals corresponding to at least two delay paths, A multiplexer array formed by connecting two or more output terminals and a challenge input terminal; Two or more counters respectively connected to the final output terminals of the multiplexer array; A feedback loop connecting the final output terminals of the multiplexer array to the first input terminals of the multiplexer array, respectively; And an arbiter connected to each of the most significant bits of the two or more counters and outputting a different response depending on a destination of a signal corresponding to each of the two or more delay paths.

According to an aspect of the invention, the feedback loop includes a connection relationship between the final output terminals of the multiplexer array and the initial input terminals of the multiplexer array such that the two or more delay paths can be repeated evenly after the feedback loop And may include a feedback multiplexer to adjust.

According to an aspect, the feedback multiplexer may change the input-output correspondence of the feedback multiplexer in response to a determination that a first input terminal to a final output terminal correspondence of the multiplexer array with respect to a challenge input is changed.

According to an aspect, the feedback multiplexer may maintain the input-output correspondence of the feedback multiplexer in response to determining that the initial input terminal to final output terminal correspondence of the multiplexer array with respect to the challenge input is maintained.

According to an aspect, the feedback loop may further include an inverter for each of the at least two delay paths to increase the value of the counter in response to the iteration of the loop along the feedback loop.

According to an aspect, the counter may be comprised of a register.

According to an aspect, the arbiter may be configured as a flip-flop.

According to an aspect of the present invention, the apparatus may further include an operation unit for calculating a difference between values of the counter at a time when any one of the most significant bits of the two or more counters becomes one.

According to one aspect, when the difference between the values of the counter according to the first challenge input is less than a predetermined threshold, the response in response to the first challenge input and the first challenge input is no longer used as a challenge- .

According to one aspect, the counter based PUF device includes a challenge memory for storing the first challenge input in a stable challenge list if the difference between the values of the counter according to the first challenge input is greater than a predetermined threshold value .

According to an aspect, the counter based PUF device is connected to a server, and the operation unit and the challenge memory may be included in the server.

According to another aspect of the present invention, there is provided a challenge-response acquisition method using a counter based PUF (Physically Unclonable Function) for solving the above-mentioned problems. The challenge-response acquisition method includes: at least one multiplexer, Receiving input signals at initial input terminals of a multiplexer array constructed by connecting at least two input terminals, at least two output terminals, and a challenge input terminal, and responding to the challenge input at each of the challenge input terminals The method comprising: receiving a signal; Receiving signals from the final output terminals at two or more counters connected to the final output terminals of the multiplexer array and outputting signals of the final output terminals of the multiplexer array to the first input terminals of the multiplexer array via a feedback loop, Receiving; And outputting a different response according to an arrival sequence of a signal corresponding to each of the two or more delay paths, in an arbiter connected to the most significant bits of the two or more counters.

According to an aspect of the invention, the feedback loop includes a connection relationship between the final output terminals of the multiplexer array and the initial input terminals of the multiplexer array such that the two or more delay paths can be repeated evenly after the feedback loop And may include a feedback multiplexer to adjust.

According to an aspect, the feedback multiplexer may change the input-output correspondence of the feedback multiplexer in response to a determination that a first input terminal to a final output terminal correspondence of the multiplexer array with respect to a challenge input is changed.

According to an aspect, the feedback multiplexer may maintain the input-output correspondence of the feedback multiplexer in response to determining that the initial input terminal to final output terminal correspondence of the multiplexer array with respect to the challenge input is maintained.

According to an aspect, the feedback loop may further include an inverter for each of the at least two delay paths to increase the value of the counter in response to the iteration of the loop along the feedback loop.

According to an aspect, the counter may be comprised of a register.

According to an aspect, the arbiter may be configured as a flip-flop.

According to an aspect, outputting the different response may include calculating a difference between values of the counter at a time when the value of any one of the most significant bits of the two or more counters becomes one.

According to an aspect, the method may further include storing the first challenge input in a stable challenge input list in the challenge memory if the difference between the values of the counter according to the first challenge input is greater than a predetermined threshold value .

The disclosed technique may have the following effects. It is to be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, as it is not meant to imply that a particular embodiment should include all of the following effects or only the following effects.

According to the above-described counter-based physical copy prevention function device and the challenge-response obtaining method using the same, it is possible to improve the reliability of the delay-based PUF efficiently while occupying a small area. That is, the prior art has an additional circuit for correcting the environmental change to improve the reliability of the PUF, thereby solving the problem that a large area is required for the PUF circuit configuration and a large power consumption is also required.

In addition, according to the counter-based physical copy protection function apparatus and the challenge-response obtaining method using the counter-based physical copy protection function apparatus according to an embodiment of the present invention, it is considered that the challenge is unstable for the challenges with few differences between the delay paths, So that more reliable reliability can be achieved.

1 is a block circuit diagram showing a configuration of an Arbiter PUF which is a conventional delay-based physical copy protection function (Delay based PUF) device.
2 is a block circuit diagram showing a configuration of a counter-based physical copy prevention function device according to an embodiment of the present invention.
3 is a detailed configuration diagram of an embodiment related to the counter of FIG.
4 is a flowchart of a challenge-response acquisition method using a counter-based PUF according to an embodiment of the present invention.
5 is a detailed flowchart of the response output step of FIG.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate the understanding of the present invention, the same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

As we have seen, attempts have been made to use a physically unclonable function (PUF) with random variations occurring in the process for security purposes such as device authentication. However, for security purposes, the same challenge It is important to secure the reliability of the PUF that can guarantee the same response to the PUF.

As an approach for securing the reliability of the conventional PUF, the introduction of an additional circuit for correcting the change of the environment of the PUF device has been studied. However, this requires a large area in the PUF circuit configuration and consumes a lot of power.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a delay-based PUF (Delay based PUF) or an Arbiter PUF And methods.

The present invention aims to improve the reliability of the delay-based PUF simply and efficiently using a small area. If you add a counter to the end of the delay-based PUF and form a feedback loop that goes back to the beginning, the counter can, for example, act to amplify the difference between the two delay paths. This makes it possible to construct a delay-based PUF that can obtain a stable challenge-response pair even in the surrounding environment.

In the present invention, for example, a counter composed of a register prime number, for example, a basic logic gate, is used as a countermeasure to solve the reliability problem by using post processing or the like which occupies a large area and consumes a large amount of power. By adding only a small number of feedback loops, a significant increase in reliability can be expected with even a small additional area.

It is also possible to easily measure the difference between two delay paths formed by each challenge, for example by comparing the values of counters corresponding to two different delay paths. Using this technique, the Challenges with few differences in the delay path are regarded as unstable, and when the actual PUF is used, trimming can be used to improve the reliability of the PUF.

1 is a block circuit diagram showing a configuration of an Arbiter PUF which is a conventional delay-based physical copy protection function (Delay based PUF) device. As shown in Figure 1, the arbiter PUF includes a multiplexer array 10 and an arbiter 20 constructed by connecting one or more multiplexers 10-1, 10-2, ..., 10-N.

Input signals 1 are respectively input to the initial input terminals of the multiplexer array 10 to form the start points of two different delay paths and one or more multiplexers 10-1 and 10-2 included in the multiplexer array 10 , ..., 10-N each receive a challenge input signal corresponding to each multiplexer corresponding to an N-bit challenge input (3), and delay paths in the corresponding multiplexer according to each challenge input signal Crossed, or maintained. Thus, it is possible to set different delay paths according to different challenges.

The arbiter 20 is connected to the final output of the multiplexer array 10 and outputs a response (Response 5) according to the posterior relationship of each delay path, thereby enabling the output of the response corresponding to each challenge.

However, in order to use such a PUF device for security purposes, it is important to secure the reliability of the PUF that can guarantee the same response to the same challenge, and the introduction of an additional circuit for environmental condition correction There was a problem requiring consumption.

Counter-based physical copy protection function device

A counter-based PUF (Physically Unclonable Function) device and a challenge-response acquisition method using the same according to an embodiment of the present invention can improve the reliability of the delay-based PUF while minimizing the area and power requirements.

First, a counter-based PUF apparatus according to an embodiment of the present invention may add a counter composed of, for example, a register to the end of an existing delay-based PUF to form a feedback loop to return to the beginning . At this time, the feedback loop can maintain or change the path according to the challenge by using the multiplexer in order to make the path of each signal constant even in the repeated loop passing through the feedback loop when operating the delay-based PUF have. You can add an inverter to increment the counter value each time the loop is turned. The final response can be generated by connecting the most significant bit of the counter to the arbiter to determine which of the two signals is coming first.

2 is a block circuit diagram showing a configuration of a counter-based physical copy prevention function device according to an embodiment of the present invention. Hereinafter, the configuration of the counter-based PUF apparatus according to an embodiment of the present invention will be described in more detail with reference to FIG.

2, a counter-based PUF apparatus according to an exemplary embodiment of the present invention includes a multiplexer array 100 configured by connecting one or more multiplexers 100-1, 100-2, ..., 100-N, A counter 200, a feedback circuit 300, and an arbiter 400.

Each of the one or more multiplexers 100-1, 100-2, ..., 100-N includes at least two input terminals and at least two output terminals corresponding to at least two delay paths, a Challenge input terminal The first input terminals 110-1 and 110-2 and the final output terminals 120-1 and 120-2 are connected in series by the multiplexers 100-1 to 100- 120-2. ≪ / RTI >

The input signals 101 are respectively input to the initial input terminals 110-1 and 110-2 of the multiplexer array 100 to form the start point of two different delay paths, for example, to the multiplexer array 100 Each of the one or more multiplexers 100-1, 100-2, ..., 100-N included therein receives a challenge input signal corresponding to each multiplexer corresponding to an N-bit challenge input 103, Depending on the signal, the delay paths in the corresponding multiplexer may cross or maintain each other. Thus, it is possible to set different delay paths according to different challenges.

The two or more counters 200 are connected to the final output terminals 120-1 and 120-2 of the multiplexer array 100 so that each time they receive the signals of each delay path, From the highest bit to the highest counter. The size of the counter 200 may be set based on the degree of reliability required according to the application field of the counter based PUF according to an embodiment of the present invention. When a relatively high reliability is required, the number of loops for the multiplexer array 100 can be increased by setting the value of the counter to a large value. If a relatively low reliability is required, the value of the counter is set small, Lt; / RTI > can be reduced. On the other hand, the counter 200 may be configured as, for example, a register.

The feedback loop 300 connects the final output terminals 120-1 and 120-2 of the multiplexer array 100 to the initial input terminals 110-1 and 110-2 of the multiplexer array 100, It is possible to form an iterative loop for the array 100 and iteratively progress the delay paths configured by the multiplexer array 100 a number of times that can be adjusted according to the counter size.

On the other hand, for each of a plurality of different challenges 103 that may be input, in order for the iterative loop of the multiplexer array 100 to repeat over a certain delay path even when any challenge 103 is input, It is necessary to appropriately adjust the connection relationship between the final output terminals 120-1 and 120-2 of the multiplexer array 100 and the initial input terminals 110-1 and 110-2 of the multiplexer array 100. [ Thus, the feedback loop 300 may be configured such that the final output terminals 120-1, 120-2 of the multiplexer array 100 and the output terminals 120-1, 120-2 of the multiplexer array 100 are coupled to the multiplexer array 100, such that two or more delay paths may be repeated constantly after the feedback loop 300, And a feedback multiplexer 310 that adjusts the connection relationship between the initial input terminals 110-1 and 110-2 of the base station 100. [

For example, if the first challenge input is input, the signal input to the first input terminal 110-1 is output to the final output terminal 120-1 and the signal input to the first input terminal 110-2 A signal input to the first input terminal 110-1 may be output to the final output terminal 120-2 and a signal input to the first input terminal 110-1 may be output to the final output terminal 120-2. A signal input to the input terminal 110-2 can be output to the final output terminal 120-1. Accordingly, when the first challenge input is input, the feedback multiplexer 310 maintains the delay path to connect the final output terminal 120-1 to the first input terminal 110-1 and the final output terminal 120-2 Can be connected to the first input terminal 110-2. Also, when the second challenge input is input, the feedback multiplexer 310 crosses the delay path to connect the final output terminal 120-1 to the first input terminal 110-2 and the final output terminal 120-2 And can be connected to the first input terminal 110-1.

In other words, the feedback multiplexer 310 may change the input-output correspondence of the feedback multiplexer 310 in response to determining that the first input terminal-final output terminal correspondence of the multiplexer array 100 with the challenge input is changed, Output correspondence of the feedback multiplexer 310 in response to the determination that the original input terminal to final output terminal correspondence of the multiplexer array 100 according to the challenge input is maintained.

On the other hand, the feedback loop 300 may further include an inverter 320 for each of the two or more delay paths to increase the value of the counter 200 in response to the iteration of the loop along the feedback loop 300. Here, the inverter 320 may be disposed before the feedback multiplexer 310 described above, and may be disposed after the feedback multiplexer 310. [

Referring again to FIG. 2, the arbiter 400 is connected to the most significant bits of the two or more counters 200, and outputs a different response (Response 105) according to the arrival sequence of signals corresponding to two or more delay paths By outputting, it is possible to output a response corresponding to each challenge. By repeating the respective delay paths according to the counter 200 and the feedback circuit 300, the difference between at least two delay paths can be further amplified, and the improvement in reliability in which the same response can be output for the same challenge is minimized Can be achieved based on the area and power consumption.

Selective challenge  use

Meanwhile, the counter-based PUF device according to an embodiment of the present invention can selectively use stable challenges when using the actual PUF to further improve reliability. To do this, for example, the difference between the two counters can be calculated at the moment when the most significant bit of any one of the two counters has a value of one. The larger the absolute value of the calculated value, the greater the difference in delay between the two paths. Therefore, the stable challenge can be selected. Since the level of reliability required varies depending on the place of use of each PUF, the size of the counter to be used and the degree of the number of challenges to be selected can be selectively determined according to the required reliability level.

3 is a detailed configuration diagram of one embodiment related to the counter of Fig. 3, the counter-based PUF apparatus according to an exemplary embodiment of the present invention calculates a difference between the values of the counter 200 at the time when any one of the most significant bits of the two or more counters 200 becomes 1 And an operation unit 210 for calculating a difference. If the difference between the values of the counter 200 at the time when the value of any one of the most significant bits of the counter 200 becomes 1 according to the first challenge input is smaller than a preset threshold value as a result of the calculation, The first challenge input and the response in response to the first challenge input may no longer be used as a challenge-response pair.

On the other hand, when the difference between the values of the counter 200 at the time when the value of any one of the most significant bits of the counter 200 according to the first challenge input becomes 1 is larger than a preset threshold value The challenge memory 220 may store the first challenge input as a stable challenge input list.

According to another embodiment of the present invention, the computing unit 210 and the challenge memory 220 described above may exist outside the counter-based PUF apparatus according to an embodiment of the present invention. That is, the operation unit 210 and the challenge memory 220 are included in a separate entity (for example, a server) separate from the counter-based PUF device according to the usage of the counter-based PUF device, It may perform operations on the bits of the counter 200 included in the counter based PUF device through connection with the device and store a stable challenge input list corresponding to the result.

According to an aspect, a challenge input list is generated by inputting a plurality of different challenges prior to actual utilization of the counter-based PUF device according to an embodiment of the present invention, and a challenge stored in the challenge input list of the challenge memory 200 Can be used for the use of PUF devices for practical security purposes.

On the other hand, as previously discussed, the predetermined threshold value for the determination as a stable challenge can be determined based on the level of reliability required depending on the usage of the PUF.

Counter based PUF  Using challenge - How to get response

Meanwhile, FIG. 4 is a flowchart of a challenge-response acquisition method using a counter-based PUF according to an embodiment of the present invention, and FIG. 5 is a detailed flowchart of the response output step of FIG. Hereinafter, a method for obtaining a challenge-response using a counter-based PUF according to an embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5. FIG.

As shown in FIG. 4, a challenge-response acquisition method using a counter based PUF (Physically Unclonable Function) according to an exemplary embodiment of the present invention includes firstly inputting at first input terminals of a multiplexer array constructed by connecting one or more multiplexers, Signal, and may receive a signal corresponding to the challenge input at each of the challenge input terminals (step 410). Here, the multiplexer may include at least two input terminals and at least two output terminals corresponding to at least two delay paths, and a challenge input terminal.

Thereafter, a signal from the final output terminal is received at two or more counters connected to the final output terminals of the multiplexer array, and the signals at the final output terminals of the multiplexer array are received at the initial input terminals of the multiplexer array via the feedback loop, respectively (Step 420).

Further, in the arbiter connected to the most significant bits of the two or more counters, it is possible to output a different response according to the arrival sequence of the signal corresponding to each of the two or more delay paths (step 430).

5, in the challenge-response obtaining method using the counter-based PUF according to an exemplary embodiment of the present invention, the step of outputting the different response (step 430) And calculating a difference between the values of the counter at a time when one value becomes 1 (step 431). In addition, the challenge-response acquisition method using the counter-based PUF according to an embodiment of the present invention is characterized in that when the difference between the values of the counter according to the first challenge input is greater than a predetermined threshold value, the first challenge input is transmitted to the challenge memory (Step 433) in a stable challenge input list in the network.

The more specific operation of the challenge-response acquisition method using the counter-based PUF according to the embodiment of the present invention or the specific configuration of the counter-based PUF used therefor is the same as the operation and configuration of the counter based PUF according to the above- .

The method for obtaining the challenge-response using the counter-based PUF control algorithm or the counter based PUF according to the present invention described above can be implemented as a computer-readable code on a computer-readable recording medium. The computer-readable recording medium includes all kinds of recording media storing data that can be decoded by a computer system. For example, there may be a ROM (Read Only Memory), a RAM (Random Access Memory), a magnetic tape, a magnetic disk, a flash memory, an optical data storage device and the like. The computer-readable recording medium may also be distributed and executed in a computer system connected to a computer network and stored and executed as a code that can be read in a distributed manner.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the present invention can be extended to all of the methods for improving the performance of the delay-based PUF in addition to the basic delay-based PUF described above.

101: input signal
103: Challenge input signal
105: Response signal
100: multiplexer array
110: First input terminal
120: Final output terminal
200: Counter
300: feedback loop
310: Feedback Multiplexer
320: Inverter
400: the arbiter

Claims (20)

A delay path element including at least two input terminals and at least two output terminals corresponding to at least two delay paths, and a challenge input terminal;
Two or more counters respectively connected to the output terminals of the delay path element;
A feedback loop connecting the output terminals of the delay path element to the input terminals of the delay path element, respectively;
An arbiter connected to each of the most significant bits of the two or more counters to output a different response depending on a destination of a signal corresponding to each of the two or more delay paths; And
And a calculator for calculating a difference between values of the counter at a time when the value of any one of the most significant bits of the two or more counters becomes 1. The Counter based PUF (Physically Unclonable Function)
The method according to claim 1,
The feedback loop includes a feedback multiplexer that adjusts the connection relationship between the output terminals of the delay path element and the input terminals of the delay path element such that the two or more delay paths can be repeated constantly after passing through the feedback loop Container-based, PUF device.
3. The method of claim 2,
Wherein the feedback multiplexer changes an input-output correspondence of the feedback multiplexer in response to a determination that an input terminal-output terminal correspondence of the delay path element with respect to a challenge input is changed.
3. The method of claim 2,
Wherein the feedback multiplexer maintains the input-output correspondence of the feedback multiplexer in response to a determination that the input terminal-output terminal correspondence of the delay path element along with the challenge input is maintained.
The method according to claim 1,
Wherein the feedback loop further comprises an inverter for each of the at least two delay paths to increase the value of the counter in response to a loop iteration according to the feedback loop.
The method according to claim 1,
Wherein the counter is comprised of a register.
The method according to claim 1,
Wherein the arbiter is configured as a flip-flop.
delete The method according to claim 1,
Wherein the response based on the first challenge input and the first challenge input is no longer used as a challenge-response pair if the difference between the values of the counter according to the first challenge input is less than a predetermined threshold, PUF device.
The method according to claim 1,
Further comprising a challenge memory to store the first challenge input in a stable challenge list if the difference between the values of the counter according to the first challenge input is greater than a predetermined threshold.
11. The method of claim 10,
Wherein the counter based PUF device is connected to a server,
Wherein the operation unit and the challenge memory are included in the server.
At least two input terminals and at least two output terminals corresponding to at least two delay paths and an input terminal of a delay path element including a challenge input terminal and receiving a challenge input at a challenge input terminal, ≪ / RTI >
Receiving a signal from the output terminal at two or more counters connected to the output terminals of the delay path element respectively and for receiving signals of the output terminals of the delay path element through input terminals of the delay path element via a feedback loop ; And
Outputting a different response according to an arrival sequence of a signal corresponding to each of the two or more delay paths in an arbiter connected to the most significant bits of the two or more counters,
Wherein outputting the different response comprises calculating a difference between values of the counter at a time when the value of any one of the most significant bits of the two or more counters becomes 1. The counter based PUF (Physically Unclonable Function) ≪ / RTI >
13. The method of claim 12,
The feedback loop includes a feedback multiplexer that adjusts the connection relationship between the output terminals of the delay path element and the input terminals of the delay path element such that the two or more delay paths can be repeated constantly after passing through the feedback loop Based PUF, the method comprising:
14. The method of claim 13,
Wherein the feedback multiplexer changes an input-output correspondence of the feedback multiplexer in response to a determination that an input terminal-output terminal correspondence of the delay path element with respect to a challenge input is changed.
14. The method of claim 13,
Wherein the feedback multiplexer maintains the input-output correspondence of the feedback multiplexer in response to a determination that the input terminal-output terminal correspondence of the delay path element along with the challenge input is maintained.
13. The method of claim 12,
Wherein the feedback loop further comprises an inverter for each of the at least two delay paths to increase the value of the counter in response to a loop iteration in accordance with the feedback loop.
13. The method of claim 12,
Wherein the counter is comprised of a register.
13. The method of claim 12,
Wherein the arbiter is configured as a flip-flop.
delete 13. The method of claim 12,
Further comprising storing the first challenge input in a stable challenge input list in the challenge memory if the difference between the values of the counter according to the first challenge input is greater than a predetermined threshold value. - Response acquisition method.

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