KR101865068B1 - Apparatus and method for mapping/demapping signal in a communication system using a low density parity check code - Google Patents

Abstract

The present invention relates to a signal mapping method in a signal transmission apparatus of a system using a Low Density Parity Check (LDPC) code, the method comprising the steps of: storing LDPC codeword bits in a column direction; Outputting stored LDPC codeword bits in a row direction and demultiplexing the output bits using a de-multiplexing scheme to generate sub-streams; And mapping the bits included in each of the lower streams to a symbol in a signal constellation, wherein the demultiplexing scheme includes a modulation scheme used in the signal transmission apparatus, a length of the LDPC codeword, Is determined correspondingly.

Description

Field of the Invention [0001] The present invention relates to a signal mapping / demapping apparatus and a signal mapping method in a system using a low density parity check code,

The present invention relates to a signal mapping / demapping apparatus and method in a system using a Low Density Parity Check (LDPC) code.

In a communication or broadcasting system, the performance of a link is significantly degraded due to various noise, fading phenomena, and inter-symbol interference (ISI) of a channel. Therefore, it is essential to develop overcoming techniques for noise, fading and ISI in order to realize communication or broadcasting systems requiring high data throughput and reliability, such as next generation mobile communication, digital broadcasting and portable Internet. In recent years, error-correcting codes have been actively studied as methods for efficiently restoring information distortion and increasing reliability of communication or broadcast data.

The low-density parity-check (LDPC) code first introduced by Gallager in the 1960s as a representative example of error correction codes has not been used for a long time due to its implementation complexity far surpassing the technology at that time. However, when the LDPC code is re-studied in the latter half of the 1990s, iterative decoding based on a sum-product algorithm is applied on the Tanner graph corresponding to the LDPC code, As performance is known, it is being used or considered in various systems.

An LDPC code can be defined using a parity-check matrix and can be expressed using a bipartite graph commonly referred to as a Tanner graph. The bipartite graph consists of two different kinds of vertices called a variable node and a check node. The variable node corresponds to the encoded bit on a one-to-one basis, and the check node represents an algebraic relation of the encoded bits.

1 is an example of a parity check matrix H1 of an LDPC code including four rows and eight columns. Referring to FIG. 1, a codeword having a length of 8 is generated because the parity check matrix H1 has eight columns

2 is a diagram illustrating a Tanner graph corresponding to a parity check matrix H1 of the LDPC code of FIG.

2, the Tanner graph includes eight variable nodes X1 202, X2 204, X3 206, X4 208, X5 210, X6 212, X7 214, X8 216, and four check nodes 218, 220, 222, and 224. Here, the i-th column and the j-th row of the parity check matrix H1 correspond to the variable nodes x _i and j-th check nodes, respectively. The value of 1 at the intersection of the i-th column and the j-th row of the parity check matrix H1, that is, a value other than 0 means that the variable node x _i and the j-th check Which means that there is an edge between the nodes.

In the Tanner graph, the degree of the variable node and the check node means the number of segments connected to each node. This means that the non-zero entry in the column or row corresponding to the corresponding node in the parity check matrix ). For example, in FIG. 2, variable nodes X1 202, X2 204, X3 206, X4 208, X5 210, X6 212, X7 214, X8 216, The orders of the check nodes 218, 220, 222, and 224 are 6, 5, 5, and 5 in order, respectively. do. The number of non-zero elements in each column of the parity check matrix H1 of FIG. 1 corresponding to the variable nodes of FIG. 2 may be calculated using the above-described orders 4, 3, 3, 3, 2, 2, 2, and the number of non-zero elements in each row of the parity check matrix H1 of FIG. 1 corresponding to the check nodes of FIG. 2 is in the order of 6, 5, 5, It matches.

In order to express the degree distribution for a node of an LDPC code, the ratio of the number of variable nodes with degree _i to the total number of variable nodes is f _i , and the number of check nodes with degree j and the total number Let the ratio of the number of g _j. For example, f2 = 4/8, f3 = 3/8 and f4 = 1/8 for the LDPC codes corresponding to FIGS. 1 and 2 and fi = 0 for i? = 3/4, g6 = 1/4, j? 5, and gi = 0 for 6. _Assuming that the length of the LDPC code is N _ldpc , that is, the number of columns is N _ldpc , and the number of rows is N _ldpc / 2, the density of nonzero elements in the parity check matrix having the above- Lt; / RTI >

If N _ldpc increases in Equation (1), the density of weight 1 continues to decrease in the parity check matrix. Generally, the LDPC code is inversely proportional to the non-zero element with respect to the code length N _ldpc , so that when N _ldpc is large, the nonzero element has a very low density. The term low-density in the name of an LDPC code comes from this reason.

3 is a diagram for explaining a general LDPC coding process.

와 같이 표기한다. 이하에서는 LDPC 부호기(310)에 입력되는 정보어의 비트들을 개별적으로 정보 비트라 칭한다. 즉, 정보어(information word)는 K_ldpc 개의 정보 비트들(information bits)로 구성된다. 이하에서는 정보어와 정보 비트들을 혼용하여 사용한다.3, the LDPC encoder 310 uses an information word having a length of K _ldpc as an input, and the information word block includes, for example,

As shown in Fig. Hereinafter, the bits of the information word input to the LDPC encoder 310 are individually referred to as information bits. That is, the information word consists of K _ldpc information bits. Hereinafter, information words and information bits are used in combination.

를 생성하며, 상기 정보 비트들과 패리티 비트들을 사용하여 도 3에 도시한 바와 같이, 부호어(codeword)

를 생성한다. 이와 같이, 상기 패리티 검사 행렬과 정보 비트들을 이용하여 LDPC 부호어를 생성하는 과정을 LDPC 부호화 과정이라 한다.The LDPC encoder 310 uses the parity check matrix having the length (the number of columns) N _ldpc to calculate N _ldpc - K _ldpc parity bits

As shown in FIG. 3, by using the information bits and the parity bits, a codeword is generated,

. The process of generating an LDPC codeword using the parity check matrix and the information bits is referred to as an LDPC encoding process.

Due to the demand for high-speed data transmission and the development of hardware, there is an increasing interest in quadrature amplitude modulation (QAM) modulation schemes with high frequency efficiency. In general, the variable nodes of an LDPC code have different error correction capabilities depending on the degree. Also, when using the QAM modulation scheme, each bit included in one symbol has a different error probability. Therefore, even when the same LDPC code is used, different performance is obtained according to the method of replacing the LDPC codeword bits with symbols in the QAM signal constellation.

The present invention provides a data processing method and apparatus for configuring transmission symbols in a broadcasting / communication system.

The present invention also provides a channel coding / decoding method and apparatus using an LDPC that guarantees optimal performance in consideration of a corresponding structure in a broadcasting / communication system having a specific structure.

The present invention proposes a signal mapping / demapping apparatus and method in a system using an LDPC code. Also, the present invention proposes an apparatus and method for mapping / demapping an LDPC codeword and a QAM modulation symbol in a system using an LDPC code.

The apparatus proposed in the present invention comprises: 1. A signal transmission apparatus for a system using a Low Density Parity Check (LDPC) code, the apparatus comprising: a receiver for storing LDPC codeword bits in a column direction and for storing the stored LDPC codeword bits in a row direction A demultiplexer for generating sub-streams by demultiplexing the output bits using a de-multiplexing scheme, and a demultiplexer for demultiplexing the bits included in each of the lower streams into a signal constellation And a symbol mapper for mapping the symbols into symbols. Another apparatus proposed in the present invention is a system comprising: A signal receiving apparatus of a system using a Low Density Parity Check (LDPC) code, comprising: a multiplexer for multiplexing sub-streams using a multiplexing scheme; And an LDPC decoder for performing LDPC decoding on the inversely interleaved bits to generate LDPC codeword bits, wherein the multiplexing scheme is determined according to a demultiplexing scheme used in a signal transmission apparatus, Scheme is determined according to the modulation scheme used in the signal transmission apparatus, the length of the LDPC codeword, and the number of the lower streams.

The method proposed by the present invention comprises: A method for signal mapping in a signal transmission apparatus in a system using a Low Density Parity Check (LDPC) code, the method comprising: storing LDPC codeword bits in a column direction; And outputting the bits in a row direction; generating sub-streams by demultiplexing the output bits using a de-multiplexing scheme; And mapping the bits included in the signal constellation into a symbol in the constellation, wherein the demultiplexing scheme comprises: a modulation scheme used in the signal transmission apparatus; a length of the LDPC codeword; .

Another method proposed by the present invention is as follows. A signal demapping method in a signal receiving apparatus of a system using a low density parity check (LDPC) code, the method comprising: multiplexing sub-streams using a multiplexing scheme; And de-interleaving the multiplexed bits, and generating LDPC codeword bits by performing LDPC decoding on the deinterleaved bits, wherein the multiplexing scheme is performed in accordance with a demultiplexing scheme used in a signal transmission apparatus And the demultiplexing method is determined according to the modulation scheme used in the signal transmission apparatus, the length of the LDPC codeword, and the number of the lower streams.

The present invention can construct an error-robust communication or broadcasting system using an LDPC encoder / decoder and a demultiplexer / multiplexer.

Also, the present invention can guarantee optimal performance considering a modulation scheme in a communication or broadcasting system using an LDPC code.

1 is a diagram illustrating an example of a parity check matrix of an LDPC code having a length of 8,
2 shows a Tanner graph of an example of a parity check matrix of an LDPC code having a length of 8,
3 is a block diagram illustrating an LDPC encoding process,
4 is a block diagram of a transmitter block of a communication or broadcasting system using an LDPC code,
5 shows a 16-QAM signal constellation,
6 is a diagram illustrating a 64-QAM signal constellation,
7 is a diagram showing a 256-QAM signal constellation
8 is a diagram illustrating an implementation of an interleaver,
Figure 9 shows an implementation of a demultiplexer,
10 is a diagram illustrating an operation of a demultiplexer according to an embodiment of the present invention.
11 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
12 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
13 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
FIG. 14 illustrates an operation of a demultiplexer according to another embodiment of the present invention; FIG.
15 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
16 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
17 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
18 is a diagram illustrating an operation of a demultiplexer according to another embodiment of the present invention.
19 is a receiver block diagram of a communication or broadcasting system using an LDPC code,
FIG. 20 schematically illustrates the internal structure of the demultiplexer 440 of FIG. 4,
21 schematically shows the internal structure of the multiplexer 1920 of FIG. 19; FIG.

Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that only the parts necessary for understanding the operation according to the present invention will be described in the following description, and the description of other parts will be omitted so as not to disturb the gist of the present invention.

The present invention proposes a signal mapping / demapping apparatus and method in a system using a Low Density Parity Check (LDPC) code.

Also, the present invention proposes an apparatus and method for mapping / demapping an LDPC codeword and a quadrature amplitude modulation (QAM) modulation symbol in a system using an LDPC code.

In the following description of the present invention, a system using the LDPC code can be variously configured. For example, a broadcasting system such as a DVB ( Next Generation Handheld) system and a MMT (Digital Video Broadcasting) An Evolved Packet System (EPS), an LTE (Long-Term Evolution) mobile communication system, an IEEE (Institute of Electrical and Electronic Engineers) of Electrical and Electronics Engineers) 802.16m communication system. It should be understood that the present invention is described by taking an LDPC code as an example, but other codes as well as an LDPC code may be applied to the apparatus and method proposed in the present invention. It should be understood that the present invention is described by taking the QAM scheme as an example, but other modulation schemes as well as the QAM scheme may be applied to the apparatus and method proposed in the present invention.

4 is a block diagram of a transmitter block of a communication or broadcasting system using an LDPC code.

가 송신기의 LDPC 부호화기(410)로 입력되면 상기 LDPC 부호화기(410)는 상기 정보어 I를 부호화하여 N_ldpc - K_ldpc 개의 패리티 비트들

을 생성하고, 길이가 N_ldpc인 LDPC 부호어

를 생성하여 전처리기(420)로 전달한다. 상기 전처리기(420)는 상기 부호어

에 인터리빙 등을 수행한 결과인

를 구성하여 인터리버(430)로 전달한다. 일부 구현에서 상기 전처리기(420)는 생략되거나 그 기능이 인터리버(430)에 통합될 수 있음에 유의한다. 상기 인터리버(430)는 상기 U 혹은 전처리기가 생략되었을 경우에는 상기 Λ를 Nc개의 열에 열 방향(column-wise)으로 저장(write)하고 행 방향(row-wise)으로 출력(read)하여 그 출력 결과인

를 역다중화기(440)에 전달한다. 상기 역다중화기(440)는 V를 Nc개 단위로 역다중화하여 N_substreams개의 하위 스트림

,

를 생성하여 심볼맵핑기(450)로 전송한다. 상기 심볼 맵핑기(450)는 각각의 하위 스트림들에 해당하는 비트들을 입력으로 사용하여 길이가

인 셀워드

를 구성하고 이를 신호 성좌 내의 신호 점에 맵핑하여 심볼 Z를 생성한다. 이때

는 N_substreams 의 약수임에 유의한다. 도 5와 도 6, 그리고 도 7은 각각 16-QAM과 64-QAM, 그리고 256-QAM 변조 방식에서 셀워드와 신호 성좌간의 맵핑을 나타낸 도면이다.Referring to FIG. 4,

The LDPC encoder 410 encodes the information word I and outputs N _ldpc -K _ldpc parity bits

And generates an LDPC codeword having a length of N _ldpc

And transmits it to the preprocessor 420. The preprocessor 420 includes a pre-

As a result of performing interleaving and the like

And transmits it to the interleaver 430. Note that in some implementations the preprocessor 420 may be omitted or its functionality may be incorporated into the interleaver 430. When the U or the preprocessor is omitted, the interleaver 430 writes the Λ in Nc columns in a column-wise manner and reads it in a row-wise manner, sign

To the demultiplexer (440). The demultiplexer 440 demultiplexes V in units of Nc to generate N _substreams

,

And transmits it to the symbol mapper 450. The symbol mapper 450 uses the bits corresponding to the respective lower streams as an input,

In cell word

And maps it to a signal point in the signal constellation to generate a symbol Z. At this time

Note that N is a divisor of N _substreams . 5, 6, and 7 are mapping diagrams of cell words and signal constellations in 16-QAM, 64-QAM, and 256-QAM modulation schemes, respectively.

FIG. 8 is a conceptual diagram illustrating an embodiment of the interleaver 430 of FIG. It is assumed that the interleaver 430 of FIG. 8 is composed of Nc rows and N _ldpc / Nc rows.

In the embodiment of the interleaver 430, the number Nr of rows and the number of columns Nc of the interleaver according to the modulation scheme when N _ldpc = 16200 are shown in Table 1 below.

The input U or A of the interleaver 430 is sequentially stored in Nc columns in the column direction and output in the row direction. Note that the first storage location in each column may be shifted by the twist parameter tc. As one example of the twist parameter, tc according to the modulation scheme when N _ldpc = 16200 is shown in Table 2 below.

FIG. 9 is a conceptual diagram illustrating an embodiment of the demultiplexer 440 of FIG.

The operation of the demultiplexer 430 is described by the relationship of Vi (i = 0,1, ..., N _ldpc- 1) and bj (j = 0,1, ..., N _substreams- 1) and can, N if _ldpc is a multiple of N _substreams, it is apparent that can be extended by the same rules.

10 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 16-QAM modulation is used according to an embodiment of the present invention.

Assuming that N _substreams = 8 in FIG. 10, demultiplexer 440 follows the following rules when mapping input bits v0 through v7 to output bits b0 through b7. In other words,

Bit v0 to bit b2.

Bit v1 to bit b4,

Bit v2 to bit b5,

Bit v3 to bit b0,

Bit v4 to bit b7

Bit v5 to bit b1

Bit v6 to bit b3

Bit v7 to bit b6

Mapping.

11 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 64-QAM modulation is used according to another embodiment of the present invention.

Assuming that N _substreams = 12 in FIG. 11, the demultiplexer 440 follows the following rules when mapping the input bits v0 to v11 to the output bits b0 to b11. In other words,

Bit v0 to bit b4,

Bit v1 to bit b0,

Bit v2 to bit b1,

Bit v3 to bit b6,

Bit v4 to bit b2,

Bit v5 to bit b3,

Bit v6 to bit b8,

Bit v7 to bit b9,

Bit v8 to bit b7,

Bit v9 to bit b5,

Bit v10 to bit b10,

Bit v11 to bit b11

Mapping.

12 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 16-QAM modulation is used in another embodiment of the present invention.

Assuming that N _substreams = 8 in FIG. 12, the demultiplexer 440 follows the following rules when mapping the input bits v0 to v7 to the output bits b0 to b7. In other words,

Bit v0 to bit b2,

Bit v1 to bit b4,

Bit v2 to bit b5,

Bit v3 to bit b1,

Bit v4 to bit b6,

Bit v5 to bit b0,

Bit v6 to bit b7,

Bit v7 to bit b3

Mapping.

13 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 16-QAM modulation is used in another embodiment of the present invention.

Assuming that N _substreams = 8 in FIG. 13, the demultiplexer 440 follows the following rules when mapping the input bits v0 to v7 to the output bits b0 to b7. In other words,

Bit v0 to bit b2,

Bit v1 to bit b0,

Bit v2 to bit b1,

Bit v3 to bit b3,

Bit v4 to bit b6,

Bit v5 to bit b4,

Bit v6 to bit b7,

Bit v7 to bit b5

Mapping.

14 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 64-QAM modulation is used in another embodiment of the present invention.

Assuming that N _substreams = 12 in FIG. 14, the demultiplexer 440 follows the following rules when mapping the input bits v0 to v11 to the output bits b0 to b11. In other words,

Bit v0 to bit b4,

Bit v1 to bit b2,

Bit v2 to bit b0,

Bit v3 to bit b5,

Bit v4 to bit b6,

Bit v5 to bit b1,

Bit v6 to bit b3,

Bit v7 to bit b7,

Bit v8 to bit b8,

Bit v9 to bit b9,

Bit v10 to bit b10,

Bit v11 to bit b11

Mapping.

15 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 64-QAM modulation is used according to another embodiment of the present invention.

Assuming that N _substreams = 12 in FIG. 15, the demultiplexer 440 follows the following rules when mapping the input bits v0 to v11 to the output bits b0 to b11. In other words,

Bit v0 to bit b4,

Bit v1 to bit b0,

Bit v2 to bit b1,

Bit v3 to bit b6,

Bit v4 to bit b2,

Bit v5 to bit b3,

Bit v6 to bit b5,

Bit v7 to bit b8,

Bit v8 to bit b7,

Bit v9 to bit b10,

Bit v10 to bit b9,

Bit v11 to bit b11

Mapping.

16 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 16-QAM modulation is used according to another embodiment of the present invention.

Assuming that N _substreams = 8 in FIG. 16, demultiplexer 440 follows the following rules when mapping input bits v0 through v7 to output bits b0 through b7. In other words,

Bit v0 to bit b2,

Bit v1 to bit b0,

Bit v2 to bit b4,

Bit v3 to bit b1,

Bit v4 to bit b6,

Bit v5 to bit b5,

Bit v6 to bit b7,

Bit v7 to bit b3

Mapping.

17 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 256-QAM modulation is used according to another embodiment of the present invention.

Assuming that N _substreams = 8 in FIG. 17, demultiplexer 440 follows the following rules when mapping input bits v0 through v7 to output bits b0 through b7. In other words,

Bit v0 to bit b4,

Bit v1 to bit b0,

Bit v2 to bit b1,

Bit v3 to bit b2,

Bit v4 to bit b5,

Bit v5 to bit b3,

Bit v6 to bit b6,

Bit v7 to bit b7

Mapping.

18 is a conceptual diagram illustrating the operation of a demultiplexer when N _ldpc = 16200 and 256-QAM modulation is used according to another embodiment of the present invention.

_Assuming that N _substreams = 8 in FIG. 18, demultiplexer 440 follows the following rules when mapping input bits v0 through v7 to output bits b0 through b7. In other words,

Bit v0 to bit b4,

Bit v1 to bit b0,

Bit v2 to bit b5,

Bit v3 to bit b1,

Bit v4 to bit b2,

Bit v5 to bit b3,

Bit v6 to bit b6,

Bit v7 to bit b7

Mapping.

As described above, according to the present invention, when LDPC codeword bits are input to a symbol mapper, they are converted and inputted according to a predetermined rule through a demultiplexer, so that when mapping modulation symbols (e.g., symbols in a QAM signal constellation) FIG. 19 is a block diagram of a receiver block of a communication or broadcasting system using an LDPC code.

인 수신 심볼 백터

가 수신기의 비트 매트릭 계산기(1910)로 입력되면, 상기 비트 매트릭 계산기(1910)는

개의 하위 스트림

,

에 대한 비트 매트릭 추정치

,

를 계산하여 다중화기(1920)로 전달한다. 이 때 상기 비트 매트릭은 LDPC 부호를 복호하기 위한 값으로 로그우도 비율(Log-Likelihood Ratio: LLR)이 대표적으로 사용된다. 상기 다중화기(1920)는 상기

,

를 다중화하여 길이가

인 이진 벡터

에 대한 비트 매트릭 벡터 추정치

를 생성하여 역인터리버(1930)에 전달한다. 상기 역인터리버(1930)는 상기 비트 매트릭 벡터

에 송신기 인터리버(도 4의 430)의 역연산을 적용하고 그 결과로

에 대한 비트 매트릭 벡터 추정치

를 후처리기(1940)로 전달한다. 상기 후처리기(1940)는 상기 비트 매트릭 벡터

에 송신기 전처리기(도 4의 420)의 역연산을 적용하고 그 결과로 송신 LDPC 부호어

에 대한 비트 매트릭 추정치

를 생성하여 LDPC 복호기(1940)로 전달한다. 상기 LDPC 복호기(1940)는 상기 비트 매트릭 벡터

를 입력으로 사용하여 LDPC 부호의 복호를 수행하고 정보어 블록

에 대한 추정 값

를 생성한다.Referring to Figure 19,

Receive symbol vector

Is input to the bit metric calculator 1910 of the receiver, the bit metric calculator 1910

Substreams

,

Lt; RTI ID = 0.0 >

,

And transmits it to the multiplexer 1920. At this time, the bit metric is a value for decoding an LDPC code, and a log-likelihood ratio (LLR) is typically used. The multiplexer 1920 multiplexes

,

Are multiplexed so that the length is

In binary vector

The bit-metric vector estimate < RTI ID = 0.0 &

And transmits it to the de-interleaver 1930. The de-interleaver 1930 receives the bit-

(430 in Fig. 4) to the transmitter interleaver

The bit-metric vector estimate < RTI ID = 0.0 &

To the post-processor 1940. The post-processor 1940 receives the bit-

(420 in FIG. 4) to the transmitter pre-processor (420 in FIG. 4)

Lt; RTI ID = 0.0 >

And transfers it to the LDPC decoder 1940. The LDPC decoder 1940 receives the bit-

As an input, performs decoding of the LDPC code,

Estimated value for

.

20 schematically shows the internal structure of the demultiplexer 440 of FIG.

Referring to FIG. 20, the demultiplexer 440 includes a demultiplexing unit 441 and a selection signal generating unit 442.

개의 하위 스트림을 생성한다. 상기 선택신호 생성 유닛(442)은 인터리빙된 부호어의 각각의 비트들이 어떤 하위 스트림에 할당될지 결정한다. 상기 선택신호 생성 유닛(442)은 메모리에 저장된 값을 읽거나 일정한 규칙을 가지는 신호를 생성하여 선택신호를 출력한다. 이 때 상기 선택신호 생성 유닛(442)의 출력 값은 사용되는 오류정정부호의 종류와 부호어 길이, 부호율, 변조 방식 등에 따라 결정되며, 시스템의 오류정정능력에 영향을 미치는 중요한 요인이다.The demultiplexing unit 441 receives the interleaved codeword and uses the selection signal output from the selection signal generating unit 442

≪ / RTI > The selection signal generating unit 442 determines to which sub-stream each bit of the interleaved codeword is allocated. The selection signal generating unit 442 reads a value stored in the memory or generates a signal having a predetermined rule and outputs a selection signal. At this time, the output value of the selection signal generating unit 442 is determined according to the type of the error correction code used, the codeword length, the coding rate, the modulation method, and the like, and is an important factor affecting the error correction capability of the system.

21 is a view schematically showing the internal structure of the multiplexer 1920 of FIG.

Referring to FIG. 21, the multiplexer 1920 includes a multiplexing unit 1921 and a selection signal generating unit 1922.

개의 하위 스트림을 입력으로 하고, 선택신호 생성 유닛(1922)의 출력인 선택신호를 사용하여 인터리빙된 부호어의 추정 값을 출력한다. 상기 선택신호 생성 유닛(1921)은 인터리빙된 부호어의 추정 값 중 각각의 비트 값들을 어떤 하위 스트림에서 취할지를 결정한다. 상기 선택신호 생성 유닛(1922)은 메모리에 저장된 값을 읽거나 일정한 규칙을 가지는 신호를 생성하여 선택신호를 출력하며, 송신기 역다중화기(도 4의 440)의 역과정을 수행하도록 설계된다.The multiplexing unit 1921

And outputs the estimated value of the interleaved codeword using the selection signal output from the selection signal generation unit 1922. [ The selection signal generating unit 1921 determines which sub-stream the respective bit values of the estimated values of the interleaved codeword are to be taken from. The selection signal generation unit 1922 is designed to read the value stored in the memory, generate a signal having a predetermined rule, output a selection signal, and perform an inverse process of the transmitter demultiplexer (440 of FIG. 4).

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

Claims (20)

A signal mapping method in a signal transmission apparatus of a system using a Low Density Parity Check (LDPC) code,
Storing LDPC codeword bits in a column direction;
Outputting the stored LDPC codeword bits in a row direction;
Generating sub-streams by demultiplexing the output bits using a de-multiplexing scheme;
And mapping bits included in each of the lower streams to symbols in a signal constellation,
Wherein the demultiplexing scheme is determined according to a modulation scheme used in the signal transmission apparatus, a length of the LDPC codeword, and a number of the lower streams.
2. The method of claim 1,
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = 12). When the output bits v0 to v11 are assigned to the twelve lower streams b0 to b11, v0 to b4, v1 to b2, v2 to b0, v3 to b5, v4 to b6 , assigning v5 to b1, v6 to b3, v7 to b7, v8 to b8, v9 to b9, v10 to b10, and v11 to b11. Mapping method.
2. The method of claim 1,
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = 12). When the output bits v0 to v11 are assigned to the twelve lower streams b0 to b11, v0 to b4, v1 to b0, v2 to b1, v3 to b6, v4 to b2 , assigning v5 to b3, v6 to b5, v7 to b8, v8 to b7, v9 to b10, v10 to b9, and v11 to b11. Mapping method.
2. The method of claim 1,
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = 8). When the output bits v0 to v7 are assigned to the eight lower streams b0 to b7, v0 to b4, v1 to b0, v2 to b1, v3 to b2, v4 to b5 , assigning v5 to b3, assigning v6 to b6, and v7 to b7.
2. The method of claim 1,
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = 8). When the output bits v0 to v7 are assigned to the eight lower streams b0 to b7, v0 to b4, v1 to b0, v2 to b5, v3 to b1, v4 to b2 , assigning v5 to b3, assigning v6 to b6, and v7 to b7.
A signal transmitting apparatus of a system using a Low Density Parity Check (LDPC) code,
An interleaver for storing LDPC codeword bits in a column direction and outputting the stored LDPC codeword bits in a row direction;
A demultiplexer for generating sub-streams by demultiplexing the output bits using a de-multiplexing scheme;
And a symbol mapper for mapping bits included in each of the lower streams into symbols in a signal constellation,
Wherein the demultiplexing scheme is determined according to a modulation scheme used in the signal transmission apparatus, a length of the LDPC codeword, and a number of the lower streams.
7. The demultiplexer according to claim 6,
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = 12). When the output bits v0 to v11 are assigned to the twelve lower streams b0 to b11, v0 to b4, v1 to b2, v2 to b0, v3 to b5, v4 to b6 , v5 to b1, v6 to b3, v7 to b7, v8 to b8, v9 to b9, v10 to b10, and v11 to b11.
7. The demultiplexer according to claim 6,
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = 12). When the output bits v0 to v11 are assigned to the twelve lower streams b0 to b11, v0 to b4, v1 to b0, v2 to b1, v3 to b6, v4 to b2 , v5 to b3, v6 to b5, v7 to b8, v8 to b7, v9 to b10, v10 to b9, and v11 to b11.
7. The demultiplexer according to claim 6,
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = 8). When the output bits v0 to v7 are assigned to the eight lower streams b0 to b7, v0 to b4, v1 to b0, v2 to b1, v3 to b2, v4 to b5 , v5 to b3, v6 to b6, and v7 to b7.
7. The demultiplexer according to claim 6,
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = 8). When the output bits v0 to v7 are assigned to the eight lower streams b0 to b7, v0 to b4, v1 to b0, v2 to b5, v3 to b1, v4 to b2 , v5 to b3, v6 to b6, and v7 to b7.
A signal demapping method in a signal receiving apparatus of a system using a Low Density Parity Check (LDPC) code,
Multiplexing sub-streams using a multiplexing scheme;
Deinterleaving the multiplexed bits;
And performing LDPC decoding on the inversely interleaved bits to generate LDPC codeword bits,
The multiplexing scheme is determined in accordance with a demultiplexing scheme used in a signal transmission apparatus, and the demultiplexing scheme is determined by a modulation scheme used in the signal transmission apparatus, a length of an LDPC codeword, And the signal demapping method of the signal receiving apparatus.
12. The method of claim 11, wherein the multiplexing comprises:
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = B0 to v1, b1 to v5, b2 to v1, b3 to v6, and b4 to v0 in the case of allocating the twelve lower streams b0 to b11 to the multiplexed bits v0 to v11 , assigning b5 to v3, b6 to v4, b7 to v7, b8 to v8, b9 to v9, b10 to v10, and b11 to v11 Demapping method.
12. The method of claim 11, wherein the multiplexing comprises:
Wherein the modulation scheme is a 64-QAM (Quadrature Amplitude Modulation) modulation scheme, the _{LD_Cd codelength} N _ldpc is 16200 (N _ldpc = 16200), the number N _substreams of the lower streams is 12 (N _substreams = 12) and b0 to b11 that are the twelve lower streams are assigned to the multiplexed bits v0 to v11, b0 to v1, b1 to v2, b2 to v4, b3 to v5, b4 to v0 , Assigning b5 to v6, b6 to v3, b7 to v8, b8 to v7, b9 to v10, b10 to v9, and b11 to v11 / RTI >
12. The method of claim 11, wherein the multiplexing comprises:
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = B0 to v2, b2 to v3, b3 to v5, and b4 to v0 in the case of assigning the eight lower streams b0 to b7 to the multiplexed bits v0 to v7 , assigning b5 to v4, b6 to v6, and b7 to v7.
12. The method of claim 11, wherein the multiplexing comprises:
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), N _substreams of the number of the lower streams are 8 (N _substreams = 8). When b0 to b7, which are the eight lower streams, are assigned to the multiplexed bits v0 to v7, b0 to v1, b1 to v3, b2 to v4, b3 to v5, b4 to v0 And assigning b5 to v2, b6 to v6, and b7 to v7. The signal demapping method of claim 1,
A signal receiving apparatus of a system using a Low Density Parity Check (LDPC) code,
A multiplexer for multiplexing sub-streams using a multiplexing scheme,
A deinterleaver for deinterleaving the multiplexed bits,
And an LDPC decoder for performing LDPC decoding on the inversely interleaved bits to generate LDPC codeword bits,
The multiplexing scheme is determined in accordance with a demultiplexing scheme used in a signal transmission apparatus, and the demultiplexing scheme is determined by a modulation scheme used in the signal transmission apparatus, a length of an LDPC codeword, Is determined.
17. The apparatus of claim 16,
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = B0 to v1, b1 to v5, b2 to v1, b3 to v6, and b4 to v0 in the case of allocating the twelve lower streams b0 to b11 to the multiplexed bits v0 to v11 , b5 to v3, b6 to v4, b7 to v7, b8 to v8, b9 to v9, b10 to v10, and b11 to v11.
17. The apparatus of claim 16,
Wherein the modulation scheme is a quadrature amplitude modulation (64-QAM) modulation scheme, the length N _LDPc of the LDPC codeword is 16200 (N _ldpc = 16200), the number N _substreams of the lower stream is 12 (N _substreams = B0 to v1, b1 to v2, b2 to v4, b3 to v5, and b4 to v0 in the case of allocating the twelve lower streams b0 to b11 to the multiplexed bits v0 to v11 , b5 to v6, b6 to v3, b7 to v8, b8 to v7, b9 to v10, b10 to v9, and b11 to v11.
17. The apparatus of claim 16,
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = B0 to v2, b2 to v3, b3 to v5, and b4 to v0 in the case of assigning the eight lower streams b0 to b7 to the multiplexed bits v0 to v7 , b5 to v4, b6 to v6, and b7 to v7.
17. The apparatus of claim 16,
Wherein the modulation scheme is a quadrature amplitude modulation (256-QAM) modulation scheme, the N _LDPSc length of the LDPC codeword is 16200 (N _ldpc = 16,200), the number N _substreams of the lower stream is 8 (N _substreams = B0 to v3, b2 to v4, b3 to v5, and b4 to v0 in the case of assigning the eight lower streams b0 to b7 to the multiplexed bits v0 to v7 , b5 to v2, b6 to v6, and b7 to v7.

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