KR101763597B1 - Broadcast receiver and data processing method thereof - Google Patents

Abstract

According to an aspect of the present invention, there is provided a broadcast signal receiver including: a demodulator for receiving and demodulating a broadcast signal; A parser for outputting data included in the broadcast signal; And a FEC decoder for decoding data included in the broadcast signal to correct an error, wherein the FEC decoder includes a BCH decoder for BCH decoding the data.
In the broadcast signal receiver according to an embodiment of the present invention, the FEC decoder further includes an inner decoder for inner decoding the data and outputting LLR values, wherein the BCH decoder is a BCH decoder having an error correction capability of 1, Code, and can correct errors of a plurality of bits using the LLR values.

Description

TECHNICAL FIELD [0001] The present invention relates to a broadcast receiver and a data processing method for a broadcast receiver,

The present invention relates to a broadcast receiver, and more particularly, to a broadcast receiver and a data processing method for processing data to more effectively correct an error generated in a transmission and reception process by receiving a broadcast signal.

Various techniques for transmitting and receiving digital broadcasting signals have been developed as the time for stopping transmission of an analog broadcasting signal approaches. A digital broadcast signal can transmit a large amount of video / audio data in comparison with an analog broadcast signal, and can include various additional data in addition to video / audio data.

The digital broadcasting system can provide HD (High Definition) video, multi-channel sound, and various additional services. However, the data transmission efficiency for high capacity data transmission, the robustness of the transmission and reception networks, and the flexibility of the network considering the mobile reception equipment are still problems to be improved.

Particularly, since the broadcasting signal communication of the digital broadcasting system is switched from one direction to the other and both reception of indoors as well as reception of a mobile device are considered, an error correction method occurring in the communication process becomes more important.

The present invention proposes a data processing method capable of correcting errors generated in a communication process in a broadcast receiver to solve the above-described technical problems.

That is, in the present invention, a BCH decoder capable of correcting one error and a decoding method thereof are improved.

Also, in the BCH decoder and decoding method, a method of correcting a plurality of errors and reducing the load on the system performance as much as possible is proposed.

According to an aspect of the present invention, there is provided a broadcast signal receiver including: a demodulator for receiving and demodulating a broadcast signal; A parser for outputting data included in the broadcast signal; And a FEC decoder for decoding data included in the broadcast signal to correct an error, wherein the FEC decoder includes a BCH decoder for BCH decoding the data.

In the broadcast signal receiver according to an embodiment of the present invention, the FEC decoder further includes an inner decoder for inner decoding the data and outputting LLR values, wherein the BCH decoder is a BCH decoder having an error correction capability of 1, Code, and can correct errors of a plurality of bits using the LLR values.

According to another aspect of the present invention, there is provided a method of processing data in a broadcast signal receiver, the method comprising: receiving and demodulating a broadcast signal; Outputting data included in the broadcast signal; And decoding the data included in the broadcast signal to correct an error, wherein the error correction step includes a BCH decoding step of BCH decoding the data to correct an error.

In the data processing method of a broadcast signal receiver according to an embodiment of the present invention, the error correction step further includes an inner decoding step of inner decoding the data and outputting LLR values, A BCH code having an error correction capability of 1 is used, and errors of a plurality of bits can be corrected using the LLR values.

According to the present invention, a broadcast receiver can effectively correct an error occurring in data during transmission and reception of a broadcast signal.

In particular, by using the BCH decoder according to an embodiment of the present invention, it is possible to correct a plurality of errors contained in data, that is, a codeword. In other words, it is possible to correct two or more errors while using a BCH code capable of correcting at most one error per one code block in the existing hard-decision decoding method.

Also, in the BCH decoding process of the BCH decoder, a predetermined number of data groups are selected and BCH decoding is performed, so that the system performance load due to a plurality of error corrections can be minimized.

The BCH decoder of the present invention is connected to an inner decoder of a soft in / soft out type such as a turbo decoder using a turbo code or the like so that the LLR value of the LDPC decoder, which is the output of the inner decoder, It is possible to obtain excellent error correction performance while minimizing the hardware change of the existing FEC decoder.

The BCH decoder of the present invention is connected to an inner decoder of a soft in / soft out method using an LDPC code or a turbo code. When using the BCH decoder, the BCH decoder uses the LLR value, which is the output of the inner decoder, Decoding method is improved and used, it is possible to obtain an excellent error correction performance while minimizing the hardware change of the existing FEC decoder.

1 is a block diagram of a broadcast transmitter according to an embodiment of the present invention.
2 is a diagram illustrating a structure of a BCH code according to an embodiment of the present invention.
3 is a diagram illustrating a method of error correction of a codeword according to an embodiment of the present invention.
4 shows a simulation environment for measuring the performance of a BCH decoder according to an embodiment of the present invention.
5 is a bit error rate (BER) graph illustrating the performance of a BCH decoder according to an embodiment of the present invention.
6 is a frame error rate (FER) graph illustrating the performance of a BCH decoder according to an embodiment of the present invention.
7 is a diagram illustrating a BCH decoding method according to another embodiment of the present invention.
8 is a BER graph illustrating performance of the BCH decoding method according to another embodiment of the present invention.
9 is a graph showing FER graphs illustrating performance of a BCH decoding method according to another embodiment of the present invention.
10 is a table showing the Eb / No gain according to the number of search points in the BCH decoding method according to another embodiment of the present invention.
11 is a diagram illustrating a broadcast receiver according to an embodiment of the present invention.
12 is a diagram illustrating a data processing method of a broadcast receiver according to an embodiment of the present invention.

As used herein, terms used in the present invention are selected from general terms that are widely used in the present invention while taking into account the functions of the present invention. However, these terms may vary depending on the intention of a person skilled in the art, custom or the emergence of new technology. Also, in certain cases, there may be a term selected arbitrarily by the applicant, and in this case, the meaning thereof will be described in the description part of the corresponding invention. Therefore, it is intended that the terminology used herein should be interpreted relative to the meaning of the term rather than to the nomenclature of the term, and the entire content of the specification.

In the case of a digital broadcasting system, broadcasting signals transmitted and received are digitized and transmitted, and thus a large amount of data can be transmitted and received. In addition, in the case of a digital broadcasting system, it is possible to correct an error according to a transmission / reception channel by using various coding / decoding methods, unlike the case of transmitting and receiving analog signals. Hereinafter, such error coding / decoding method may be referred to as FEC (Forward Error Correction) encoding / decoding. However, in the case of error coding / decoding, additional data is added in the process of encoding transmission data, which may degrade data transmission efficiency. When a complicated algorithm is used in data decoding at the receiving end, It may lead to an increase in the cost of constructing the receiving system. Therefore, an error correction method that improves the error correction performance and reduces the load on the overall broadcasting system is a very important issue in the digital broadcasting system. Therefore, the present invention proposes an error correction method capable of improving the error correction performance without adding additional data to the transmission / reception data, that is, without decreasing the data transmission efficiency, and without imposing additional load on the reception system.

Hereinafter, a broadcast receiver represents an electronic device capable of receiving and processing a broadcast signal, and a digital broadcast receiver is an electronic device capable of receiving and processing a broadcast signal, and a digital TV, a PDA, a mobile phone, Various types of fixed and mobile electronic devices.

1 is a block diagram of a broadcast transmitter according to an embodiment of the present invention.

The broadcast transmitter 1010 of FIG. 1 includes an FEC encoder 1020, a formatter 1030, and a modulator 1040.

The FEC encoder 1020 performs coding for error correction on the data to be transmitted. In this case, the FEC encoder 1020 may include an outer encoder for performing outer coding and an inner coder for performing inner coding. In the following embodiments, outer code can use BCH code (Bose-Chaudhuri-Hocquengem error correction binary block code) and inner code used in inner encoding can use LDPC code (Low Density Parity Check code) . In one embodiment, the FEC encoder is configured to concatenate the BCH coding scheme with the three rate LDPC coding schemes of (7493,4572) and (7493,6096) and the rate of (762,752) Can be used.

A formatter 1030 configures the FEC encoded data in a transmission format. In one embodiment, the formatter 1020 may format data in transmission units such as transmission frames, packets, or signal blocks.

A modulator 1040 modulates the formatted data into a broadcast signal and transmits the modulated data. In one embodiment, the modulator may perform Orthogonal Frequency Division Multiplexing (OFDM) modulation or VSB (Vestigial Side Band) modulation.

The receiver receiving the transmitted broadcast signal performs FEC decoding to correct errors contained in the data. FEC decoding performs an inverse process of FEC encoding described above, and can perform LDPC decoding and BCH decoding. The above-mentioned (762,752) rate BCH coding method corrects errors through hard decoding, so that only error correction of a maximum of 1 bit per BCH block is possible. Therefore, a method of improving the coding gain using the reliability of bits will be described below.

2 is a diagram illustrating a structure of a BCH code according to an embodiment of the present invention.

FIG. 2 shows the structure of a code word generated by (762, 752) shortened BCH coding.

In one embodiment of the present invention, the BCH code may be generated using a code generation polynomial of G _BCH (x) = 1 + x ³ + x ¹⁰ , with a shortened BCH code of (762,752) t = . As shown in FIG. 2, when shortened, 261 zero bits are padded in front of message bits of 752 bits and then 10 parity bits are added to the BCHs 1023 and 1013, , Indicating that only 762 bits are transmitted except 261 padded bits. The message bit means a bit representing data to be transmitted.

The codeword of FIG. 2 can be expressed by Equation (1) below. However, the operation of the mathematical expression representing the codeword in the following equation expresses the operation of the Galois field. That is, in the equation representing the codeword, the addition operation can represent the XOR operation by the addition operation of the Galois field.

In Equation (1), the portion c ₇₆₂ to c ₁₀₂₂ can be eliminated because it is a zero padded portion as shown in FIG. 2, and a code word from which a zero padded portion is removed can be expressed by Equation (2) below.

In Equation (2), the value of each coefficient c _i (i = 0, 1, ..., 761) of the polynomial representing the codeword is a binary value of 0 or 1, the c ₀ to c ₉ portion is a parity portion, The c ₁₀ through c ₇₆₁ parts represent the message part, respectively. In other words, Equation 2 represents a 762-bit codeword in which zero padding is removed and transmitted in the codeword of FIG.

A codeword such as Equation ( ² ) has a property of c (a ¹ ) = c (a ² ) = 0. Where a ¹ and a ² are the elements of the Galois field 1024 and all operations (addition, subtraction, exponentiation) in the equations of c (a ¹ ) and c (a ² ) Lt; RTI ID = 0.0 > 1024 < / RTI > a ¹ and a ² may also be referred to as primary elements of a Galois Field.

When a codeword such as Equation 2 is transmitted, the codeword is received through the channel. At this time, the channel is assumed to have noise, and this noise can be expressed by an error polynomial e (x). Therefore, the signal received through the noise, that is, the received codeword can be expressed by Equation (3) below.

As shown in Equation (3), the received codeword can be represented by adding the codeword c (x) to be transmitted and the error e (x) generated in the channel. In Equation (3), each coefficient r _i , e _i (i = 0,1, ..., 761) has a binary value of 0 or 1 as described above. Then, if a ¹ and a ² are substituted for x in the equation (3), r (x) can be expressed by the following equation (4).

As shown in Equation (4), r (a ² ) can be expressed in the same manner as the equation for r (a). Therefore, in the following description, r (a) is used and the equation r (a) is referred to as syndrome S ₁ (= r (a ¹ )). In the syndrome S ₁ , when there is no error, e (x) becomes zero, so that S ₁ = 0. However, when there is an error, S ₁ = e (a) is not zero, and in this case, the syndrome S ₁ can be expressed by the following equation (5).

Equation (5) can be referred to as a syndrome equation. The syndrome equation of Equation (5) has a unique solution only when only one value is 1 in the coefficients e _i (i = 0,1, ..., 761) and when all of the other values are 0, that is, when the number of errors is 1 bit . However, when the number of error bits is two or more, there are a plurality of solutions, so error correction is impossible by solving the syndrome equation. The syndrome equation according to the number of bits in which the error occurs can be expressed by Equation (6).

Equation (6) represents the case where the number of bits in which an error occurs is one to four.

In one embodiment of the present invention, a BCH decoder using a hard decision value assumes a single error and obtains a solution of S ₁ = e _i a ⁱ . That is, it is determined that an error has occurred in the bit at the position a ⁱ using the exponent of the syndrome S ₁ , and the bit of the position is toggled. In other words, BCH decoder determines that an error has occurred in the position of the index of the syndrome S _1, an error of 1 to obtain a solution to the syndrome equations, if an individual, a coefficient from the obtained year 1 in equation (6), the bit at the location If the value of the toggle bit is 1, it is switched to 0 and if it is 0, it is switched to 1.

However, when there are two or more errors in the BCH decoder using such a hard decision value, a problem occurs. If there are two or more errors, you can think of two cases. First, the syndrome of the error is a case where the exponent sections have 762 or more of S _1. In this case, the BCH decoder knows that the exponent portion of S ₁ indicates a zero padding portion, and the zero padding portion knows that all bit values are 0, so that an error occurrence or decoding failure can be recognized. However, the second problem arises when the exponent part of the syndrome S ₁ in which the error occurs has a value between 0 and 761. That is, in this case, since the BCH decoder determines that an error has occurred in one bit at a completely different position than the position of the two bits in which the actual error occurs, the error can not be corrected, There is a problem that can be caused. Therefore, if two or more errors occur in a BCH block, that is, a code word, error correction is impossible, and the error correction performance is deteriorated.

Therefore, a decoding method of a BCH decoder capable of solving such a problem and improving error correction performance will be described below.

In the case of the FEC decoder, since the data is processed in the reverse order of the FEC encoder of FIG. 1, when the LDPC decoder and the BCH decoder are included, the LDPC decoder is positioned at the front end of the BCH decoder. The LDPC decoder may output a soft decision value instead of a hard decision value, and the soft decision value represents probability information represented by reliability. Therefore, in the following embodiments, a BCH decoder that performs error correction, i.e., BCH decoding, using the soft decision value output from the LDPC decoder will be described.

The soft decision value output from the LDPC decoder indicates reliability and can be expressed by Equation (7) below.

Equation (7) represents the reliability of the LDPC decoded data, that is, a log-likelihood ratio (LLR) value, and represents a value obtained by dividing the probability that the bit at the i-th position of the received data is zero by the probability of one day. If the LLR value is a positive number, it indicates the probability of 1 day; As the absolute value increases, the probability that the corresponding bit is 1 or 0 is high, indicating that the reliability is high. The closer the absolute value is to 0, the lower the reliability and the higher the probability that an error occurs in the bit. The LLR _i value in Equation (7) represents a value corresponding to the position of a ⁱ .

라고 지칭하도록 한다.The codeword ideally corrected by the BCH decoder must satisfy the following two conditions. Hereinafter, the corrected syndrome (or syndrome equation) of the codeword

Quot;

= 0One)

= 0

2) The corrected codeword should have maximum reliability.

Condition 1) indicates that the corrected codeword is valid, i.e., the syndrome of the corrected codeword should be zero. Condition 2) means that the error should be corrected to the most probable data among the codewords before the error is added in the received codeword. That is, the corrected codeword is corrected to the data with the highest probability close to the codeword before the error is corrected.

및 |LLR| 값은 이하의 수학식 8 및 수학식 9와 같이 표현할 수 있다.For example, when correcting n bits at positions a ^L1 , a ^L2 , ~, a ^{Ln (} where _0? L _i? 761), the corrected syndrome of the codeword

And | LLR | The values can be expressed by the following equations (8) and (9).

에 대한 수식은 상술한 바와 같이 갈로아 필드(1024)에서 정의되는 연산을 사용하며, aⁱ는 갈로아 필드(1024)의 엘러먼트이다. 수학식 8에서, L₁~L_n은 n개의 에러를 정정하는 경우 정정하는 위치를 나타낸다. The syndrome of the corrected codeword of Equation (8)

Is an element of the Galois field 1024, where a ⁱ is an operation defined in the Galois field 1024 as described above. In Equation (8), L ₁ to L _n denote correction positions when correcting n errors.

The operations in the equations for REL _BLK in mathematical expression 9 represent general operations in the real area. The LLR value (REL _BLK ) in Equation (9) is calculated by subtracting the sum of the LLRs of the corrected portion from the sum of the LLRs of the uncorrected portion in the received code word. That is, when n pieces of data are corrected, the sum is the value obtained by subtracting the sum of n LLRs to be corrected from the sum of (762-n) LLRs that are not corrected.

이 최소가 되어야 한다. 이하에서 감산하는 부분

을 REL_ERR이라 지칭하기로 한다.In order to maximize the reliability of the corrected codeword as in the above-mentioned condition 2), the reliability value of Equation (9) becomes maximum. In Equation (9), in order for REL _BLK to be the maximum,

Should be the minimum. Hereinafter,

_Will be referred to as REL _ERR .

3 is a diagram illustrating a method of error correction of a codeword according to an embodiment of the present invention.

In FIG. 3, an error has occurred in bits a ⁰ and a ¹⁰ of the received codeword. BCH decoder using the above-described hard Decision Since error of one bit only correction is possible, because in spite of an error of 2 bits, and to loosen the syndrome equations (S ₁ = a ³⁾ is shown to a ^3, a ³ position As an error.

However, when using the LLR value in accordance with an embodiment of the invention, for a ³ position | LLR _ERR | | LLR _ERR | for two positions a ⁰ and a ¹⁰ than the value (| + 65 |). Since the value (| + 5 | + | -3 | = | 8 |) is smaller, it is possible for a ⁰ and a ¹⁰ to recognize the two bits as errors. Therefore, the BCH decoder according to the present invention can recognize and correct a plurality of errors.

Hereinafter, the performance of the BCH decoder of the present invention will be described.

4 shows a simulation environment for measuring the performance of a BCH decoder according to an embodiment of the present invention.

In the following performance measurements, only the BCH encoding / decoding was used in the simulation to exclude the influence of the inner code, such as LDPC encoding / decoding, in order to clearly show only the performance of the BCH decoder. BPSK (Binary Phase Shift Keying) is used for modulation, and the environment of the channel is conditioned by AWGN (Additive white Gaussian noise) channel. The AWGN channel represents a channel in which noise having the same probability exists for all frequency bands.

In other words, the performance of the BCH decoding will be described below when BCH encoded codeword is mapped and transmitted in the BPSK scheme, and the codeword received through the AWGN environment is BCH decoded using the LLR value.

5 is a bit error rate (BER) graph illustrating the performance of a BCH decoder according to an embodiment of the present invention.

In FIG. 5, the abscissa represents the ratio of bit energy to Eb / No (energy per bit to noise spectral density ratio), that is, the noise power density, and the ordinate represents the bit error ratio (BER). In FIG. 5, 1) a case where BCH coding / encoding is not performed (hard decision), 2) a conventional hard decoding using a hard decision value, 3) a soft decision value is used, A BCH decoder for correcting errors by considering errors of up to three bits while using a soft decision value; (BER) performance of soft decoding with considering maximum 3 errors.

In FIG. 5, 3) has a signal-to-noise ratio (SNR) gain of 0.6 dB based on 10 ^-4 BER compared with BCH decoding using a hard decision value, and 4) It can be seen that there is a gain.

6 is a frame error rate (FER) graph illustrating the performance of a BCH decoder according to an embodiment of the present invention.

In FIG. 6, the horizontal axis represents the ratio of bit energy to Eb / No (energy per bit to noise spectral density ratio), that is, the noise power density, and the vertical axis represents FER (Frame Error Ratio). In FIG. 6, 1) a case where a BCH coding / encoding is not performed (hard decision), 2) a case of a BCH decoder using a hard decision value (conventional hard decoding), 3) A BCH decoder for correcting errors by considering errors of up to three bits while using a soft decision value; (BER) performance of soft decoding with considering maximum 3 errors.

In FIG. 6, 3) has a signal-to-noise ratio (SNR) gain of 0.9 dB based on 10 ^-4 FER compared to BCH decoding using a hard decision value, and 4) It can be seen that there is a gain.

=0 을 만족하는 모든 위치를 검색하고, 이 위치에서 |LLR_ERR| 값을 계산하여 최소값을 검색하는 방법은 검색해야하는 비트의 위치 즉 검색 지점이 매우 많아지므로, 계산량에 대한 부하가 예상된다. 즉, 752개의 비트로 구성된 코드워드에서 임의의 모든 검색 지점에 대하여 검색이 가능하므로, 2개의 에러 또는 3개의 에러를 검색하는데 수백 개 이상의 검색 지점에 대해 연산을 수행해야 할 수 있기 때문이다. 따라서, 이하에서는 이러한 계산량에 따른 시스템의 성능 저하를 피하면서, 에러 정정 성능을 유지할 수 있는 BCH 디코딩 방법을 제안한다.
However,

= 0, and at this position, all the positions that satisfy | LLR _ERR | The method of calculating a value and searching for a minimum value is a load on a calculation amount since a position of a bit to be searched, that is, a search point, becomes very large. That is, since it is possible to search for any arbitrary search point in a code word composed of 752 bits, it is necessary to perform an operation on several hundred search points to search for two errors or three errors. Therefore, a BCH decoding method capable of maintaining the error correction performance while avoiding the performance degradation of the system according to the amount of calculation is proposed below.

7 is a diagram illustrating a BCH decoding method according to another embodiment of the present invention.

The BCH decoding method of FIG. 7 is characterized in that a range to be calculated is grouped and a candidate set is used in order to reduce the amount of calculation, while using the above-described BCH decoding method using the LLR value .

In the BCH decoding method according to the embodiment of the present invention, the BCH decoder constructs a candidate set prior to searching for a minimum REL _ERR . The candidate set includes 762 bits | LLR | Lt; RTI ID = 0.0 > K < / RTI > That is, it includes K bits having the highest probability of occurrence of an error. Here, K can be set according to the performance of the system, and may be set to a value of 3 to 7 as an example.

=0 을 만족하는 모든 해(solution)에 대해 최소 REL_ERR을 검색하는 대신, 다음과 같이 검색을 수행한다. 즉, K개의 비트들을 포함하는 후보 세트에서 (n-1)개의 위치를 선정하고, 나머지 한개는

의 수식을 계산하여 LLR 값들이 저장된 메모리로부터 불러온다. 여기서 LLR 값들이 저장된 LLR 메모리는, 총 762개의 |LLR_i| 값들을 포함한다. 도 7에서, a^m이 LLR 메모리로부터 읽어온 LLR 값에 해당한다. 그리고 2개 비트 에러 정정시 aⁱ, 3개 비트 에러 정정시 aⁱ 및 a^j, 4개 비트 에러 정정시 aⁱ, a^j 및 a^k는 모두 후보 세트로부터 읽어온 값들이다. 다만, 후보 세트에서 읽어오는 값들의 지수는 모두 다른 수이어야 하고, 다시 말하면 0~761의 범위에서 각기 다른 위치를 갖는 값들이어야 한다.The BCH decoder is used for error correction of n bits

Instead of searching for the minimum REL _ERR for all solutions that satisfy = 0, the search is performed as follows. That is, (n-1) positions are selected in the candidate set including K bits, and the other

And the LLR values are retrieved from the stored memory. Here, the LLR memory in which the LLR values are stored is 762 total | LLR _i | Lt; / RTI > In Fig. 7, a ^m corresponds to the LLR value read from the LLR memory. And 2-bit error correction when a ^i, 3 bits error-correction when a ⁱ and a ^j, 4 bits error-correction when a ^i, a ^j and a ^k are all values read from the candidate set. However, the exponents of the values read from the candidate set must all be different numbers, that is, values having different positions in the range of 0 to 761.

수식을 산출하여 LLR 메모리에서 선정하여 LLR_ERR 값이 최소가 되는 조합을 검출한다. 다시 말하면, LLR 메모리에서 선정하는 1개는, 정정된 코드워드의 신드롬 방정식(수학식 8)을 연산하여 결정된다. 이 경우 후보 세트에는 K개의 비트의 검색 지점이 포함되므로, BCH 디코더가 연산해야 하는 검색 지점의 조합의 수는 _KC_{n -1}개가 된다. 따라서 ₇₅₂C_n개의 조합을 연산해야하는 전술한 실시예에 비해 시스템이 수행해야하는 연산량의 부하가 현저히 줄어들게 된다.
In other words, as described with reference to FIG. 3, the BCH decoder finds a bit in which the LLR _ERR is minimum, and if the number of errors correcting the position of the target bit is n, n-1 is a candidate having a minimum LLR value In the set, one

The formula is calculated and selected in the LLR memory to detect the combination that minimizes the LLR _ERR value. In other words, one selected in the LLR memory is determined by computing the syndrome equation of the corrected codeword (equation (8)). In this case, since the candidate set includes K bit search points, the number of combinations of search points that the BCH decoder has to operate is _K C _{n -1} . Therefore, the load of the calculation amount to be performed by the system is significantly reduced as compared with the above-described embodiment in which ₇₅₂ C _n combinations are to be calculated.

8 is a BER graph illustrating performance of the BCH decoding method according to another embodiment of the present invention.

In FIG. 8, the abscissa represents the ratio of bit energy to Eb / No (energy per bit to noise spectral density ratio), that is, the noise power density, and the ordinate represents a bit error ratio (BER). In FIG. 8, 1) a case where BCH coding / encoding is not performed (hard decision), 2) a case of a BCH decoder using a hard decision value (conventional hard decoding), 3) (2-bit error correction) for correcting errors by considering errors of bits, and 4) for a BCH decoder that corrects errors by considering errors of up to three bits while using soft decision values ( 3-bit error correction, and 5) BER performance of a 4-bit error correction for a BCH decoder that corrects errors by considering errors of up to four bits while using a soft decision value.

=0를 만족하는 모든 지점에 대해 검색한 도 5의 결과에 비해 Eb/No의 성능 감소가 약 0.1dB밖에 나타나지 않는 것을 알 수 있다.
As shown in FIG. 8, although the number of search points is significantly reduced,

= 0, the performance degradation of Eb / No is only about 0.1 dB compared to the result of FIG.

9 is a graph showing FER graphs illustrating performance of a BCH decoding method according to another embodiment of the present invention.

In FIG. 9, the axis of abscissas represents the ratio of bit energy to Eb / No (energy per bit to noise spectral density ratio), that is, the noise power density, and the vertical axis represents FER (Frame Error Ratio). In FIG. 9, 1) hard decision in case of BCH coding / encoding, 2) conventional hard decoding in case of BCH decoder using hard decision value, 3) use of soft decision value, (2-bit error correction) for correcting errors by considering errors of bits, and 4) for a BCH decoder that corrects errors by considering errors of up to three bits while using soft decision values ( 3-bit error correction, and 5) a 4-bit error correction for a BCH decoder that corrects errors by considering errors of up to four bits while using soft decision values.

=0를 만족하는 모든 지점에 대해 검색한 도 6의 결과에 비해 Eb/No의 성능 감소가 약 0.1dB밖에 나타나지 않는 것을 알 수 있다.
As shown in Fig. 9, although the number of search points is significantly reduced,

= 0, the performance degradation of Eb / No is only about 0.1 dB compared with the result of FIG.

10 is a table showing the Eb / No gain according to the number of search points in the BCH decoding method according to another embodiment of the present invention.

10 shows a case of a BCH decoding method using a candidate set with K = 5. As shown in FIG. 10, the number of search points is 5 in case of 2-bit correction, 10 in case of 3-bit correction, and 10 in case of 4-bit correction. However, in the case of the error correction performance, the error correction performance is almost maintained even though the computation amount is significantly reduced compared to the one shown in FIG. 6 at + 0.9dB for the 2-bit error correction and +0.5dB for the 3-bit error correction Able to know. However, as the number of error correction increases, the additional gain decreases. However, when K = 5 is fixed, an additional gain can be obtained by increasing the number of K as the number of error correction increases.

11 is a diagram illustrating a broadcast receiver according to an embodiment of the present invention.

11, the broadcast receiver 11010 includes a demodulator 11020, a parser 11030 and an FEC decoder 11040. The FEC decoder 11040 includes an inner decoder 11050 and an outer decoder 11060 do.

The demodulator 11020 receives and demodulates the broadcast signal. In one embodiment, the demodulator 11020 may receive a broadcast signal and perform OFDM (Orthogonal Frequency Division Multiplexing) demodulation or VSB (Vestigial Side Band) demodulation.

The parser 11030 can parse the structure of the frame included in the broadcast signal and output desired data. For example, the parser 1103 can output the data by parsing a broadcast signal composed of units such as a transmission frame, a packet, or a signal block.

The FEC decoder 11040 performs decoding for error correction on the received data. FEC decoder 11040 can perform the inverse operation of the FEC encoder as described above. Accordingly, the FEC decoder 11040 may include an inner decoder 11050 that performs inner decoding on inner coding, and an outer decoder 11060 that performs outer decoding on outer coding. In the embodiment of FIG. 11, the LDPC decoder 11050 corresponds to the inner decoder and the BCH decoder 11060 corresponds to the outer decoder.

The broadcast receiver 11010 as shown in FIG. 11 performs FEC decoding to correct errors included in the received data. In particular, in FIG. 11, the BCH decoder 11060 performs BCH decoding using the soft decision value output from the LDPC decoder 11050. The description of the BCH decoding operation of the BCH decoder is the same as that described with reference to FIG. 2 to FIG.

In the broadcast receiver of FIG. 11, the inner decoder 11050 is described as an LDPC decoder. However, as described above, since the BCH decoder of the FEC decoder of the present invention uses the LLR output, various types of decoders for outputting LLR values can be used together with the BCH decoder. In other words, in FIG. 11, the inner decoder may be a decoder using a Turbo code, a soft output Viterbi algorithm, a BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm. As another embodiment, it is possible to use only the BCH decoder alone without using an inner decoder such as an LDPC decoder as the FEC decoder. In this case, as shown in FIG. 4, an LLR value may be calculated for the data received by the BCH decoder, and BCH decoding may be performed using the calculated LLR value as described above.

12 is a diagram illustrating a data processing method of a broadcast receiver according to an embodiment of the present invention.

The broadcast signal receiver receives and demodulates the broadcast signal (S12010). As described above, the broadcast signal receiver can perform OFDM demodulation or VSB demodulation on a broadcast signal using a demodulator.

The broadcast signal receiver parses the demodulated broadcast signal and outputs data included in the broadcast signal (S12020). The broadcast signal receiver can parse the structure of the broadcast signal using a parser and extract and output the data included in the broadcast signal according to the structure of the broadcast signal.

The broadcast signal receiver can FEC decode the parsed data and the FEC decoding step includes an inner LDPC decoding step S12030 and an outer BCH decoding step S12040 as follows.

The broadcast signal receiver performs inner (LDPC) decoding on the received data (S12030). The LDPC decoder of the broadcast signal receiver performs LDPC decoding, and the LDPC decoder can output the data as a hard decision value or soft decision value.

The broadcast signal receiver performs outer (BCH) decoding on the received data (S12040). The BCH decoder of the broadcast signal receiver receives the data decoded by the LDPC decoder and performs BCH decoding, and can use the hard decision value or the soft decision value as described above.

The decoding operation of the BCH decoder is the same as described above with reference to FIG. 2 and FIG. The BCH decoder of the present invention is characterized by performing BCH decoding using a soft decision value. In addition, BCH decoding is performed to correct a plurality of non-one errors. In this case, the BCH decoder performs error correction such that the corrected codeword has the maximum reliability, which means that error correction is performed such that the sum of the reliability of the bits to be corrected is at a minimum as described in connection with Equation (9) . That is, when correcting the n errors, the BCH decoder combines the bits included in the data so that the sum of the reliability of the n bits to be corrected is the smallest, calculates the sum of the reliability, and the combination of the bits with the smallest sum of the reliability The error is corrected by judging the combination of the errored bits. At this time, the BCH decoding can be performed in units of code words as shown in FIG. In one embodiment, the BCH decoder may perform the above-described BCH decoding on 752 units or 762 units of codewords including parity bits.

The BCH decoder can use the K candidate sets while using the soft decision value to calculate the reliability as described above. In other words, the BCH decoder can select a candidate set that includes K bits with the lowest reliability. And the n-1 bits can calculate the sum of the reliability for the _K candidate sets, one using the solution of the syndrome equation as shown in FIG. 7 for _K C _{n -1} combinations. In other words, the BCH decoder can perform error correction by extracting n-1 pieces from K candidate sets and one piece from 752 pieces of data, as described in FIG. 7, using their LLR values. In this case, the object to which the LLR values are compared is a total of n, including n-1 in the candidate set and one in the entire set (out of 752), where the n elements are obtained by subtracting the zero- 0 < / RTI > to 761 < th > bits, and all n elements are selected at different positions. The BCH decoder can determine that an error has occurred with respect to the combination in which the sum of the reliability is the smallest, and correct the error of the data by toggling the bit where the error occurs.

However, as described above, since the BCH decoder of the FEC decoder of the present invention uses the LLR output, various decoding schemes for outputting LLR values can be used. In other words, in step S12030 of Fig. 12, the broadcast receiver can decode the data using an inner decoder of another method of outputting the LLR value. Turbo codes, soft output Viterbi algorithms, BCJR (Bahl, Cocke, Jelinek and Raviv) algorithms can be used as the inner coding scheme. That is, step S12030 of FIG. 12 may be replaced with a step of inner decoding the data using at least one of the turbo code, soft output Viterbi algorithm, and BCJR algorithm to output LLR values. As another embodiment, the BCH decoder alone can be used without using an inner decoder such as an LDPC decoder. In other words, as shown in FIG. 4, the LLR value may be calculated for the data received by the BCH decoder and the BCH decoding may be performed using the calculated LLR value as described above. In such a case, step 12030 of FIG. 12 may be replaced by calculating the LLR value of the received data.

1010; Broadcasting transmitter
1020; FEC encoder
1030; Former
1040; Modulator
11010; Broadcasting receiver
11020; Demodulator
11030; Parser
11040; FEC decoder
11050; Inner decoder
11060; Outer decoder

Claims (13)

A demodulator for receiving and demodulating a broadcast signal;
A parser for outputting data included in the broadcast signal; And
And a FEC (Forward Error Correction) decoder for decoding data included in the broadcast signal to correct an error,
The FEC decoder includes:
A BCH (Bose-Chaudhuri-Hocquenghem) decoder for decoding the LDPC decoded data using an LDPC decoder for LDPC decoding the data and a log-likelihood ratio (LLR) value output from the LDPC decoder; Decoder,
Wherein the BCH decoder uses a BCH code having an error correction capability of 1 to correct errors for N bits when the BCH decoder determines that the absolute value of the LLR value is N-1 in the candidate set including K bits with the smallest absolute value Correcting an error by selecting the number of combinations,
Broadcast signal receiver.

delete delete delete delete The method according to claim 1,
Wherein the BCH decoder adds absolute values of the LLR values of the plurality of bits to a plurality of bits correcting the error and toggles a plurality of bits with the absolute value being the minimum. The method according to claim 1,
Detecting a combination in which the sum of the LLR values included in the candidate set and the absolute values of the LLR values included in the data is minimized using the LLR value included in the candidate set and the LLR value included in the data,
And corrects the plurality of errors corresponding to the LLR values at which the sum of the absolute values becomes minimum. Receiving and demodulating a broadcast signal;
Outputting data included in the broadcast signal; And
And decoding the data included in the broadcast signal to correct an error,
The error correction step includes:
Decoding the data by LDPC (Low Density Parity Check Code); And
And a BCH decoding step of BCH decoding the LDPC decoded data using an LLR (Log-Likelihood Ratio) value output from the LDPC decoding step to correct an error,
Wherein the BCH decoding step uses a BCH code having an error correction capability of 1 to correct errors in the N bits by performing a BCH decoding on the N-th bit in a candidate set including K bits with an absolute value of the LLR value being minimum, Correcting an error by selecting the number of one combination,
Data processing method.

delete delete delete 9. The method of claim 8,
Wherein the BCH decoding step adds absolute values of the LLR values of the plurality of bits to the plurality of bits and toggles the plurality of bits with the absolute value to the minimum to correct the error. 9. The method of claim 8,
Detecting a combination in which a sum of an LLR value included in the candidate set and an absolute value of an LLR value included in the data is minimized using an LLR value included in the candidate set and an LLR value included in the data,
And corrects errors of bits corresponding to LLR values at which the sum of the absolute values becomes minimum.

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