KR101761417B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including a timing controller for outputting data through a transmitter comparator; One or more source driver ICs for receiving data from the timing controller through a receiver stage comparator connected to the transmitter stage comparator via a data wire pair, converting the data to a data voltage and supplying the data voltage to the data lines of the display panel; First and second terminal resistors connected in series between the two input terminals of the receiving terminal comparator; And a switch element for connecting a node between the first and second terminal resistances to a base voltage source or a terminal voltage source.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is rapidly applied to a television, thereby rapidly replacing a cathode ray tube.

The liquid crystal display device includes a plurality of source drive integrated circuits (hereinafter referred to as "IC") for supplying data voltages to the data lines of the liquid crystal display panel, gate pulses (or scan pulses ), And a timing controller for controlling the drive ICs, and the like.

The timing controller supplies digital video data, a clock signal for sampling digital video data, a control signal for controlling the operation of the source drive ICs, and the like to the source drive ICs through an interface such as mini LVDS (Low Voltage Differential Signaling) do. The source driver ICs convert the digital video data serially inputted from the timing controller into a parallel system, and then convert the analog data voltage using the gamma compensation voltage and supply the analog data voltage to the data lines.

The timing controller supplies the necessary signals to the source drive ICs in a multi-drop scheme that applies clock and digital video data commonly to the source drive ICs. This data transfer scheme includes control wirings for controlling the R data transfer wiring, the G data transfer wiring, the B data transfer wiring, the output of the source drive ICs, and the operation timing of the polarity change operation between the timing controller and the source drive ICs, Many wires, including clock transmission wires, are needed.

The mini-LVDS interface method transmits RGB digital video data and clocks in pairs of differential signals. Therefore, when transmitting odd data and superior data simultaneously, there is a minimum 14 wires are required. If the RGB data is 10-bit data, 18 wires are required. Therefore, it is difficult to reduce the width of a source printed circuit board (PCB) mounted between the timing controller and the source drive ICs because many wires must be formed.

The applicant of the present application filed a Korean patent application for a new signal transmission protocol for minimizing the number of wires between the timing controller and the source drive ICs and stabilizing the signal transmission by connecting the timing controller and the source drive ICs in a point to point manner 10-2008-0127458 (2008-12-15), US application 12 / 543,996 (2009-08-19), Korean patent application 10-2008-0127456 (2008-12-15), US application 12 / 461,652 (2009- 08-19), Korean Patent Application No. 10-2008-0132466 (2008-12-23), and US Application No. 12 / 537,341 (2009-08-07).

The timing controller transmits data through a transmission stage comparator Tx as shown in FIGS. 1 and 2, and the source drive ICs receive data via a reception stage comparator Rx as shown in FIG. 1 or FIG. In Figures 1 and 2, EPI + and EPI- are the differential signal pair transmitted from the timing controller to the source drive ICs, and ZO is the wiring resistance. RT is the terminal resistance connected between the two wirings where the difference signal pair is transmitted in the receiving terminal comparator (Rx).

The receiver comparator Rx shown in FIG. 1 has lower power consumption than that of FIG.

In consideration of impedance matching, a receiving terminal comparator Rx of the type shown in FIG. 1 uses a terminal resistance of about 100? And a receiving terminal comparator Rx of the type shown in FIG. 2 uses a terminal resistance RT of about 50? use. Since the signal operation speed Speed is affected in inverse proportion to the resistance value of the terminal resistance RT, that is, the larger the resistance, the larger the signal attenuation. Therefore, the receiving signal characteristic is better in the receiving terminal comparator Rx of the type shown in FIG. . On the other hand, since VOD = I (current) x R (terminal resistance) in terms of the signal level (VOD), in order to obtain the same desired signal level, the receiving terminal comparator Rx A lot of current is needed.

The receiving terminal comparator Rx may be selected as a receiving terminal comparator Rx of the type shown in FIG. 1 or a receiving terminal comparison Rx of the type shown in FIG. 2 depending on the LCD application product. This receiver-end comparator (Rx) is not selected and shared with any one application.

The present invention provides a liquid crystal display device including a receiver stage comparator that can be used for various applications.

The liquid crystal display of the present invention includes: a timing controller for outputting data through a transmission stage comparator; One or more source driver ICs for receiving data from the timing controller through a receiver stage comparator connected to the transmitter stage comparator via a data wire pair, converting the data to a data voltage and supplying the data voltage to the data lines of the display panel; First and second terminal resistors connected in series between the two input terminals of the receiving terminal comparator; And a switch element for connecting a node between the first and second terminal resistances to a base voltage source or a terminal voltage source.

The present invention can easily convert the receiving terminal comparator to one of the terminals shown in FIG. 1 or 2 by connecting the switch to the node between the terminal resistors of the receiving terminal comparator, so that the receiving terminal comparator can be used for various applications.

1 is a circuit diagram showing an example of a transmitter stage comparator of a timing controller and a receiver stage comparator of a source drive IC.
2 is a circuit diagram showing another example of a transmitter-stage comparator of the timing controller and a receiver-stage comparator of the source drive IC.
3 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
4 is a diagram illustrating data and an external clock transmitted between the timing controller and the source drive IC shown in FIG.
5 is a diagram illustrating a receiver stage comparator according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

3, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel (LCP), a timing controller (TCON), one or more source drive ICs (SIC # 1 to SIC # 8) (GIC).

A liquid crystal layer is formed between the substrates of the liquid crystal display panel (LCP). The liquid crystal display panel LCP includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL.

The pixel array including the data lines DL, the gate lines GL, the TFTs, and the storage capacitor Cst is formed on the TFT array substrate of the liquid crystal display panel LCP. The liquid crystal cells Clc are driven by the electric field between the pixel electrode to which the data voltage is supplied through the TFT and the common electrode to which the common voltage Vcom is supplied. The gate electrode of the TFT is connected to the gate line GL, and the drain electrode thereof is connected to the data line DL. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the data voltage from the data line DL to the pixel electrode of the liquid crystal cell Clc. On the color filter substrate of the liquid crystal display panel (LCP), a black matrix, a color filter, a common electrode, and the like are formed. In each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel (LCP), an alignment film for attaching a polarizing plate and setting a pre-tilt angle of liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc may be formed between the TFT array substrate of the liquid crystal display panel LCP and the color filter array substrate.

The liquid crystal display panel (LCP) is a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode or a horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Can be implemented. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller TCON receives vertical / horizontal synchronization signals Vsync and Hsync from an external host system (not shown) via an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling Signal (Data Enable, DE), and a dot clock (CLK). The timing controller TCON is connected in series to each of the source drive ICs (SIC # 1 to SIC # 8) via a point-to-point interface.

The timing controller TCON generates the difference signal EPI + and EPI- from the external clock signal CLK and the RGB digital video data as shown in FIG. 4 and supplies the source drive ICs SIC # 1 to SIC # 8). Also, the timing controller TCON may generate control data as a pair of differential signals and transmit the control data to the source drive ICs (SIC # 1 to SIC # 8) through a pair of data wirings. The control data includes source control data for controlling the output timing of the data voltage output from the source drive ICs (SIC # 1 to SIC # 8), the polarity of the data voltage, and the like. In addition, the control data may include gate control data for controlling the operation timing of the gate drive IC (GIC). The signal transfer protocol between the timing controller (TCON) and the source drive ICs (SIC # 1 to SIC # 8) is disclosed in Korean Patent Application No. 10-2008-0127458 (2008-12-15), US Application No. 12 / 543,996 -19), Korean Patent Application 10-2008-0127456 (2008-12-15), US Application 12 / 461,652 (2009-08-19), Korean Patent Application 10-2008-0132466 (2008-12-23), USA 12 / 537,341 (2009-08-07).

The source drive ICs (SIC # 1 to SIC # 8) are connected in a point-to-point fashion to a timing controller (TCON) via a pair of data wires. Each of the source drive ICs SIC # 1 to SIC # 8 may be connected to the data lines of the liquid crystal display panel LCP by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The source drive ICs SIC # 1 to SIC # 8 receive the RGB digital video data, the external clock signal CLK, and the control data through the data line pair through the receiving terminal comparator Rx as shown in FIG. The source drive ICs SIC # 1 to SIC # 8 receive the frequency of the received external clock signal CLK through a phase locked loop (PLL) or a delay locked loop (DLL) Generates the number of bits of video data x 2 internal clock signals, samples the RGB digital video data according to the internal clock signal, and converts the sampled RGB digital video data into a parallel data system.

The source drive ICs (SIC # 1 to SIC # 8) decode the control data input through the pair of data lines by a code mapping method to recover the source control data and the gate control data. The source drive ICs SIC # 1 to SIC # 8 convert the RGB digital video data converted into the parallel system according to the source control data into the positive / negative analog data voltages and output the data voltages to the data lines of the liquid crystal display panel LCP (DL). The source drive ICs (SIC # 1 to SIC # 8) can transmit gate control data to one or more of the gate drive ICs (GIC).

The gate drive IC (GIC) may be connected to the gate lines of the TFT array substrate of the liquid crystal display panel through the TAP process or directly formed on the TFT array substrate of the liquid crystal display panel (LCP) by a GIP (Gate In Panel) process . The gate drive IC GIC is supplied from the timing controller TCON or sequentially supplies gate pulses to the gate lines GL in accordance with gate control data supplied through the source drive ICs SIC # 1 to SIC # 8 Supply. The gate control data includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) controls the start horizontal line at which the scan starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is a clock signal that is input to a shift register in the gate drive IC (GIC) to sequentially shift the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive IC (GIC).

FIG. 5 is a detailed circuit diagram of a receiver comparator Rx according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 5, a data line pair ZO is connected to both input terminals of a receiving terminal comparator Rx. Two terminal resistances RT are connected between one data line ZO and the other data line ZO of the data line pair ZO and a switch element SW is connected to a node between the terminal resistors . The switch element is mounted on the source PCB on which the source drive ICs (SIC # 1 to SIC # 8) are mounted.

The source PCB is supplied with the ground voltage (GND) and the terminal voltage (Vterm). The base low voltage GND may be set to 0 V, and the terminal voltage Vterm may be set to approximately 1.2 V. [ The switch element SW may be floating by operation of an operator or connected to a capacitor C connected to a ground voltage source GND. Here, the fact that the switch element SW is floating means that the node between the terminal resistances RT is not connected to any voltage source. In this case, the receiving stage comparator Rx of the source drive ICs SIC # 1 to SIC # 8 is implemented with a receiving stage comparator Rx substantially the same as in FIG.

The switch element SW may supply the terminal voltage Vterm to the node between the terminal resistances RT by connecting the terminal voltage source Vterm to the node between the terminal resistances RT by the operation of the operator. In this case, the receiving stage comparator Rx of the source drive ICs SIC # 1 to SIC # 8 operates as a receiving stage comparator Rx substantially the same as in FIG.

The switch element SW can supply the terminal voltage Vterm to the node between the terminal resistances RT. In this case, the receiving stage comparator Rx of the source drive ICs SIC # 1 to SIC # 8 operates as a receiving stage comparator Rx substantially the same as in FIG.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TCON: Timing controller SIC: Source drive IC
GIC: Gate drive IC Tx: Transmitter comparator
Rx: Receiver stage comparator SW: Switch element

Claims (5)

A timing controller for outputting data through a transmission stage comparator;
One or more source driver ICs for receiving data from the timing controller through a receiver stage comparator connected to the transmitter stage comparator via a data wire pair, converting the data to a data voltage and supplying the data voltage to the data lines of the display panel;
First and second terminal resistors connected in series between the two input terminals of the receiving terminal comparator; And
And a switch element for connecting a node between the first and second terminal resistances to a base voltage source or a terminal voltage source.
The method according to claim 1,
The switch element includes:
And supplies a terminal voltage from the terminal voltage source to a node between the first terminal resistance and the second terminal resistance.
The method according to claim 1,
The switch element includes:
And a node between the first terminal resistance and the second terminal resistance is connected to the base voltage source via a capacitor.
The method according to claim 1,
And the switch element is floated.
The method according to claim 1,
The timing controller
Converts the data into a differential signal pair, and outputs the differential signal pair to the data line pair through the transmission terminal comparator,
The source drive IC includes:
Receiving the difference signal pair through the receiver comparator connected to the data wire pair,
And a pair of data lines through which the difference signal pair is transmitted are connected in series between the timing controller and the source drive IC.

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