KR101757454B1 - A method for forming a three dimensional non-volatile memory device - Google Patents

Abstract

A method of forming a three-dimensional semiconductor memory element is provided. A method of forming a three-dimensional semiconductor memory device according to the present invention includes loading a substrate into one chamber, alternately and repeatedly depositing oxide films and sacrificial films in the chamber, and unloading the substrate from the chamber Wherein during the deposition of each of the oxide films, the oxygen source gas may comprise nitrous oxide.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of forming a three-dimensional semiconductor memory device,

The present invention relates to a method of forming a three-dimensional semiconductor memory element, and more particularly, to a method of forming a three-dimensional semiconductor memory element including stacking a plurality of oxide films and sacrificial films.

It is required to increase the degree of integration of semiconductor memory elements in order to satisfy the excellent performance and the low price required by the consumer. In the case of a semiconductor memory device, the degree of integration is an important factor in determining the price of the product, and thus an increased degree of integration is required. In the case of the conventional two-dimensional or planar semiconductor memory element, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional semiconductor memory device is increasing, but it is still limited, because the ultrafast equipment is required for the miniaturization of the pattern.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, a process technology capable of reducing the manufacturing cost per bit of the two-dimensional semiconductor memory device and realizing a reliable product characteristic is required.

A problem to be solved by the present invention is to provide a method of forming a three-dimensional semiconductor memory element capable of improving productivity.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a three-dimensional semiconductor memory device with improved reliability and electrical characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A method of forming a three-dimensional semiconductor memory element to solve the above-described technical problems is provided. A method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes loading a substrate into one chamber, alternately and repeatedly depositing oxide films and sacrificial films in the chamber, Wherein the oxygen source gas may comprise nitrous oxide during the deposition of each of the oxide films.

According to one embodiment, alternating and repeated deposition of the oxide films and sacrificial films may include depositing an oxide film, first purging the first gas mixture used to deposit the oxide film, depositing a sacrificial film And a second purging of the second gas mixture used for the deposition of the sacrificial film, wherein the deposition of the oxide film, the first purging, the deposition of the sacrificial film, and the second purging can be repeatedly performed a plurality of times.

According to one embodiment, the sacrificial layer is a silicon nitride layer, and the oxide layers may be a silicon oxide layer.

According to one embodiment, the sacrificial layers can be deposited by a first gas mixture comprising silane and ammonia, and the oxide layers include tetraethyl-ortho-silicate (TEOS) and nitrous oxide The second gas mixture being < / RTI >

According to one embodiment, each of the first gas mixture and the second gas mixture may further comprise a carrier gas.

A method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming semiconductor patterns through the oxide films and the sacrificial films, patterning the oxide films and the sacrificial films, and forming trenches and alternately and repeatedly Forming stacked sacrificial patterns and oxide film patterns, wherein the semiconductor patterns pass through the sacrificial patterns and the oxide film patterns, removing the sacrificial patterns to form empty regions between the oxide film patterns, Forming a multi-layered dielectric film on the inner surface of the dielectric layer, and forming gate patterns to fill the void regions, respectively.

According to one embodiment, the multilayered dielectric film may include a blocking insulating film, a charge trap film, and a tunnel insulating film.

According to one embodiment, alternately and repeatedly stacked gate patterns and oxide film patterns are included in the gate structure, and a plurality of semiconductor patterns passing through the gate structure can be arranged in one column in one direction.

According to one embodiment, alternately and repeatedly stacked gate patterns and oxide film patterns are included in the gate structure, and a plurality of semiconductor patterns passing through the gate structure may be arranged in a zigzag fashion in one direction .

According to embodiments of the present invention, oxide films and sacrificial films can be alternately and repeatedly deposited in one chamber. Thus, it is possible to improve the productivity of forming oxide films and sacrificial films alternately and repeatedly stacked.

Further, by using nitrous oxide as the oxygen source gas when forming the oxide films and the sacrificial films, it is possible to minimize the particles generated on the substrate when forming the oxide films and the sacrificial films have. Therefore, a three-dimensional semiconductor memory device with improved reliability and electrical characteristics can be realized.

1 is a simplified circuit diagram of a three-dimensional semiconductor memory device according to an embodiment of the present invention.
2 is a perspective view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention.
3 is a flowchart illustrating a method of alternately and repeatedly depositing oxide films and sacrificial layers to form a three-dimensional semiconductor memory device according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a method of alternately and repeatedly depositing oxide films and sacrificial layers to form a three-dimensional semiconductor memory device according to an embodiment of the present invention.
5A to 5D are particle maps showing the degree of generation of particles in a gas reaction test.
6 to 13 are perspective views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention.
Figs. 14A to 14D are views showing part A of Fig.
15 and 16 are perspective views showing a three-dimensional semiconductor memory device according to another embodiment of the present invention.
17 is a schematic block diagram showing an example of a memory system including a three-dimensional semiconductor memory element according to embodiments of the present invention.
18 is a schematic block diagram showing an example of a memory card having a three-dimensional semiconductor memory element according to the embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, a three-dimensional semiconductor memory device and a method of forming the same according to embodiments of the present invention will be described in detail with reference to the drawings.

The three-dimensional semiconductor memory device according to embodiments of the present invention may include a cell array region, a peripheral circuit region, and a connection region. In the cell array region, bit lines and word lines are arranged for electrical connection to a plurality of memory cells and memory cells. Peripheral circuitry may be formed with peripheral circuits that drive memory cells and read data stored in memory cells. Specifically, a word line driver, a sense amplifier, row and column decoders, and control circuits may be disposed in the peripheral circuit region C / P. The connection region may be disposed between the cell array region and the peripheral circuit region, and a wiring structure for electrically connecting the word lines and the peripheral circuits may be disposed.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory element according to an embodiment of the present invention. 2 is a perspective view showing a cell array of a three-dimensional semiconductor memory element according to an embodiment of the present invention.

1, a cell array of a three-dimensional semiconductor memory device according to an embodiment includes a common source line CSL, a plurality of bit lines BL, and a common source line CSL and bit lines BL And a plurality of cell strings (CSTR) arranged in the cell array.

The bit lines are arranged two-dimensionally, and a plurality of cell strings CSTR are connected in parallel to each of the bit strings. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between a plurality of bit lines and one common source line CSL. According to one embodiment, a plurality of common source lines CSL may be two-dimensionally arranged. Here, electrically common voltages may be applied to the common source lines CSL, or each common source line CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and ground and string selection transistors GST and SST And a plurality of memory cell transistors MCT arranged between the plurality of memory cell transistors MCT. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground selection transistors GST. In addition, the ground selection line GSL, the plurality of word lines WL0-WL3 and the plurality of string selection lines SSL, which are disposed between the common source line CSL and the bit lines BL, As the gate electrodes of the selection transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a data storage element.

Referring to FIG. 2, the common source line CSL may be a conductive thin film disposed on the substrate 100 or an impurity region formed in the substrate 100. The bit lines BL may be conductive patterns (e.g., metal lines) spaced from and disposed above the substrate 100. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL. Whereby the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate 100.

Each of the cell strings CSTR includes a plurality of ground selection lines GSL1 and GSL2 disposed between the common source line CSL and the bit lines BL, a plurality of word lines WL0 to WL3, And two string selection lines SSL1 and SSL2. In one embodiment, a plurality of string selection lines (SSL1, SSL2) is also can be configured to the string selection line of the two (SSL), a plurality of ground selection line (GSL1, GSL2) is selected ground in Fig. 2 Lines GSL can be constructed. The ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2 may be conductive patterns stacked on the substrate 100. [

Each of the cell strings CSTR may include a semiconductor column (or a vertical semiconductor pattern) PL extending vertically from the common source line CSL and connected to the bit line BL. The semiconductor pillars PL may be formed to penetrate the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2. In other words, the semiconductor pillars PL may penetrate a plurality of conductive patterns stacked on the substrate 100. [ In addition, the semiconductor pillars PL may include impurity regions D formed at one or both ends of the body portion B and the body portion B, respectively. For example, a drain region D may be formed at the upper end of the semiconductor column PL (i.e., between the body portion B and the bit line BL).

A data storage film DS may be disposed between the word lines WL0-WL3 and the semiconductor pillars PL. According to one embodiment, the data storage film DS may be a charge storage film. For example, the data storage film DS may be one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots.

A dielectric film used as a gate insulating film of the transistor may be disposed between the ground select lines GSL1 and GSL2 and the semiconductor columns PL or between the string select lines SSL1 and SSL2 and the semiconductor column PL. Here, the dielectric layer may be formed of the same material as the data storage layer DS or may be a gate insulation layer (for example, a silicon oxide layer) for a typical MOSFET.

In this structure, the semiconductor pillars PL together with the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2, It is possible to constitute a MOSFET (field effect transistor) for use as a channel region. Alternatively, the semiconductor pillars PL may comprise MOS capacitors together with the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2. can do.

In this case, the ground selection lines GSL1 and GSL2, the plurality of word lines WL0 to WL3, and the plurality of string selection lines SSL1 and SSL2 may be used as the gate electrodes of the selection transistor and the cell transistor, respectively. The semiconductor pillars PL are formed by a fringe field from voltages applied to the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2, Inversion regions may be formed in the substrate. Here, the maximum distance (or width) of the inversion region may be greater than the thickness of the word lines or selection lines that create the inversion region. Thus, the inversion regions formed in the semiconductor column are vertically superimposed to form a current path electrically connecting the selected bit line from the common source line CSL.

That is, the cell string CSTR includes the cell transistors (also referred to as cell transistors) constituted by the ground and string transistors constituted by the lower and upper selection lines GSL1, GSL2, SSL1 and SSL2 and the word lines WL0 to WL3 2 MCT) may be connected in series.

The operation of the three-dimensional semiconductor memory device described with reference to FIGS. 1 and 2 will be briefly described below. The method of operating the three-dimensional semiconductor memory device according to the embodiments of the present invention is not limited thereto and can be variously modified.

First, the program operation for writing data in the memory cells will be described. The same voltage is applied to the word lines WL0-WL3 located on the same layer, and different voltages may be applied to the word lines WL0-WL3 located on different layers. The program voltage V _{- PGM} is applied to the word lines WL0-WL3 of the layer including the selected memory cell and the pass voltage V _PASS is applied to the word lines WL0-WL3 of the non- . Here, the program voltage V _{PGM -} is a high voltage of about 10 to 20 V, and the pass voltage V _{PASS -} is a voltage capable of turning on the memory cell transistors. In addition, 0 V is applied to the bit line BL connected to the selected memory cell transistor, and Vcc voltage (i.e., power supply voltage) is applied to the other bit lines BL. Then, 0V (i.e., ground voltage) is applied to the ground selection lines GSL, and all the ground selection transistors are turned off. Furthermore, Vcc voltage is applied to the selected string selection line SSL and 0 V is applied to the unselected string selection line SSL. In this voltage condition, the selected memory cell transistors MCT included in the selected string selection transistor SST and the selected cell string CSTR can be turned on. Therefore, the channel of the memory cell transistors MCT included in the selected cell string CSTR has the equal potential (i.e., 0V) with the selected bit line BL. At this time, since the high program voltage V _PGM is applied to the word lines WL0-WL3 of the selected memory cell transistor MCT, the FN tunneling phenomenon occurs and data can be written to the selected memory cell transistor.

Next, a read operation for reading data written in the memory cells will be described. The same voltage is applied to the word lines WL0-WL3 located on the same layer, and different voltages may be applied to the word lines WL0-WL3 located on different layers. Specifically, for the read operation, 0V is applied to the word lines WL0-WL3 connected to the selected memory cell transistor MCT, and the word lines WL0 of the non-selected memory cell transistors MCT located on the other layer -WL3) is applied with a read voltage (Vread). Here, the read voltage Vread is a voltage capable of turning on unselected memory cell transistors. A bit line voltage of about 0.4 to 0.9 V can be applied to the selected bit line BL, and 0 V is applied to the other bit lines BL. 0 V is applied to the common source line CSL and the read voltage Vread is applied to the ground selection lines GSL so that the channel of the selected memory cell transistor MCT can be connected to the common source line CSL have. In addition, the read voltage Vread is applied to the selected string selection line SSL and 0V is applied to the non-selected string selection line SSL. Under such a voltage condition, the memory cell transistor MCT may be turned on or off according to data (0 or 1) in the selected memory cell. When the selected memory cell transistor MCT is turned on, a current flow can be generated in the cell string CSTR and a current change in the cell string CSTR can be detected through the selected bit line BL.

For example, when electrons are stored in the selected memory cell transistor MCT, the selected memory cell transistor MCT is turned off and the voltage of the selected bit line BL is not transferred to the common source line CSL Do not. Alternatively, if no electrons are stored in the selected memory cell transistor MCT, the selected memory cell may be turned on by the read voltage, and the voltage of the bit line BL may be transferred to the common source line CSL .

Next, the erasing operation of the three-dimensional semiconductor memory element will be described. According to one embodiment, the charge stored in the memory cell transistor MCT can be released to the semiconductor column PL and then erased. According to another embodiment, charge of the opposite type to that stored in the data storage film may be injected into the data storage film and erased. According to another embodiment, one of the memory cell transistors may be selected and erased, or the memory cell transistors MCT may be erased simultaneously.

Hereinafter, a method of forming a three-dimensional semiconductor memory device including forming a laminated structure in which a plurality of sacrificial films and oxide films are stacked will be described in detail with reference to FIGS. 3 and 4. FIG. FIG. 3 is a flowchart illustrating a method of alternately and repeatedly depositing oxide films and sacrificial layers to form a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a cross- FIG. 3 is a cross-sectional view illustrating a method of alternately and repeatedly depositing the oxide films and the sacrificial films according to FIG.

Referring to FIG. 3, the substrate 100 may be loaded into the process chamber (S100). The deposition equipment including the process chamber may further include a load lock chamber, a transfer chamber, and a transfer robot. The substrate 100 may be transferred to the transfer chamber through the load lock chamber. The substrate 100 can be loaded into the process chamber using a transfer robot disposed in the transfer chamber.

Referring to FIGS. 3 and 4, the sacrificial layer 10 and the oxide layer 20 may be formed in the process chamber (S110). The sacrificial layer 10 and the oxide layer 20 may be formed by a chemical vapor deposition process (CVD). According to one embodiment, the chemical vapor deposition process (CVD) may include a plasma enhanced chemical vapor deposition process (PE-CVD). The plasma enhanced chemical vapor deposition process (PE-CVD) may be performed by generating a plasma using microwave or RF power to deposit a film in a plasma atmosphere. In addition, the process chamber may be a single type of chamber.

The sacrificial layer 10 and the oxide layer 20 may be materials having an etch selectivity with respect to each other. The sacrificial layer 10 may be a silicon nitride layer, and the oxide layer 20 may be a silicon oxide layer. For example, the silicon oxide film constituting the oxide film 20 may be formed of a material selected from the group consisting of Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PE-TEOS), Undoped Silicate Glass (USG), Phospho-Silicate Glass (PSG) silicate Glass, BPSG (Boro-Phospho-Silicate Glass), or a combination thereof.

The step S110 may include a step S111 of depositing the sacrificial layer 10, a first purging step S113, a step S115 of depositing the oxide layer 20, and a second purging step S117 .

The step S111 of depositing the sacrificial layer 10 may be performed using the first gas mixture. The first gas mixture may comprise a silicon source gas and a nitrogen source gas. For example, the silicon source gas may include at least one selected from the group consisting of silane gas and tetraethyl-ortho-silicate gas (TEOS), and the nitrogen source gas may be at least one selected from the group consisting of ammonia gas and nitrogen gas And may include at least one selected. The sacrificial layer 10 may be formed on the substrate 100 by reacting the silicon source gas and the nitrogen source gas.

The first gas mixture may further comprise a carrier gas. The carrier gas may include at least one of nitrogen, argon, and helium.

According to one embodiment, the first gaseous mixture may comprise about 10-100 sccm of a silicon source gas, about 10-100 sccm of a nitrogen source gas, and about 1-5 sccm of a carrier gas.

The first purging step S113 may include discharging a first gas mixture used to deposit the sacrificial layer 10 and a by-product generated during the deposition of the sacrificial layer 10 to the outside of the process chamber It can be done.

The step of depositing the oxide layer 20 (S115) may be performed using the second gas mixture on the sacrificial layer 10. The second gas mixture may comprise a silicon source gas and an oxygen source gas. For example, the silicon source gas may comprise at least one selected from silane gas or tetraethylorthosilicate gas (TEOS). According to embodiments of the present invention, the oxygen source gas may include nitrous oxide gas (N ₂ O). The silicon source gas and the nitrous oxide gas react with each other to form the oxide film 20 on the sacrificial layer 10. [

The second gas mixture may further comprise a carrier gas. The carrier gas may include at least one of nitrogen, argon, and helium.

According to one embodiment, the second gaseous mixture may comprise about 10 to 100 sccm of a silicon source gas, about 10 to 100 sccm of a nitrous oxide gas, and about 1 to 5 sccm of a carrier gas.

The second purging step S117 may include discharging a second gas mixture used to deposit the oxide layer 20 and a by-product generated during the deposition of the oxide layer 20 out of the process chamber .

The sacrificial layer 10 deposition step S111 and the oxide layer deposition step S115 may be performed at a process temperature of about 250 DEG C to 650 DEG C and an RF power RF power can be used to form a plasma.

The step (110) may be repeatedly performed a plurality of times in the one process chamber. Accordingly, a stacked structure in which the sacrificial films 10 and the oxide films 20 are alternately and repeatedly stacked on the substrate 100 can be formed.

In the above-described method, the step (110) may first form the sacrificial layer (10) and form the oxide layer (20). However, the present invention is not limited thereto. For example, the sacrificial layer 10 may be formed after the oxide layer 20 is formed first. In this case, the first purging step 113 may include a second gas mixture used to deposit the oxide film 20 and a by-product generated during the deposition of the oxide film 20, It may be discharge. In addition, the second purging step 117 may include a first gas mixture used to deposit the sacrificial layer 10 and a by-product generated during deposition of the sacrificial layer 10, It may be to discharge it out.

Referring again to FIG. 3, the sacrificial layers 10 and the oxide layers 20 may alternatively and repeatedly deposit the substrate 100 (S120) from the process chamber. The substrate 100 on which the laminated structure is formed may be unloaded to the load lock chamber through the transfer chamber. The substrate 100 on which the laminated structure is formed can be unloaded from the process chamber using the transfer robot disposed in the transfer chamber.

According to the embodiments of the present invention, since the laminated structure is formed in one process chamber, it is possible to reduce the time required to move the plurality of chambers to form the sacrificial layer 10 and the oxide layer 20 The productivity of forming the laminated structure can be improved.

Gas reaction tests were performed by combining the gases used to form the sacrificial films 10 and the oxide films 20 in one process chamber. 5A to 5D are particle maps showing the degree of generation of particles in gas reaction tests.

5A shows the degree of generation of particles on a bulk wafer after reacting silane gas, ammonia gas, tetraethylorthosilicate gas (TEOS), and oxygen gas (O ₂ ). As shown in FIG. 5A, at least two kinds of gases selected from silane gas, ammonia gas, tetraethylorthosilicate gas (TEOS) or oxygen gas (O ₂ ) react with each other, Respectively.

FIG. 5B shows particles generated on a bulk wafer after reacting tetraethylorthosilicate gas (TEOS), ammonia gas, and oxygen gas (O ₂ ). In this case, the amount of particles generated on the bulk wafer was smaller than in the case of FIG. 5A. Compared to the gases used in Figure 5a, no silane gas was used in Figure 5b.

FIG. 5C shows particles generated on the wafer after reacting silane gas, tetraethylorthosilicate gas (TEOS), and oxygen gas (O ₂ ). In this case, particles are generated on the bulk wafer in a large amount similar to the case of FIG. 5A. Compared to the gases used in Figure 5b, silane gas was used in Figure 5c.

Figure 5d shows particles generated on the wafer after reacting silane gas and tetraethylorthosilicate gas (TEOS). In this case, as in the case of FIG. 5B, the amount of particles generated on the bulk wafer was smaller than in the case of FIG. 5A. Compared to the gases used in Figure 5c, no oxygen gas (O ₂ ) was used in Figure 5d.

According to the results of the gas reaction tests of Figs. 5A to 5D, when the sacrificial films 10 and the oxide films 20 are deposited in one process chamber, the sacrificial films 10 The silane gas used may increase the generation of particles on the substrate 100 by reacting with the oxygen gas O ₂ used for depositing the oxide film 20. After depositing the sacrificial film 10 react with oxygen gas (O ₂₎ is used when the silane gas could not be discharged from the first purge step (S113) is to deposit the oxide film 20, the substrate 100 It is possible to increase the generation of particles on the substrate. However, according to the embodiments of the present invention, the use of nitrous oxide (N ₂ O) instead of oxygen (O ₂ ) as the oxygen source gas makes it possible to prevent the generation of particles on the substrate 100 Can be minimized. Therefore, the reliability and electrical characteristics of the three-dimensional semiconductor memory element can be improved

Hereinafter, a method of manufacturing a three-dimensional semiconductor memory device using the method of forming a laminated structure according to the embodiments of the present invention will be described with reference to FIGS. 6 to 13. FIG.

6 to 13 are perspective views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 6, a stacked structure ST in which sacrificial films SC1 to SC8 and oxide films 111 to 118 are alternately and repeatedly stacked on a substrate 100 can be formed.

The substrate 100 may be formed of a material having a semiconductor property (for example, a silicon wafer, a silicon film, a germanium film, a silicon germanium film), an insulating material (for example, As shown in FIG.

The sacrificial films SC1 to SC8 and the oxide films 111 to 118 may be formed by the method described with reference to FIGS.

The sacrificial films SC1 to SC8 and the oxide films 111 to 118 may be formed of materials having etching selectivity ratios mutually. For example, the oxide films 111 to 118 may be silicon oxide films, and the sacrificial films SC1 to SC8 may be silicon nitride films.

According to one embodiment, the sacrificial films SC1 to SC8 may be the sacrificial films 10 described with reference to FIGS. 3 and 4, May be the oxide films 20 described with reference to FIG. In this case, the sacrificial films SC1 to SC8 and the oxide films 111 to 118 may be formed by chemical vapor deposition (CVD) in one process chamber. According to one embodiment, the chemical vapor deposition process (CVD) may include a plasma enhanced chemical vapor deposition process (PE-CVD). That is, the sacrificial films SC1 to SC8 and the oxide films 111 to 118 may be formed by repeatedly performing the step S110 of FIG. 3 a plurality of times in the one process chamber.

The steps of depositing the sacrificial layers SC1 to SC8 may be formed by the same method as described with reference to FIGS. The steps of depositing the respective oxide films 111 to 118 may also be formed by the same method as described with reference to FIGS. Therefore, nitrous oxide (N ₂ O) may be used as an oxygen source gas in the step of depositing the oxide films 111 to 118.

According to one embodiment, the sacrificial layers SC1 to SC8 may have the same thickness. Alternatively, the uppermost sacrificial layer SC1 and the uppermost sacrificial layer SC8 of the sacrificial layers SC1 to SC8 may be formed thicker than the sacrificial layers SC2 to SC7 located therebetween . In this case, the sacrificial layers SC2 to SC7 between the sacrificial layers SC1 and SC8 of the lowermost layer and the uppermost layer may be formed to have the same thickness.

According to an embodiment, the uppermost oxide layer 118 among the oxide layers 111 to 118 may be thicker than the oxide layers 111 to 117 thereunder. The oxide films 111 to 117 under the uppermost oxide film 118 may be formed to have the same thickness. The oxide films 112 and 116 formed on a predetermined layer of the oxide films 111 to 118 may be thicker than the other oxide films 111 to 113 .

In addition, a buffer insulating layer 101 may be formed between the sacrificial layer (SC1) of the lowest layer and the substrate (100). The buffer insulating layer 101 may be formed to be thinner than the other oxide layers 111 to 118. The buffer insulating layer 101 may be a silicon oxide layer formed through a thermal oxidation process.

Referring to FIG. 7, the openings 131 for exposing the substrate 100 are formed by patterning the stacked structure ST.

The step of forming the openings 131 may include forming a mask pattern (not shown) defining a planar position of the openings 131 on the stacked structure ST, And anisotropically etching the stacked structure ST using the stacked structure ST as an etch mask.

The openings 131 may be formed to expose the sidewalls of the sacrificial films SC1 to SC8 and the oxide films 111 to 118. [ Also, according to one embodiment, the openings 131 may be formed through the buffer insulating layer 101 to expose the upper surface of the substrate 100. The upper surface of the substrate 100 exposed to the openings 131 may be recessed to a predetermined depth by overetching while the openings 131 are formed. The openings 131 may have different widths depending on the distance from the substrate 100 by the anisotropic etching process.

According to one embodiment, each of the openings 131 may be formed in a cylindrical or rectangular hole shape, and may be formed two-dimensionally and regularly on the xy plane. That is, the openings 131 are spaced apart from each other on the x-axis and the y-axis. According to another embodiment, in the horizontal shape, the openings 131 may be a line-shaped trench extending in the y-axis direction. The line-shaped openings 131 may be formed parallel to each other. In another embodiment, the openings 131, as shown Figure 16, or may be staggered (zig zag) disposed in the y-axis direction. The distance between adjacent ones of the openings 131 in one direction may be less than or equal to the width of each of the openings 131. As such, when the openings 131 are arranged in a zigzag manner, a larger number of openings 131 can be disposed within a certain area.

Referring to FIG. 8, the semiconductor patterns 132 may be formed in the openings 131.

The semiconductor patterns 132 may be formed in the openings 131 and may be in direct contact with the substrate 100 and may be substantially perpendicular to the substrate 100. [ The semiconductor patterns 132 may include, for example, silicon (Si), germanium (Ge), or a mixture thereof. The semiconductor patterns 132 may be impurity-doped semiconductors, Or may be an intrinsic semiconductor in an undoped state. In addition, the semiconductor patterns 132 may have a crystal structure including at least one selected from the group consisting of single crystal, amorphous, and polycrystalline.

The semiconductor patterns 132 may be formed in the openings 131 using a chemical vapor deposition technique or an atomic layer deposition technique. When the semiconductor patterns 132 are formed using a deposition technique, a discontinuous interface due to a crystal structure difference may be formed between the semiconductor patterns 132 and the substrate 100. In addition, according to one embodiment, the semiconductor patterns 132 may be formed of monocrystalline silicon by depositing amorphous silicon or polysilicon, and then phase-transforming the amorphous silicon or the polycrystalline silicon through a heat treatment process such as laser annealing. According to another embodiment of the present invention, an epitaxial process is performed using the substrate 100 exposed by the openings 131 as a seed layer, (132) may be formed.

In addition, the semiconductor pattern 132 may be deposited to a thickness less than half the width of the opening 131. In this case, the semiconductor pattern 132 may fill a portion of the opening 131 and define a hollow region in a central portion of the opening 131. Further, the thickness of the semiconductor pattern 132 (i.e., the thickness of the shell) may be thinner than the width of the depletion region to be generated in the semiconductor film in operation of the semiconductor memory element or smaller than the average length of the silicon grains constituting the polycrystalline silicon . That is, each of the semiconductor patterns 132 may be formed in a pipe-shaped, a hollow cylindrical shape, or a cup shape in each of the openings 131. In addition, the buried insulating patterns 134 may be filled in the empty regions defined by the semiconductor patterns 132. The buried insulating patterns 134 may be formed of an insulating material having excellent gap fill characteristics. For example, the buried insulating patterns 134 may be formed of a high-density plasma oxide layer, a SOG layer (Spin On Glass layer), a CVD oxide layer, or the like.

In addition, the semiconductor patterns 132 may be completely filled in the cylindrical openings 131 by a deposition process to have a cylindrical shape. In this case, a planarization process for the semiconductor film may be performed after the semiconductor film filling the openings 131 is deposited on the stacked structure ST.

15 , the semiconductor patterns 132 are formed in the openings 131, and the semiconductor patterns 132 are formed in the openings 131. The openings 131 are formed in a line shape, Insulation patterns can be interposed. The semiconductor patterns 132 are formed by sequentially forming a semiconductor film and a buried insulating film in the openings 131 and patterning the semiconductor film and the buried insulating film to form a rectangular plane in each of the openings 131 The semiconductor patterns 132 can be formed. The cross section of the semiconductor patterns 132 may have a U-shaped shape.

Referring to FIG. 9, after the semiconductor patterns 132 are formed, trenches 140 may be formed to expose the substrate 100 between adjacent semiconductor patterns 132.

Specifically, forming the trenches 140 may include forming a mask pattern (not shown) defining a planar position of the trenches 140 on the stacked structure ST, And anisotropically etching the stacked structure ST by using the stacked structure ST as an etch mask.

The trenches 140 may be spaced apart from the semiconductor patterns 132 and may be formed to expose the sidewalls of the sacrificial layers SC1 to SC8 and the oxide layers 111 to 118. [ In the horizontal shape, the trenches 140 may be formed in a line shape or a rectangular shape. Also, in the vertical depth, the trenches 140 may be formed to expose the upper surface of the substrate 100. In addition, the trenches 140 may have different widths depending on the distance from the substrate 100 by the anisotropic etching process. The top surface of the substrate 100 exposed to the trenches 140 by overetching during the formation of the trenches 140 may be recessed to a predetermined depth.

As the trenches 140 are formed, a preliminary gate structure in which the sacrificial patterns SC1 to SC8 and the oxide film patterns 111 to 118 are alternately and repeatedly stacked can be formed. The preliminary gate structure may be in the form of a line extending in the y-axis direction. A plurality of semiconductor patterns 132 arranged in the y-axis direction may pass through the preliminary gate structure. As such, the preliminary gate structure may have an inner wall adjacent to the semiconductor patterns 132 and an outer wall exposed to the trenches 140.

Meanwhile, according to one embodiment, after forming the trenches 140, the impurity region 105 may be formed in the substrate 100. The impurity region 105 may be formed through an ion implantation process using the preliminary gate structure formed by the trenches 140 as an ion mask. The impurity region 105 may overlap with a portion of the lower region of the preliminary gate structure by diffusion of impurities. The impurity region 105 may have a conductivity type opposite to that of the substrate 100.

Referring to FIG. 10, the sacrificial patterns SC1 to SC8 exposed by the trenches 140 are removed to form recessed regions 142 between the oxide film patterns 111 to 118 .

The recess regions 142 may be formed by removing the sacrificial patterns SC1 to SC8 between the oxide film patterns 111 to 118. [ That is, the recess regions 142 may extend horizontally from the trenches 140 to between the oxide pattern patterns 111 to 118 and may expose portions of the sidewalls of the semiconductor patterns 132 have. The recess region 142 formed at the lowermost portion may be defined by the buffer insulating film 101. [ Vertical thickness of the recess region 142 formed in this way (the length in the z-axis direction) is the deposition of the sacrificial layer in (SC1 ~ SC8) when depositing said sacrificial layer (SC1 ~ SC8) in Fig. 6 Can be defined by the thickness.

Specifically, the recessed regions 142 are formed by isotropically etching the sacrificial patterns SC1 to SC8 using the etching recipe having etching selectivity with respect to the oxide film patterns 111 to 118 Lt; / RTI > Here, the sacrificial patterns SC1 to SC8 may be completely removed by an isotropic etching process. For example, when the sacrificial patterns SC1 to SC8 are silicon nitride films and the oxide film patterns 111 to 118 are silicon oxide films, the etching process may be performed using an etchant containing phosphoric acid.

Referring to FIG. 11, a multi-layered dielectric film 150 may be formed in the recessed regions 142.

The multi-layered dielectric film 150 may be formed to substantially conformally cover the preliminary gate structure in which the recessed regions 142 are formed. The multi-layer dielectric film 150 may be formed using deposition techniques (e.g., chemical vapor deposition or atomic layer deposition techniques) that can provide good step coverage. The multi-layered dielectric film 150 may be formed to a thickness smaller than half of the thickness of the recessed regions 142. That is, a multi-layered dielectric film 150 may be formed on the sidewalls of the semiconductor patterns 132 exposed in the respective recessed regions 142, and the multi-layered dielectric film 150 may be formed on the sidewalls of the respective recessed regions 142 And may extend to the lower surface and the upper surface of the oxide film patterns 111 to 118, respectively. In addition, the multi-layered dielectric film 150 formed by the deposition process may be formed on the surface of the substrate 100 exposed between the thin film structures in the form of a line and the top surface of the topmost oxide film pattern 118, The sidewalls of the sidewalls 111 to 118 may be covered. The multilayered dielectric film 150 may cover the upper surface of the substrate 100 or the buffer insulating film 101 exposed by the lowermost recessed region 142. That is, the multi-layered dielectric film 152 may be conformally formed on the surface of the preliminary gate structure in which the recessed regions 142 are formed.

According to another embodiment, as shown in FIG. 14B, multilayer dielectric patterns 154 are locally formed between vertically adjacent oxide film patterns 111 to 118 to form vertically adjacent other multilayer dielectric patterns ( 154, respectively. Thus, when the multi-layer dielectric patterns 154 are vertically separated from each other, it is possible to prevent the charges trapped in the multi-layer dielectric patterns 154 from spreading to adjacent multi-layer dielectric patterns 154 adjacent to each other. Layer dielectric pattern 154 is formed between the buffer insulating layer 101 and the substrate (not shown) even when each of the multilayered dielectric patterns 154 is formed locally between the vertically adjacent oxide layer patterns 111 to 118, 100). ≪ / RTI >

According to one embodiment, the multi-layer dielectric film 150 may be a charge storage film. For example, the charge storage film may be one of a charge trap insulating film, a floating gate electrode, or an insulating film including conductive nano dots. When the multilayered dielectric film 150 is a charge storage film, information stored in the multilayered dielectric film 150 is induced by a voltage difference between the semiconductor patterns 132 and the gate electrodes (WL in FIG. 12) Can be changed using Fowler-Nordheim tunneling. Meanwhile, the multi-layered dielectric film 150 may be a thin film (for example, a thin film for a phase change memory or a thin film for a variable resistance memory) capable of storing information based on another operation principle.

According to one embodiment, as shown in FIGS. 14A and 14C, the multilayered dielectric film 152 may include a blocking insulating film 152a, a charge trap film 152b, and a tunnel insulating film 152c which are sequentially stacked. The blocking insulating layer 152a may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric layer, and may be formed of a plurality of layers. In this case, the high-k dielectric layer refers to insulating materials having a dielectric constant higher than that of the silicon oxide layer, and may be a tantalum oxide layer, a titanium oxide layer, a hafnium oxide layer, a zirconium oxide layer, an aluminum oxide layer, a yttrium oxide layer, a niobium oxide layer, a cesium oxide layer, Film and a PZT film. The tunnel insulating layer 152c may be formed of a material having a dielectric constant lower than that of the blocking insulating layer 152a. For example, the tunnel insulating layer 152c may include at least one selected from oxides, nitrides, and oxynitrides. The charge trap film 152b may be an insulating thin film (for example, a silicon nitride film) rich in charge trap sites or an insulating thin film including conductive grains. According to one embodiment, the tunnel insulating film 152c is a silicon oxide film, the charge trap film 152b is a silicon nitride film, and the blocking insulating film 152a is an insulating film including an aluminum oxide film.

Meanwhile, according to another embodiment, the blocking insulating layer 152a may include a first blocking insulating layer and a second blocking insulating layer. Here, the first and second blocking insulating films may be formed of different materials, and one of the first and second blocking insulating films may have a bandgap smaller than the tunnel insulating film 152c and larger than the charge trap film Lt; / RTI > For example, the first blocking insulating layer is one of high-k films such as an aluminum oxide layer and a hafnium oxide layer, and the second blocking insulating layer may be a material having a smaller dielectric constant than the first blocking insulating layer. According to another embodiment, the second blocking insulating film is one of the high-k films, and the first blocking insulating film may be a material having a smaller dielectric constant than the second blocking insulating film.

According to another embodiment, in the multi-layered dielectric film 152 composed of the blocking insulating film 152a, the charge trap film 152b and the tunnel insulating film 152c sequentially stacked, the tunnel insulating film 152c and the charge trap film 152b May be formed across the inner wall of the stacked structure ST adjacent to the semiconductor patterns 132, as shown in FIG. 14C. That is, the tunnel insulating film 152c and the charge trap film 152b may be formed on the inner walls of the openings 131 before the semiconductor patterns 132 are formed. The blocking insulating layer 152a may be formed in the recessed regions 142 after forming the recessed regions 142. [ Accordingly, the blocking insulating layer 152a may directly contact the upper surface and the lower surface of the oxide film patterns 111 to 118. The charge trap film 152b and the blocking insulating film 152a may be formed in the recess regions 142 after the recess regions 142 are formed.

Next, referring to FIGS. 11 and 12, gate electrodes WL may be formed in each of the recessed regions 142 where the multi-layered dielectric film 150 is formed. In addition, when the gate electrodes WL are formed, a common source line CSL may be formed in the substrate 100 together.

As the gate electrodes WL are formed in the recessed regions 142 in which the multilayered dielectric film 150 is formed in a conformal manner, the vertical thickness of each of the gate electrodes WL is greater than the vertical thickness of the respective recessed regions 142. [ Can be reduced. The reduction in the thickness of the gate electrodes WL may increase the resistance of the gate electrodes WL. Therefore, in order to improve the integration and the electrical characteristics of the three-dimensional semiconductor memory device, it is necessary to reduce the resistivity of the materials constituting the gate electrodes WL.

According to one embodiment, the gate electrodes WL and the common source line CSL may be formed of a metal material having a low specific resistance (for example, tungsten). The common source line CSL may be an impurity region 105 formed in the substrate 100. However, when the common source line CSL is an impurity region formed in the substrate 100, it is difficult to keep the resistance constant and the resistance of the common source line CSL may be high.

According to another embodiment, the common source line CSL may include an impurity region 105 and a common source silicide film 184 in the substrate 100. The common source line CSL including the metal silicide can be reduced in resistance than the common source conductive line made of the impurity region 105. [ The common source silicide layer 184 constituting the common source line CSL may include a gate silicide layer 182 constituting the gate electrodes WL stacked on the substrate 100, As shown in FIG.

Hereinafter, a method of forming the gate electrodes WL and the common source line CSL will be described in detail with reference to FIGS. 11 and 12. FIG.

The formation of the gate electrodes WL may include forming a gate conductive layer 170 in the recessed regions where the multi-layered dielectric layer 150 is formed and the trenches 140, And removing the gate conductive layer 170 to form the gate electrodes WL vertically separated from each other.

The gate conductive film 170 may be formed using a deposition technique (e.g., chemical vapor deposition or atomic layer deposition technique) capable of providing excellent step coverage. Thus, the gate conductive layer 170 may be conformally formed in the trenches 140 while filling the recessed regions 142. Specifically, the gate conductive layer 170 may be deposited to a thickness of a half or more of the thickness of each of the recessed regions 142. When the planar width of each of the trenches 140 is greater than the thickness of the respective recessed regions 142, the gate conductive layer 170 fills a portion of the trenches 140, A blank area can be defined at the center portion of the area. At this time, the empty area can be opened up.

The gate conductive layer 170 may include at least one of doped polysilicon, tungsten, metal nitride films, and metal silicides. According to one embodiment, forming the gate conductive film 170 includes forming a barrier metal film (e.g., metal nitride) and a metal film (e.g., tungsten) in sequence. Meanwhile, since the technical idea of the present invention is not limited to the three-dimensional semiconductor memory device, the gate conductive film 170 may be variously modified in terms of material and structure.

Then, the gate conductive layer 170 filled in the trenches 140 is anisotropically etched to form the vertically separated gate electrodes WL.

Specifically, removing the gate conductive layer 170 in the trenches 140 may be performed using an etching mask (not shown), which is a topmost oxide layer pattern or a hard mask pattern (not shown) And anisotropically etching the gate conductive film 170 using the etching mask. When the gate conductive layer 170 is anisotropically etched, the multi-layered dielectric layer 150 in contact with the upper surface of the substrate 100 may be used as an etch stop layer.

According to one embodiment, the multi-layer dielectric film 150 covering the upper surface of the substrate 100 may be exposed to form the vertically separated gate electrodes WL. Alternatively, the upper surface of the substrate 100 may be exposed in the trenches 140 as the gate conductive layer 170 is anisotropically etched. As shown in the figure, the upper surface of the substrate 100 may be recessed .

According to another embodiment, the gate electrodes WL may be formed by performing an isotropic etching process on the gate conductive film 170 having a vacant region. The isotropic etching process may be performed until the gate electrodes WL are separated from each other. That is, the sidewalls of the oxide film patterns 111 to 118 and the multi-layered dielectric film 150 on the upper surface of the substrate 100 may be exposed by an isotropic etching process. Here, as the isotropic etching process is performed through the vacant regions, the gate conductive films 170 at the side walls and bottom portions of the vacant regions can be etched substantially simultaneously. The gate conductive layer 170 may be uniformly etched on the upper portion of the preliminary gate structure and the upper portion of the substrate 100 by performing the isotropic etching process through the open region. Accordingly, the horizontal thickness of the gate electrodes WL can be uniform. In addition, the horizontal thickness of the gate electrodes WL may be varied depending on the process time in the isotropic etching process. For example, the gate electrodes WL may be formed to fill a portion of the recessed regions. Thus, the gate electrodes (WL) each of Figures 14a to the like, a barrier metal pattern 162 is interposed between the metal patterns (163a) and a gate silicide film 182 and the multi-layer dielectric layer 152, shown in Figure 14c . ≪ / RTI >

According to one embodiment, the gate electrodes WL formed locally in each of the recessed regions 142 and the oxide film patterns 111 to 118 may constitute a gate structure. That is, the gate structure may be formed between adjacent trenches 140. According to one embodiment, the gate structure may have a line shape extending in one direction. A plurality of semiconductor patterns 132 arranged in one direction may pass through the gate structure. The gate electrodes WL have outer walls adjacent to the trenches 140 and inner walls adjacent to the semiconductor patterns 132. The inner walls of these gate electrodes WL may surround the semiconductor patterns 132 or may cross one side wall of the semiconductor pattern 132. [ Alternatively, the gate electrodes WL included in one block may be connected to each other in the word line contact region WCTR, and may be formed in a comb-shape or a finger-shape.

According to this embodiment, the stacked gate electrodes WL can be used as the string selection line SSL, the ground selection line GSL and the word lines WL described in FIG. For example, the uppermost layer and the lowermost layer of the gate electrodes WL are used as the string selection line SSL and the ground selection line GSL, respectively, and the gate electrodes WL therebetween are connected to the word lines WL. .

Alternatively, as described with reference to FIG. 3, two layers of gate electrodes WL disposed at the top may be used as a string selection line (SSL in FIG. 2), and two layers of gate electrodes WL May be used as the ground selection line (GSL in Fig. 2). The gate electrodes WL used as a string selection line (SSL in FIG. 2) or a ground selection line (GSL in FIG. 2) can be horizontally separated, in which case, Select lines (SSL in FIG. 2) or ground select lines (GSL in FIG. 2 ) can be placed.

14A, a step of selectively removing the sidewalls of the oxide film patterns 111 to 118 and the multi-layered dielectric film 150 formed on the surface of the substrate 100 is further performed as shown in FIG. 14A . The step of removing the multilayered dielectric film 150 may use an etching gas or an etching solution having an etching selection ratio with respect to the gate conductive film 170. For example, when the multi-layered dielectric film 150 on the sidewalls of the oxide film patterns 111 to 118 is removed through an isotropic etching process, an etching solution such as HF, O ₃ / HF, phosphoric acid, sulfuric acid and LAL is used . Further, in order to remove the multilayered dielectric film 150, a fluoride series etching solution and a phosphoric acid or a sulfuric acid solution may be sequentially used.

Referring to FIG. 13, after the gate electrodes WL are formed, impurity ions are implanted into the substrate 100 between the gate electrodes WL to form impurity regions 105 used as a common source line. Can be formed.

Specifically, the impurity regions 105 can be formed through an ion implantation process using the gate structures on the substrate 100 as an ion implantation mask. Accordingly, the impurity regions 105 may be in the form of a line extending in one direction, such as a horizontal shape of the trench. The impurity regions 105 may overlap with a portion of the lower region of the gate structure by diffusion of impurities. In addition, the impurity regions 105 may have a conductivity type opposite to that of the substrate 100.

When the impurity regions 105 are formed, the multi-layered dielectric film 150 located on the bottom surface of the trenches 140 may be used as an ion implantation buffer film. According to another embodiment, the impurity regions 105 may be formed in the substrate 100 below the trenches 140 after forming the trenches 140, as described with reference to FIG.

Also, according to one embodiment, a silicidation process may be performed in which the impurity regions 105 in the substrate 100 are reacted with the metal film 180 to form a metal silicide.

Next, referring to FIG. 13, a gate isolation insulation pattern 190 is formed in the trenches 140.

The step of forming the gate isolation insulation pattern 190 includes filling the trenches 140 from which unreacted metal film has been removed with at least one of the insulating materials. According to one embodiment, the gate separation insulation pattern 190 may be at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. According to another embodiment of the present invention, before forming the gate isolation insulation pattern 190 in the trenches 140, the gate insulation layer 130 may be formed on the gate insulation layer 130 to prevent oxidation of the gate electrodes WL and the common source silicide layers 184. [ A capping film may be formed. The capping layer may be formed of an insulating nitride, for example, a silicon nitride layer.

After the gate isolation insulation pattern 190 is formed, a conductive type impurity opposite to the semiconductor patterns 132 is injected into an upper portion of the semiconductor patterns 132 to form a drain region D . Alternatively, the drain region D may be formed on the semiconductor patterns 132 before forming the trenches 140 described in FIG.

Bit lines BL for electrically connecting the semiconductor patterns 132 may be formed on the gate electrodes WL. The bit lines BL may be formed along a direction crossing the gate electrodes WL formed in a line shape as shown in FIG. The bit lines BL may be connected to the drain region D on the semiconductor patterns 132 by a contact plug.

17 is a schematic block diagram showing an example of a memory system including a three-dimensional semiconductor memory element manufactured according to the manufacturing method of the embodiments of the present invention.

17, an electronic system 1100 according to one embodiment of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, (1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. The storage device 1130 may be used to store instructions executed by the controller. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The storage device 1130 may include at least one of the three-dimensional semiconductor storage elements according to the present invention. Further, the storage device 1130 may further include other types of semiconductor storage elements (ex, a DRAM element and / or an SLAM element). The interface 1140 may perform functions to transmit data to or receive data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and / or an SLAM device as an operation memory device for improving the operation of the controller 1110. [

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

18 is a schematic block diagram showing an example of a memory card having a semiconductor memory element manufactured according to the manufacturing method of the embodiments of the present invention.

Referring to FIG. 18, a memory card 1200 for supporting a high capacity data storage capability mounts a three-dimensional semiconductor memory element 1210 according to the present invention. The three-dimensional semiconductor memory element 1210 may include at least one of the three-dimensional semiconductor memory elements of the above-described embodiments. Further, the three-dimensional semiconductor memory element 1210 may further include other types of semiconductor memory elements (ex, a DRAM element and / or an SLAM element). The memory card 1200 may include a memory controller 1220 that controls data exchange between the host and the three-dimensional semiconductor memory device 1210.

The memory controller 1220 may include a processing unit 1222 that controls the overall operation of the memory card. In addition, the memory controller 1220 may include an SRAM 1221, which is used as an operation memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225. The host interface 1223 may include a data exchange protocol between the memory card 1200 and a host. The memory interface 1225 may connect the memory controller 1220 and the three-dimensional semiconductor memory device 1210. Further, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 can detect and correct errors in data read from the three-dimensional semiconductor storage element 1210. Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. The memory card 1200 may be used as a portable data storage card. Alternatively, the memory card 1200 may be implemented as a solid state disk (SSD) capable of replacing a hard disk of a computer system.

Further, the three-dimensional semiconductor memory element or memory system according to the present invention can be mounted in various types of packages. For example, the three-dimensional semiconductor memory device or the memory system according to the present invention can be used as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package A wafer-level stacked package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (9)

Loading the substrate into one chamber;
Alternately and repeatedly depositing a plurality of oxide films and a plurality of sacrificial films in the one chamber; And
Wherein the oxygen source gas comprises nitrous oxide (N ₂ O) at the time of depositing each oxide film, comprising: unloading the substrate from the one chamber. The method according to claim 1,
The alternately and repeatedly lamination of the oxide films and the sacrificial films,
Depositing an oxide film;
Purging the first gas mixture used to deposit the oxide film;
Depositing a sacrificial film; And
And a second purging step of purging the second gas mixture used for the deposition of the sacrificial film, wherein the deposition of the oxide film, the first purging, the deposition of the sacrificial film, and the second purging are repeatedly performed a plurality of times / RTI > 3. The method of claim 2,
Wherein the sacrificial layers are silicon nitride layers, and the oxide layers are silicon oxide layers. The method of claim 3,
The sacrificial films are deposited by a first gas mixture comprising silane and ammonia,
Wherein the oxide films are deposited by a second gas mixture comprising tetraethylorthosilicate (TEOS) and nitrous oxide. 5. The method of claim 4,
Wherein each of the first gas mixture and the second gas mixture further comprises a carrier gas. The method according to claim 1,
Forming semiconductor patterns through the oxide films and the sacrificial films;
Patterning the oxide films and the sacrificial films to form trenches and alternately and repeatedly stacked sacrificial patterns and oxide film patterns, the semiconductor patterns passing through the sacrificial patterns and the oxide film patterns;
Removing the sacrificial patterns to form empty regions between the oxide film patterns;
Forming a multi-layered dielectric film on the inner surface of the void regions; And
And forming gate patterns to fill the vacant regions, respectively. The method according to claim 6,
Wherein the multilayered dielectric film comprises a blocking insulating film, a charge trap film and a tunnel insulating film. The method according to claim 6,
Wherein the semiconductor patterns are arranged in one row in one direction. The method according to claim 6,
Wherein the semiconductor patterns are arranged in a zigzag shape in one direction.

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