KR101746862B1 - Liquid Crystal Display - Google Patents

Abstract

The liquid crystal display according to the present invention is characterized in that the intersection of m / 2 (m is a positive even number) data lines extending along the column direction and 2n (n is a natural number) a liquid crystal display panel having n pixels defined therein and having a display region in which m / 2 gate link lines extending along the column direction between the data lines and connected to the gate lines are arranged; A data driver disposed on one side of the liquid crystal display panel for applying a data voltage to the data lines; And a gate driver disposed on the other side of the liquid crystal display panel so as to face the data driver with the display region interposed therebetween and supplying scan pulses to the gate lines through the gate link lines.

Description

[0001] Liquid crystal display [0002]

The present invention relates to a liquid crystal display capable of reducing a bezel area.

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in accordance with a video signal. Since the liquid crystal display device can actively control the switching element, it is advantageous for implementing a moving image.

A thin film transistor (hereinafter referred to as "TFT") is mainly used as a switching element used in a liquid crystal display device. The gate electrode of the TFT is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode of the liquid crystal cell. A common voltage is supplied to the common electrode of the liquid crystal cell facing the pixel electrode. When a scan pulse is applied to the gate line, the TFT is turned on to form a channel between the source electrode and the drain electrode to supply the voltage on the data line to the pixel electrode of the liquid crystal cell. At this time, the liquid crystal molecules of the liquid crystal cell are changed in arrangement by the electric field between the pixel electrode and the common electrode to modulate the incident light.

Such a liquid crystal display includes a gate drive IC (integrated circuit) for driving gate lines and a data drive IC for driving data lines. Since the number of drive ICs required in accordance with the enlargement of liquid crystal display devices is also increasing, a gate driver in panel (GIP) technology has been proposed to reduce material costs. GIP technology eliminates gate driver ICs and instead incorporates gate drivers into panels.

As shown in Fig. 1, the gate driver of the GIP scheme divides the display area AA when the liquid crystal display panel is divided into the display area AA for forming the pixel array and the bezel area BA outside the display area Are formed in the bezel areas BA disposed on the left and right sides.

As shown in Fig. 2, in the bezel area BA, gate link lines for connecting the GIP circuit 3 and each gate line, as well as the lower glass substrate 1a and the lower glass substrate 1b, An external common line 4 for supplying a common voltage to the common electrode of the pixel array, and a black matrix BM for preventing light leakage are arranged. Therefore, in the conventional liquid crystal display device, there is a limit in reducing the left and right bezel areas BA.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of reducing a left and right bezel area.

It is another object of the present invention to provide a liquid crystal display device capable of reducing manufacturing cost and gate load deviation.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention includes m / 2 (m is positive even) data lines extending in the column direction and 2n (n is a natural number M × n pixels are defined by the intersection of the gate lines and the display region in which m / 2 gate link lines extending along the column direction and connected to the gate lines are arranged between the data lines A liquid crystal display panel; A data driver disposed on one side of the liquid crystal display panel for applying a data voltage to the data lines; And a gate driver disposed on the other side of the liquid crystal display panel so as to face the data driver with the display region interposed therebetween and supplying scan pulses to the gate lines through the gate link lines.

In the liquid crystal display device according to the present invention, the gate driver may be disposed on the lower side of the liquid crystal display panel so that the left and right bezel regions can be drastically reduced.

Further, the present invention adopts DRD driving to reduce the number of data driver ICs, thereby greatly reducing the manufacturing cost, minimizing the overlap between the gate link line and other signal lines, reducing the parasitic capacitance, It is possible to prevent the image quality defect by minimizing the gate rod deviation by changing the connection ratio between the gate lines.

1 is a view showing a conventional bezel region;
Fig. 2 is a cross-sectional view taken along the line I-I 'in Fig. 1; Fig.
3 is a view illustrating a liquid crystal display according to an embodiment of the present invention.
4 is a view showing a detailed connection configuration of liquid crystal cells;
5 is a cross-sectional view of a gate line and a gate line.
6 is a cross-sectional view taken along line II-II 'in FIG. 3;
7 is a view showing a width of a bezel region according to the present invention in comparison with a conventional one;
8 is a view showing the magnitude of the amount of the gate rod according to the display position.
9A to 9C are diagrams showing a method for reducing a variation in gate load amount between display areas.
10 is a view showing a relative positional relationship between a pixel common line pattern and a gate link line;
11 is a cross-sectional view taken along line III-III 'in FIG. 10;
12 is a view illustrating a liquid crystal display according to another embodiment of the present invention.
13 is a view showing a method for reducing the deviation of a gate load amount between display areas;

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 13. FIG.

FIG. 3 shows a liquid crystal display according to an embodiment of the present invention. 4 shows a detailed connection configuration of liquid crystal cells. 5 shows a cross-sectional view of the connection of the gate link line and the gate line. FIG. 6 is a cross-sectional view taken along line II-II 'in FIG. 3, and FIG. 7 shows a width of a bezel region according to the present invention in comparison with the prior art.

Referring to FIG. 3, the liquid crystal display of the present invention includes a liquid crystal display panel 10, a data driver (DDRV), and a gate driver (GDRV).

The liquid crystal display panel 10 includes a display area AA for forming a pixel array. In the display area AA, m / 2 (m is a positive even number) data lines extending along the column direction and 2n (n is a natural number) gate lines extending along the row direction are arranged. Then, m / 2 gate link lines extending along the column direction are arranged between the data lines.

The liquid crystal display panel 10 has a liquid crystal layer formed between two glass substrates. Data lines, gate lines, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed by a combination of IPS (In Plane Switching) mode, FFS (Fringe Field Switching) In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate together with the pixel electrode 1. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal display panel 10 includes m × n liquid crystal cells Clc arranged in a matrix form for each intersection of data lines and gate lines, and driven by a double rate driving (DRD) method. DRD driving reduces the number of data lines by half and increases the number of gate lines by twice, thereby realizing the same resolution as the conventional one. In the DRD driving, two liquid crystal cells neighboring each other with the data line interposed therebetween share the data line and are sequentially driven according to the driving frequency twice. DRD drive is advantageous in cost reduction because it can reduce the number of relatively expensive data drivers in half.

The liquid crystal cells Clc include a plurality of R liquid crystal cells, G liquid crystal cells, and B liquid crystal cells. The connection structure of the liquid crystal cells Clc for DRD driving will be described with reference to FIG.

(-) liquid crystal cell connected to the first gate line G1 and the G (-) liquid crystal cell connected to the second gate line G2 in the first row pixel line RL # 1 arranged along the row direction, (+) Liquid crystal cell connected to the first gate line G1 and an R (+) liquid crystal cell connected to the second gate line G2 are connected in common to the first data line D1, (-) liquid crystal cell connected to the first gate line G1 and the B liquid crystal cell (-) connected to the second gate line G2 are connected in common to the second data line D2, And are commonly connected to the third data line D3 adjacent to each other.

In the second row pixel line RL # 2 adjacent to the first row pixel line RL # 1 in the column direction, the R (+) liquid crystal cell connected to the first gate line G1 and the second gate line (-) liquid crystal cell connected to the second gate line G1 and the G (+) liquid crystal cell connected to the second gate line G2 are connected in common to the first data line D1, The liquid crystal cells R (-) connected to the first gate line G1 are commonly connected to the second data line D2, and the G (+) liquid crystal cell and the second gate line G2, which are connected to the first gate line G1, B liquid crystal cells (+) connected to the second data line D2 are connected to the third data line D3 in common.

(+) Liquid crystal cell is a liquid crystal cell in which a positive voltage having a higher potential than a common voltage (Vcom) is charged, and (-) a liquid crystal cell is a liquid crystal cell in which a negative voltage having a potential lower than a common voltage . Therefore, among the liquid crystal cells arranged in the first row pixel line RL # 1, the R (-) liquid crystal cell and the G (-) liquid crystal cell sharing the first data line D1 are connected to the gate lines G1 and G2 And the B (+) liquid crystal cell and the R (+) liquid crystal cell sharing the second data line D2 are sequentially charged from the gate lines G1 and G2 in synchronization with the supply of the scan pulse from the scan lines The G (-) liquid crystal cell and the B (-) liquid crystal cell sharing the third data line D3 are sequentially charged in the positive polarity in synchronization with the supply of the scan pulse of the scan lines G1 and G2 And are sequentially charged in a negative polarity in synchronization with the pulse supply timing. Among the liquid crystal cells arranged in the second row pixel line RL # 2, the R (+) liquid crystal cell and the G (+) liquid crystal cell sharing the first data line D1 are connected to the gate lines G1 and G2, (-) liquid crystal cell and R (-) liquid crystal cell sharing the second data line D2 are sequentially charged in the positive polarity in synchronization with the supply of the scan pulses from the gate lines G1 and G2 (+) Liquid crystal cell and the B (+) liquid crystal cell sharing the third data line D3 are charged in the negative polarity in synchronization with the supply of the scan pulse, and the scan pulses from the gate lines G1 and G2 And are sequentially charged in the positive polarity in synchronization with the supply timing.

The data driver DDRV includes a plurality of data driver ICs arranged on one side (i.e., upper side) of the liquid crystal display panel 10 and attached in a TAB (Tape Automated Bonding) manner. Each of the data driver ICs may be implemented in a source TCP (Tape Carrier Package) (or source COF (Chip On Film)). The source TCP electrically connects the source PCB (SPCB) and the liquid crystal display panel (10). The input terminals of the source TCP are electrically connected to the output terminals of the source PCB SPCB and the output terminals of the source TCP are connected to data pads (not shown) formed on the lower glass substrate of the liquid crystal display panel 10 through anisotropic conductive film Respectively. The data pads are connected one-to-one with the data lines. The data driver (DDRV) converts the input digital video data into a data voltage and supplies it to the data lines.

The gate driver GDRV is disposed on the other side (i.e., lower side) of the liquid crystal display panel 10 so as to face the data driver DDRV with the display area AA therebetween. The gate driver GDRV may be embedded in the other non-display region of the liquid crystal display panel 10 according to a gate driver in panel (GIP) scheme. The gate driver GDRV includes GIP circuit portions (GIP # 1 to GIP # 2n) as many as the number of gate lines.

The gate driver GDRV supplies scan pulses to the gate lines through the gate link lines GLL1, GLL2, GLL3, and so on. Since the gate link lines GLL1, GLL2, GLL3, ... are formed between the data lines in the liquid crystal display panel 10, the number thereof is substantially equal to the number of data lines, many. The gate link lines may be formed on the same layer as the data lines. In this case, the gate link line GLL may be in contact with the gate line GL through the contact hole 15 formed in the gate insulating film GI as shown in FIG. In Fig. 5, the symbol 'SUB' denotes a lower glass substrate.

The gate driver GDRV is disposed on the lower side of the liquid crystal display panel 10, unlike the prior art which is disposed on the left and / or right side of the liquid crystal display panel 10. [ Due to such arrangement change of the gate driver GDRV, the GIP circuit portion and the gate link lines do not need to be formed in the left (right) side bezel region of the liquid crystal display panel 10 as shown in Fig. As a result, the left (right) side bezel area BA of the liquid crystal display panel 10 is greatly reduced as compared with the conventional one, as shown in FIG. The present invention can reduce the width of the bezel area (BA), which was 6.75 mm, to less than 1.0 mm, thereby greatly enhancing the product competitiveness. 6, reference numeral 20 denotes a sealant for attaching the lower glass substrate 10a and the lower glass substrate 10b, 40 denotes an external common electrode for supplying a common voltage to the common electrode of the pixel array, Line, and a reference numeral 'BM' denotes a black matrix for preventing light leakage in the bezel area BA, respectively.

As described above, the liquid crystal display according to the embodiment of the present invention places the gate driver GDRV on the lower side of the liquid crystal display panel 10 in order to minimize the left (right) side bezel area BA. Then, DRD driving is adopted to arrange the gate link lines on the liquid crystal display panel 10 while minimizing the decrease of the aperture ratio. A method for reducing the deviation of the gate rods according to the position will be described below with such a configuration.

Fig. 8 shows the magnitude of the amount of the gate rod according to the display position.

Referring to FIG. 8, the amount of gate load per pixel location is gradually decreased in the order of PXL A, PXL B, PXL C, and PXL D. The amount of gate load per display position becomes larger as the distance from the gate driver is increased. The largest in the upper part AR1 of the display area AA and the next largest in the central part AR2 of the display area AA and the smallest in the lower part AR3 of the display area AA. The amount of gate load affects the RC delay together with the parasitic capacitance. As the RC delay value increases, the charging and holding characteristics of the data voltage deteriorate. To reduce the RC delay value, the gate load amount (R) must be reduced and / or the parasitic capacitance value (C) must be reduced.

9A, a method for reducing the amount of gate load will be described with reference to FIG. 9C.

Since the number of liquid crystal cells arranged in the row direction is much larger than the number of liquid crystal cells arranged in the column direction, the number of data lines is reduced to 1/2 and the number of gate lines is doubled The number of liquid crystal cells arranged in the row direction is larger than the number of liquid crystal cells arranged in the column direction. For example, when 1366 (horizontal resolution) x 768 (vertical resolution) is implemented by the DRD method, the number of data lines is 2049 (1366 x 3) / 2 and the number of gate lines is 1536 (768 x 2) . Since the number of gate link lines is equal to the number of data lines, the number of gate link lines is also 2049. [ However, since the number of gate lines to be actually driven is 1536, when one-to-one connection is made between the gate line and the gate link line, 513 gate link lines can not participate in the connection.

In view of the fact that the number of gate link lines is larger than that of the gate lines in the present invention, the connection ratio of the gate line to the gate link line in the third region AR3 having the smallest gate load amount is set to 1: a (a is a natural number of 1 or more) In the second region AR2 in which the load amount is intermediate, the connection ratio of the gate line to the gate link line is set to 1: b (b is a natural number larger than a), and in the first region AR1, Let the connection ratio of the line be 1: c (c is a natural number greater than b). Since the resistance value is inversely proportional to the cross-sectional area, as the number of gate link lines connected to one gate line is increased to increase the cross-sectional area, the amount of gate load is reduced.

9A shows a connection configuration in the first area AR1 where the connection ratio of the gate line to the gate link line is 1: 3.

Referring to FIG. 9A, the first gate line G (a) is connected to each of the first through third gate link lines GLL (a), GLL (a + 1), and GLL (15). The scan pulses generated in the first GIP circuit section GIP # a are commonly applied to the first through third gate link lines GLL (a), GLL (a + 1) and GLL (a + Is applied to the gate line G (a).

The second gate line G (a + 1) is connected to each of the fourth through sixth gate link lines GLL (a + 3), GLL (a + ). The scan pulses generated in the second GIP circuit part GIP # b are commonly transmitted through the fourth to sixth gate link lines GLL (a + 3), GLL (a + 4) and GLL (a + And applied to the second gate line G (a + 1).

FIG. 9B shows a connection configuration in the second area AR2 where the connection ratio of the gate line to the gate link line is 1: 2.

9B, the first gate line G (b) is connected to the first and second gate link lines GLL (b) and GLL (b + 1) through the contact hole 15 at the same time do. The scan pulses generated in the first GIP circuit part GIP # b are commonly applied to the first gate line G (b) through the first and second gate link lines GLL (b) and GLL (b + 1) .

The second gate line G (b + 1) is simultaneously connected to the third and fourth gate link lines GLL (b + 2) and GLL (b + 3) through the contact hole 15. The scan pulses generated in the second GIP circuit portion GIP # b + 1 are commonly applied to the second gate line GLL (b + 3) through the third and fourth gate link lines GLL (b + 2) G (b + 1)).

FIG. 9C shows a connection configuration in the third area AR3 in which the connection ratio of the gate line to the gate link line is 1: 1.

Referring to FIG. 9C, the first gate line G (c) is connected to the first gate link line GLL (c) through the contact hole 15. The scan pulses generated in the first GIP circuit section GIP # c are commonly applied to the first gate line G (c) through the first gate link line GLL (c).

The second gate line G (c + 1) is connected to the second gate link line GLL (c + 1) through the contact hole 15. The scan pulses generated in the second GIP circuit part GIP # c + 1 are commonly applied to the second gate line G (c + 1) through the second gate link line GLL (c + 1).

A method for reducing the parasitic capacitance value will be described with reference to FIGS. 10 and 11. FIG. 10 shows the relative positional relationship between the pixel common line pattern EC, the gate link line GLL, and the pixel electrode EP. 11 is a cross-sectional view taken along line III-III 'in FIG.

In order to reduce the parasitic capacitance value, the overlapping area between the gate link line GLL and the other signal lines must be lowered. 10 and 11, in order to reduce the overlapped area, the gate line GLL and the pixel common line pattern EC are formed so as not to overlap with each other except for a specific connecting portion between the pixel common line patterns EC. . Each of the pixel common line patterns EC is formed below the gate insulating film GI together with the gate lines and is connected to each other through the specific connection portion surrounding the opening region of the pixel. The pixel common line pattern EC is connected to an external common line formed in the bezel region, receives a common voltage, and supplies this common voltage to the common electrode of the pixel. The gate link line GLL is formed between pixel common line patterns EC of neighboring pixels. In FIG. 11, reference numeral 'SUB' designates a lower glass substrate, 'GI' designates a gate insulation film, and 'PAS' designates a passivation film.

12 shows a liquid crystal display according to another embodiment of the present invention.

This liquid crystal display device is different from that of FIG. 3 only in the method of forming the gate driver GDRV, but the remaining configuration is substantially the same as that of FIG. The gate driver GDRV of FIG. 12 is formed by a TAB (Tape Automated Bonding) method like a data driver DDRV disposed on one side (i.e., upper side) of the liquid crystal display panel 10, Gate driver ICs (GIC # 1 to GIC # 4).

The gate driver GDRV is disposed on the other side (i.e., lower side) of the liquid crystal display panel 10 so as to face the data driver DDRV with the display area AA therebetween. The total number of channel numbers of the gate driver ICs (GIC # 1 to GIC # 4) constituting the gate driver (GDRV) is the same as the number of gate lines.

The gate driver GDRV is electrically connected to the gate lines through gate link lines. Since the gate link lines are formed between the data lines in the liquid crystal display panel 10, the number thereof is substantially equal to the number of the data lines, and is larger than the number of the gate lines.

Considering that the gate link lines are larger than the gate lines in this embodiment, the connection ratio of the gate line to the gate link line in the third region (AR3 in Fig. 8) having the smallest gate load amount is set to 1: a ), The connection ratio of the gate line to the gate link line is 1: b (b is a natural number larger than a) in the second region (AR2 in FIG. 8) The connection ratio of the gate line to the gate link line is set to 1: c (c is a natural number larger than b).

For example, when 1366 (horizontal resolution) x 768 (vertical resolution) is implemented by the DRD method, the number of data lines is 2049 (1366 x 3) / 2 and the number of gate lines is 1536 (768 x 2) . Since the number of gate link lines is equal to the number of data lines, the number of gate link lines is also 2049. [ 13, channel 1 (CH1) to channel 104 (CH104) of the gate driver (GDRV) are commonly connected to three gate link lines, and gate line 1 to gate line 104 And the scan pulse is sequentially applied to the scan electrodes. Each of the channel 105 (CH105) to the channel 410 (CH410) of the gate driver GDRV is commonly connected to two gate link lines and sequentially scanned (scanned) to the gate line 105 to the gate line 410 of the second area AR2 Pulse is applied. Each of the channels 411 (CH411) to CH1536 (CH1536) of the gate driver GDRV is individually connected to one gate link line, and sequentially applies a scan pulse to the gate line 411 to the gate line 1536 of the third area AR3 .

As described above, in the liquid crystal display device according to the present invention, the left and right bezel regions can be drastically reduced by disposing the gate driver on the lower side of the liquid crystal display panel.

Further, the present invention adopts DRD driving to reduce the number of data driver ICs, thereby greatly reducing the manufacturing cost, minimizing the overlap between the gate link line and other signal lines, thereby reducing parasitic capacitance, It is possible to prevent the image quality defect by minimizing the gate rod deviation by changing the connection ratio between the gate lines.

10: liquid crystal display panel 15: contact hole
20: sealant 40: external common line

Claims (9)

M × n pixels are defined by the intersection of m / 2 (m is positive even) data lines extending along the column direction and 2n (n is a natural number) gate lines extending along the row direction, A liquid crystal display panel having a display region in which m / 2 gate link lines extending along the column direction between the data lines and connected to the gate lines are arranged;
A data driver disposed on one side of the liquid crystal display panel for applying a data voltage to the data lines; And
And a gate driver which is disposed on the other side of the liquid crystal display panel to face the data driver with the display region therebetween and supplies scan pulses to the gate lines through the gate link lines. . The method according to claim 1,
Wherein two neighboring pixels with a data line therebetween share the data line and are connected to different gate lines and sequentially driven. The method according to claim 1,
And the connection ratio between the gate line and the gate link line varies depending on the display position in the display area. The method according to claim 1,
When the display region is divided into a first region, a second region in which the amount of the gate load is smaller than the first region, and a third region in which the amount of the gate load is smaller than the second region,
The connection ratio of the gate line to the gate link line in the third region is selected to be 1: a (a is a natural number of 1 or more);
The connection ratio of the gate line to the gate link line in the second region is selected to be 1: b (b is a natural number greater than a);
And the connection ratio of the gate line to the gate link line in the first area is selected to be 1: c (c is a natural number larger than b). 5. The method of claim 4,
Each of the gate lines of the first region being commonly connected to three gate link lines to receive a scan pulse from the gate driver;
Each of the gate lines of the second region being commonly connected to two gate link lines to receive a scan pulse from the gate driver;
Wherein each of the gate lines of the third region is connected to one gate link line to receive a scan pulse from the gate driver. The method according to claim 1,
Wherein the gate line lines are formed on the gate insulating film together with the data lines and are selectively contacted to the gate lines through contact holes passing through the gate insulating film. The method according to claim 6,
Wherein the display region further comprises pixel common line patterns for supplying a common voltage to a common electrode of each of the pixels;
Wherein each of the pixel common line patterns is formed below the gate insulating film together with the gate lines and is connected to each other through a specific connection portion surrounding the opening region of the pixel,
Wherein each of the pixel common line patterns is formed so as not to overlap the gate link lines except for the specific connection portion. The method according to claim 1,
Wherein the gate driver is embedded in the other non-display area of the liquid crystal display panel according to a gate driver in panel (GIP) scheme. The method according to claim 1,
Wherein the gate driver includes a plurality of gate driver ICs formed by a TAB (Tape Automated Bonding) method.

Images