KR101735590B1 - Transaction extracting apparatus and method thereof - Google Patents

Abstract

Provided are a transaction extraction apparatus, which collects a trace between a host and a memory, distinguishes an idle section and a transaction from the trace, and stores the transaction, and a method thereof. The transaction extraction apparatus can interpret a trace in real time to distinguish the trace. The transaction extraction apparatus can store start time and end time of a transaction by using a timestamp. The timestamp can be generated based on a clock of a host and a clock of a memory.

Description

[0001] TRANSACTION EXTRACTING APPARATUS AND METHOD THEREOF [0002]

The present invention relates to an apparatus and method for analyzing a protocol between a host and a memory, and more particularly, to an apparatus and method for extracting a transaction between a host and a memory.

Today, mobile systems such as smart phones and tablets use embedded flash memory as high-performance storage devices. Embedded flash memory has advantages of small size, low power and relatively strong durability, and the transfer speed is also relatively fast. However, since the embedded flash memory operates at a low transfer rate and at the same time low power, an unexpected error may occur while communicating with the host.

In order to cope with errors that may occur in the embedded flash memory, it is necessary to check the accuracy of the protocol such as clock, command signal, and data block in the interface step. A protocol analyzer is a device that can analyze the accuracy of a protocol.

The protocol analyzing device can collect commands or data transmitted between the embedded flash memory and the host to analyze the accuracy of the protocol. Generally, a protocol analyzing apparatus includes hardware for collecting protocols and software for analyzing collected protocols.

The hardware that collects the protocol converts the collected information into a format that is easy for the user to analyze, and then transmits it to the host. The hardware that collects the protocol can use a channel interface to transfer the converted data to the host. The software analyzing the collected protocols can be run on the host and can analyze the received information.

As the transfer rate of the embedded flash memory increases, the amount of data that the protocol analyzer needs to collect increases. Also, if the amount of collected data increases, more data needs to be transmitted to the host, so channel utilization may be lowered.

The present invention proposes a transaction extraction apparatus and method capable of reducing analysis time of analysis software by pre-processing traces before analysis software performs analysis.

The present invention proposes a transaction extracting apparatus and method for extracting and storing transactions in collected traces, thereby increasing channel utilization.

According to an embodiment of the present invention, there is provided an information processing apparatus including a trace collection unit for collecting traces between a host and a memory, a trace analysis unit for analyzing the traces to distinguish between idle periods and transactions, And a transaction storage unit for extracting the transaction other than the idle period in the trace and storing the extracted transaction together with the time stamp.

According to an embodiment of the present invention, there is provided an apparatus comprising: a command detection unit for identifying a command signal or a response signal included in a trace between a host and a memory; and a control unit for detecting, based on the command signal or the response signal, A trace analyzing apparatus including a detecting unit is provided.

According to an embodiment of the present invention, there is provided a method for processing a transaction, comprising: collecting a trace between a host and a memory; analyzing the trace to distinguish between an idle period and a transaction; generating a time stamp corresponding to a start time and an end time of the transaction And extracting the transaction from the trace, excluding the idle period, and storing the extracted transaction together with the time stamp, and a computer-readable recording medium storing the transaction extracting method.

According to one embodiment of the present invention, the analysis time of the analysis software can be reduced by preprocessing the trace before the analysis software performs the analysis.

According to an embodiment of the present invention, a channel utilization can be increased by extracting and storing a transaction in the collected trace.

1 is a diagram illustrating a memory and a host coupled with a transaction extracting apparatus according to an embodiment of the present invention.
FIG. 2 is a view showing a trace collected by a transaction extracting apparatus according to an embodiment of the present invention.
3 is a diagram illustrating a structure of a transaction extracting apparatus according to an embodiment of the present invention.
4 is a diagram illustrating a structure of a trace analysis unit according to an embodiment of the present invention.
5 is a state diagram of the command detection unit according to an embodiment of the present invention.
6A to 6G are state diagrams of a transaction detection unit according to an embodiment of the present invention.
7 is a flowchart illustrating an operation performed by the transaction extracting apparatus according to an embodiment of the present invention.

It is to be understood that the specific structural or functional descriptions of embodiments of the present invention disclosed herein are presented for the purpose of describing embodiments only in accordance with the concepts of the present invention, May be embodied in various forms and are not limited to the embodiments described herein.

Embodiments in accordance with the concepts of the present invention are capable of various modifications and may take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. However, it is not intended to limit the embodiments according to the concepts of the present invention to the specific disclosure forms, but includes changes, equivalents, or alternatives falling within the spirit and scope of the present invention.

The terms first, second, or the like may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example without departing from the scope of the right according to the concept of the present invention, the first element being referred to as the second element, Similarly, the second component may also be referred to as the first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Expressions that describe the relationship between components, for example, "between" and "immediately" or "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms " comprises ", or " having ", and the like, are used to specify one or more of the features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

FIG. 1 is a diagram illustrating a memory 110 and a host 100 to which a transaction extracting apparatus 120 according to an embodiment of the present invention is coupled. The host 100 is an apparatus capable of controlling the memory 110 and may be a smartphone, a smartpad, a personal computer, a laptop, or the like, as well as a central processing unit (CPU) .

Referring to FIG. 1, the host 100 may include a host controller 101 for controlling the memory. The host controller 101 means hardware or software for controlling the memory. The host controller 101 can generate a command signal for controlling the memory 110 based on an instruction of an application program, a middleware, and an operating system executed in the host 100. [ The command signal includes a command to write at least one data block to the memory 110, or an instruction to read at least one data block of the memory 110.

The host controller 101 can transmit the generated command to the memory 110 via the bus 130. [ FIG. 1 illustrates an embodiment in which the host 100 and the memory 110 are separated, and the memory 110 may be disposed inside the host 100. FIG.

Referring to FIG. 1, the memory 110 can manage stored data based on an instruction transferred from the host 100. [0034] FIG. The memory 110 may include a memory array 112 for storing data and a device controller 111 for managing data stored in the memory array 112. [

The memory 110 may be a flash memory. More specifically, the memory 110 may be a solid state drive (SSD), an embedded multimedia card (eMMC), or a universal flash storage (UFS).

Referring to FIG. 1, a transaction extracting apparatus 120 according to an embodiment of the present invention may be connected to a bus 130. Accordingly, the transaction extraction device 120 can collect the command signal, the response signal, and the data block that the host 100 and the memory 110 exchange with each other. A command signal, a response signal, and a data block that the host 100 and the memory 110 exchange with each other at an interface (e.g., the bus 130) level are collectively referred to as a protocol. That is, the transaction extraction device 120 can collect the protocol via the bus 130. [

The trace is a list of protocols in order of time transmitted by the host 100 and the memory 110. The transaction extraction device 120 according to an embodiment may collect traces by collecting protocols in a time sequence.

A transaction is a part of a trace, a combination of command signals, response signals, and data blocks that are related to each other. (I) a command signal that the host 100 delivers to the memory 110, (ii) a block of data that is passed to the memory 110, and (iii) ) Memory 110 records specific data based on the data block, and then, as a result, the response signal transferred to the host 100 can be viewed as one transaction.

The transaction extracting apparatus 120 according to an exemplary embodiment of the present invention may store only the transactions among the collected traces. Therefore, the transaction extracting apparatus 120 can remove an idle time, which is a section of the collected trace, in which the content of the protocol is absent. The transaction extracting apparatus 120 may store the time stamp corresponding to the start and end of the transaction instead of removing the idle period. As a result, the transaction extracting apparatus 120 can store more transactions in the same storage capacity.

Referring to FIG. 1, the transaction extracting apparatus 120 according to an embodiment of the present invention can transmit the stored trace to the analysis host 150 through the channel interface 140. The channel interface 140 may be a Universal Serial Bus (USB), a Peripheral Component Interconnect Bus (PCI), or a Peripheral Component Interconnect Bus Express (PCIe). As described above, the trace transmitted through the channel interface 140 has a small capacity because the idle section is removed. Thus, the channel utilization of the channel interface 140 may increase.

Referring to FIG. 1, the analysis host 150 may analyze the received trace by executing the analysis software 150. Analysis software 150 may analyze information related to the speed of memory 110 (e.g., read latency, device busy). The analysis software 150 may display the analyzed information or may store it in the form of a log. The performance of the analysis software 150 can be improved since the analysis software 150 does not need to remove the idle interval from the trace or extract the transaction.

FIG. 2 is a view showing a trace collected by a transaction extracting apparatus according to an embodiment of the present invention. The transaction extraction device can collect traces by storing the protocol of the bus connecting the host and the memory in chronological order. Figure 2 shows collected traces in chronological order along the arrow direction. FIG. 2 shows the collected traces classified into two axes (data block axis, command signal and response signal axis) according to the type.

Referring to FIG. 2, the host may forward the command signal 201 to the memory to fetch the data block from memory or write the data block to memory. The command signal 201 may include parameters required to transmit the data block. Examples of parameters include the bus width, the data transfer rate, and the number of data blocks. It is assumed that the command included in the command signal 201 fetches one data block from the memory.

Referring to FIG. 2, the memory may generate a response signal 202, corresponding to the command signal 201. The generated response signal 202 may be transmitted to the host via the bus. Since the command signal 201 is an instruction to fetch a data block, the acknowledgment signal 202 may indicate that the memory is ready to transmit the data block. Alternatively, the acknowledgment signal 202 may indicate that the memory is unable to transmit a block of data.

2, after a response signal 202 is transmitted, a data block 203 for the command signal 201 may be transmitted to the host via the bus. The data block 203 may include a CRC code (cyclic redundancy checking code) for checking the error of the data.

2, the host may receive the data block 203 and then pass the command signal 204 to the memory. The command signal 204 may be an ACK signal indicating that the data block 203 has been successfully received. Alternatively, the command signal 204 may be an instruction to resend the data block 203 again. The memory may communicate a response signal 205 to the command signal 204 to the host.

The response signal 205 is transmitted to the host, thereby completing the operation of fetching one data block 203 from the memory. The command signal 201, the response signal 202, the command signal 204 and the response signal 205 associated with the data block 203 and the data block 203 thus constitute one transaction 200.

Referring to FIG. 2, the host may transmit the command signal 211 to the memory again after a certain idle period 220 has passed since the transaction 200. It is assumed that the command included in the command signal 211 is to write a plurality of data blocks (two data blocks 213 and 214) in a memory.

2, the memory may communicate a response signal 212 corresponding to the command signal 211 to the host and the host may transmit the data blocks 213 and 214 to memory based on the response signal 212 have. The memory may write the received data blocks 213 and 214 to the memory array.

Referring to FIG. 2, the host may send a command signal 215 to the memory requesting the result of the recording operation. The memory may communicate the response signal 216 to the host in response to the command signal 215. The response signal 216 is transmitted to the host, thereby completing the operation of writing the data blocks 213 and 214. Thus, the command signal 211, response signal 212, command signal 215 and response signal 216 associated with data blocks 213 and 214 and data blocks 213 and 214 constitute one transaction 210 .

According to one embodiment of the present invention, the transaction extraction device may collect traces including the transaction 200 and the transaction 210 as well as the idle period 220. The collected traces include an idle period 220 in which no operation is performed, and the idle period 220 is an interval in which no analysis is required, so that the collected traces may include unnecessary data.

The transaction extraction device according to one embodiment may remove the idle period 220 from the collected trace. Since the idle period 220 is removed, the capacity of the memory (or buffer) for storing the trace can be saved. Furthermore, since the transaction extractor can transmit less capacity traces to the host, the channel utilization of the channel interface can be reduced.

3 is a diagram illustrating a structure of a transaction extraction apparatus 300 according to an embodiment of the present invention. Referring to FIG. 3, the transaction extraction apparatus 300 according to an exemplary embodiment may be connected to a bus 310 connecting a host and a memory, thereby collecting traces. In addition, the transaction extraction device 300 may be coupled to the channel interface 320 to transmit the collected traces to the host.

3, the transaction extracting apparatus 300 may include a trace analyzing unit 301 connected to a bus, a time stamp generating unit 302, and a trace collecting unit 303.

Referring to FIG. 3, the transaction extracting apparatus 300 may include a transaction collecting unit 303 for collecting traces between the host and the memory. The trace collection unit 303 may include a memory element or buffer to store the trace. Since the trace collecting unit 303 collects traces, it can store traces in a first-in first-out (FIFO) manner.

If the memory is an eMMC, the protocol transmitted between the host and the memory may be transmitted at a rate of either SDR (Single Data Rate) or DDR (Double Data Rate). The trace collection unit 303 can detect the transmission rate (SDR or DDR) of the protocol, and then collect traces based on the transmission rate. Furthermore, the trace collection unit 303 may store the traces transmitted to the SDR and the traces transmitted to the DDR in different memories.

Referring to FIG. 3, the transaction extracting apparatus 300 may include a time stamp generating unit 302 for generating a time stamp corresponding to a start time and an end time of a transaction. The transaction extracting apparatus 300 may remove the idle period from the collected trace. The transaction extracting apparatus 300 may store time information on an idle period or time information on a transaction in a trace using the time stamp generated by the time stamp generating unit 302. [

The time stamp generating unit 302 may collect the clock of the host and the clock of the memory via the bus in order to generate the time stamp. Since the memory generates a variable clock, the clock of the memory may not contain information about the absolute time. The time stamp generating unit 302 can know the absolute time based on the clock of the fixed host.

In addition, the time stamp generator 302 may count the clock of the memory and measure the clock speed of the memory in real time. Specifically, the time stamp generating unit 302 may reduce the clock speed of the memory in order to sample the clock of the memory according to the clock of the host. According to one embodiment, the time stamp generator 302 can convert a clock of a memory of 50 MHz to a signal of 12.5 Mhz by reducing the clock speed by four. The time stamp generating unit 302 can sample the clock of the converted memory according to the clock of the host. The time stamp generating unit 302 may count a count of 1 or 0 in the sampled signal.

When the speed of the clock of the memory is reduced by n times, the time stamp generator 302 generates a clock of the memory based on the count a obtained by sampling the host clock x Hz and the clock of the memory whose speed has decreased in accordance with the clock of the host Can be calculated. The time stamp generating unit 302 can calculate the clock of the memory based on Equation (1).

For example, referring to Equation 1, if the clock of the host is 200 MHz and the speed of the clock of the memory is reduced by 4, if the count obtained by sampling the clock of the memory converted according to the clock of the host is 8, It can be seen that the clock of the memory is 100 MHz.

The time stamp generating unit 302 can output the time stamp in a 64-bit format. Specifically, the time stamp generating unit 302 can output the time stamp based on the format shown in Table 1.

beat name value 63 Timestamp flag 1: Timestamp format 62-61 Bus width 11: 8 bit data bus
10: 4 bit data bus
01: 1 bit data bus
00: default 60-59 Data rate (based on CMD6) 11: HS400
10: HS200
01: High Speed (52MHz)
00: Selecting backwards compatibility interface timing 59-48 Sampling speed mode 47 The effective bit of the amount of change in the clock cycle of the memory 1: Valid
0: Invalid 46-32 Amount of change in memory clock cycle The length of the idle interval based on the clock of the memory (from the end of the previous transaction to the start of the next transaction) 31-0 Timestamp (Wall clock) The clock of the host

Referring to FIG. 3, the transaction extracting apparatus 300 may include a trace analyzing unit 301 for discriminating an idle period and a transaction. The trace analyzing unit 301 can analyze the collected trace in real time by analyzing the 1-bit command line of the bus. Since the trace can be analyzed in real time, the trace analyzing unit 301 can distinguish the idle period and the transaction in real time.

Further, the trace analyzing unit 301 can track the internal state of the transaction (for example, whether a data block is being transmitted) in real time. The trace analysis unit 301 may include a finite-state machine (FSM). The state of the FSM can be changed based on the internal state of the transaction, and the trace analysis unit 301 can analyze the collected protocol or suspend the analysis (delay) according to the data block based on the state of the FSM .

The trace analyzing unit 301 according to an embodiment can transmit the analyzed result to the trace collecting unit 303. [ For example, the trace analyzing unit 301 may detect the data transfer rate (whether SDR or DDR) and then transmit the detected result to the trace collecting unit 303. [ Therefore, the trace collection unit 303 can collect the trace according to the data transmission rate.

The trace analyzing unit 301 according to an embodiment can adjust the switch 305 according to a result of classifying the idle period and the transaction. Accordingly, the trace analyzing unit 301 can determine whether a time stamp or a collected trace is to be transferred to the transaction storage unit 304. [

When the trace analyzing unit 301 identifies the idle period, the time stamp may be transmitted to the transaction storage unit 304. [ Therefore, the trace for the idle period is not stored in the transaction storage 304. [ When the trace analyzing unit 301 identifies a transaction, the collected trace may be transmitted to the transaction storage unit 304. [ Accordingly, the transaction storage unit 304 can store the transaction.

Referring to FIG. 3, the transaction extracting apparatus 300 may include a transaction storing unit 304 for extracting the transaction other than the idle period and storing the extracted transaction together with the time stamp. The transaction storage 304 may include a memory or buffer for storing transactions. The transaction storage unit 304 may store a transaction with a time stamp in a FIFO manner.

The transaction storage unit 304 may transmit the stored trace to the analysis host through the channel interface 320. [ The analysis host can analyze the received trace using analysis software. The transaction storage unit 304 may convert the trace into a form that can be easily analyzed by the analysis software and store the trace.

4 is a diagram illustrating a structure of a trace analysis unit 400 according to an embodiment of the present invention. The transaction extracting apparatus may include a trace analyzing unit 400 for separating the idle period and the transaction from the trace. Referring to FIG. 4, the trace analyzing unit 400 can receive a trace through the bus 410.

Referring to FIG. 4, the trace analyzing unit 400 may include a command detecting unit 401 for identifying a command signal or a response signal included in the trace. The command detection unit 401 can identify a command signal or a response signal by analyzing a command line of one bit among a plurality of lines included in the bus. When the memory is eMMC, since the command signal has a size of 48 bits, the command detecting unit 401 can collect a 1-bit command line in a 48-bit shift register.

According to one embodiment of the present invention, the command detection unit 401 can detect the type of command signal or response signal and the state of the memory included in the command signal. That is, the command detecting unit 401 can detect the parameters included in the command signal when the command signal includes a parameter for setting or changing the state of the memory. In addition, the command detection unit 401 can transmit the detected result to the transaction detection unit 402.

For example, in an embodiment where the memory is an eMMC, the command detector 401 may detect the bus width, the data transfer rate (SDR or DDR) included in the CMD6 signal when the CMD6 signal, And the data transfer mode of the memory. The command detection unit 401 can transmit the detection result to the transaction detection unit 402. According to one embodiment, the command detection unit 401 may transmit the data transmission rate to the trace collection unit.

According to an embodiment of the present invention, the command detection unit 401 may be implemented as an FSM. Based on the type of the command signal or the response signal, the command detection unit 401 can adjust its own state. In each state, the command detection unit 401 can identify the command signal or the response signal by performing an operation corresponding to the state.

Referring to FIG. 4, the trace analysis unit 400 may include a transaction detection unit 402 that identifies the start and end of a transaction based on a command signal or a response signal. The transaction detection unit 402 can identify the type and detailed operation of the transaction according to the type of the command signal or the type of the response signal transmitted by the command detection unit 401. [

The transaction detection unit 402 can control the transaction storage unit based on the type and detailed operation of the detected transaction. Specifically, the transaction detection unit 402 can notify the transaction storage unit of a signal to store the current trace. When the transaction detection unit 402 identifies that the current trace is the idle period, it transmits a signal to the transaction storage unit to inform that the current trace is the idle period. In this case, the transaction storage unit may not store the trace corresponding to the idle period.

According to an embodiment of the present invention, the transaction detection unit 402 may be implemented as an FSM. Based on the type and detailed operation of the identified transaction, the transaction detection unit 402 can adjust its state. The transaction detection unit 402 can, in each state, perform an operation corresponding to the state, thereby tracking the type of transaction and the detailed operation.

For example, assume that the transaction detection unit 402 detects that an operation of writing a plurality of data blocks will be performed. Since it is clear that the state of the transaction will not change while a plurality of data blocks are transferred, the transaction detection unit 402 can stop the detection while a plurality of data blocks are transferred. The transaction detection unit 402 can resume detection when the transfer of the data block is completed.

Hereinafter, an embodiment in which the instruction detection unit and the transaction detection unit of the present invention are implemented by the FSM will be described. To explain the concrete state, it is assumed that the memory is eMMC, and the host and the memory transmit the command signal, the response signal and the data block based on the eMMC standard established by Joint Electron Device Engineering Council (JEDEC). In this case, the command detection unit and the transaction detection unit may include a state corresponding to the kind of the command signal defined in accordance with the eMMC standard and the type of the response signal.

It should be apparent to those of ordinary skill in the art that although the memory is an eMMC embodiment only, the present invention can be applied to other types of memory. In addition, while only the embodiments in which the instruction detection unit and the transaction detection unit of the present invention are implemented by the FSM are described, it will be apparent to those skilled in the art that the present invention can be implemented using other types of devices.

5 is a state diagram of the command detection unit according to an embodiment of the present invention. Hereinafter, the operation of the command detection unit will be described in detail with reference to each state of FIG.

Referring to FIG. 5, when the transaction extracting apparatus is initially started or reset, the instruction detecting unit is in the INITIAL state. In the INITIAL state, the command detection unit initializes all output signals or delay counts. The command detection unit may include a delay count. The command detection unit may include, based on the delay count, for suspending the identification of the command signal or the response signal for a predetermined period of time. The instruction detector moves from the next memory clock to the IDLE state.

Referring to FIG. 5, in the IDLE state, the command detection unit can determine the type of the collected trace. The instruction detection unit discriminates whether the collected trace is a command signal or a response signal based on a shift register that collects a 1-bit command line (bits stored in a specific area [39: 0] of the shift register when the memory is eMMC) can do. When the collected trace is a command signal, the command detecting unit may move to different states (CMD_16, COMMAND, CMD_23, CMD_6, and the like) according to the type of the command signal. If the collected trace is a response signal, the command detection unit can move to the RESPONSE state.

Referring to FIG. 5, the command detection unit can move to the CMD_16 state when the collected trace is a command signal (CMD16 signal in the case of eMMC) for the length of the data block. In the CMD_16 state, the command detection unit can identify the length of the data block included in the command signal. For example, the length of a data block can be identified from a specific area of the shift register (in the case of an eMMC, a bit stored in [31: 0]) and then stored in a specific variable. For convenience of explanation, it is assumed that the length of the data block identified by the command detection unit is stored in the variable name blk_len_tmp.

Referring to FIG. 5, the command detection unit can move to the CMD_23 state when the collected trace is a command signal (CMD23 signal in the case of eMMC) for the number of data blocks. In the CMD_23 state, the command detection unit can identify the number of data blocks included in the command signal. For example, the length of a data block can be identified from a specific area of the shift register (in the case of an eMMC, a bit stored in [15: 0]) and then stored in a specific variable. For convenience of explanation, it is assumed that the number of data blocks identified by the command detection unit is stored in the variable name blk_count_tmp.

Referring to FIG. 5, the command detection unit can move to the CMD_6 state when the collected trace is the command signal (CMD6 signal in the case of eMMC) for the bus width, the data transfer rate, and the data transfer mode of the memory. The host can transfer the state of the memory, such as the bus width, the data transfer rate, and the data transfer mode of the memory, to the memory using one command signal.

In the CMD_6 state, the command detection unit can identify the bus width, the data transfer rate, and the data transfer mode of the memory included in the command signal. The instruction detection unit can check whether the memory accesses a specific register (eMMC, HS_TIMING [185] and BUS_WIDTH [183]) in the memory to identify the three parameters.

Some kinds of command signals (CMD2, CMD9, CMD10 in the case of eMMC) may carry the same kind of response signal (R2 response). Referring to FIG. 5, the command detection unit can move to one state (CMD_2_9_10 state) when this command signal is detected. In the CMD_2_9_10 state, the command detection unit can set the delay count of the RSP DELAY state by the number of clocks of the response signals accompanied by these command signals.

A specific command signal (CMD0 in the case of eMMC) may not carry a response signal. Referring to FIG. 5, if the command detection unit identifies a command signal that does not involve a response signal, it can move to the CMD_0 state. In the CMD_0 state, the command detector can set the delay count to immediately terminate the RSP DELAY state.

The command detection unit can move to the COMMAND state when the remaining command signals except for the command signal described above are detected. In the COMMAND state, the command detection unit can detect the type of command signal. Further, the command detection unit can detect the size of the response signal based on the type of the command signal.

In the CMD_16, COMMAND, CMD_23, CMD_6, CMD_2_9_10 and CMD_0 states, the command detection unit can proceed to the CMD_DELAY state when the above described operation is completed or the next clock is input. Since the interpretation of the command signal in the previous state is completed, the command detection unit can stay in the CMD_DELAY state for the number of clocks in which the entire command signal is received. The length of the entire command can be 48 bits, in which case the command detector can stay in the CMD_DELAY state while the 48-bit command signal is being input (can stop progressing to the next step).

The command detection unit can stay in the CMD_DELAY state by the number of clocks stored in the delay count. The delay count can be reduced each time a clock is input. The command detection unit can move to the IDLE state when the delay count becomes zero.

Referring to FIG. 5, in the RESPONSE state, the command detection unit can identify the type of the response signal and the length of the response signal. In the RESPONSE state, the command detection unit can transmit the kind of the identified response signal to the transaction detection unit. Further, the command detection unit can set the delay count based on the length of the response signal. At the next clock, the command detector can move to the RSP_DELAY state.

Referring to FIG. 5, the command detection unit can stay in the RSP_DELAY state by the length of the response signal. The command detection unit can stay in the RSP_DELAY state by the number of clocks stored in the delay count. For example, in the embodiment for the eMMC, if the response signal is R2 RESPONSE, it can stay in the RSP_DELAY state for 136 clocks. If the length of the response signal is 48 bits, it can stay in the RSP_DELAY state for 48 clocks. The command detection unit can move to the IDLE state when the delay count becomes zero.

6A to 6G are state diagrams of a transaction detection unit according to an embodiment of the present invention. For convenience of explanation, the state of the transaction detection unit will be described with reference to FIGS. 6A to 6G. The states having the same names in FIGS. 6A to 6G (for example, the INITIAL state and the IDLE state) mean the same state.

6A to 6G, when the transaction extracting apparatus is initially started or reset, the transaction detecting unit becomes INITIAL. In the INITIAL state, the transaction detector initializes all output signals or delay counts. The transaction detector moves from the next memory clock to the IDLE state.

6A to 6G, in the IDLE state, the transaction detection unit can move to the next state corresponding to the type of command signal that the command detection unit identified. The transaction detection unit can identify the type of command signal by receiving the type of command signal from the command detection unit or by detecting the state of the command detection unit.

Referring to FIG. 6A, in the IDLE state, the transaction detection unit can move to the CMD_0 state when the collected command signal is a command signal that does not involve a response signal. In the CMD_0 state, the transaction detection unit can set the delay count based on the length of the command signal.

The transaction detector may move to the CMD_0_COUNT state at the next clock and stop tracking the state of the transaction while the command signal is being input. That is, the transaction detection unit can maintain the CMD_0_COUNT state until the delay count becomes zero. When the delay count reaches 0, the transaction detector moves to the IDLE state again.

Referring to FIG. 6B, in the IDLE state, the transaction detection unit can move to the CMD_RSP_TRANS state when the acquired command signal is a command signal accompanying a response signal. In the CMD_RSP_TRANS state, the transaction detection unit can set the delay count based on the length of the command signal. The transaction detector can move to the CMD_RSP_TRANS_COUNT state at the next clock. The transaction detector can stay in the CMD_RSP_TRANS_COUNT state for as long as the set delay count. The transaction detector moves to the WAIT_RSP_EN state when the delay count is zero.

Referring to FIG. 6B, in the WAIT_RSP_EN state, the transaction detection unit can wait for a response signal of the memory. When the command detection unit identifies the response signal, it can notify the transaction detection unit that the response signal has been received. In this case, the transaction detection unit can identify the type and length of the response signal based on the information delivered by the command detection unit. The transaction detection unit may set the delay count based on the length of the response signal. In addition, the transaction detection unit can move to the RSP_48_COUNT state or the RSP_136_COUNT state based on the length of the response signal.

The transaction detector moves to the RSP_48_COUNT state if the response signal is 48 bits long. The transaction detector moves to the RSP_136_COUNT state if the response signal is 136 bits long. The transaction detection unit can stay in the RSP_48_COUNT state or the RSP_136_COUNT state by the length of the corresponding response signal. Referring to FIG. 6B, in the RSP_136_COUNT state, the transaction detection unit can move to the IDLE state when the delay count becomes zero. In the RSP_48_COUNT state, when the delay count becomes zero, the transaction detection unit can move to the next state based on the type of command signal.

Referring to FIG. 6C, when a command signal including the number of data blocks is input, the transaction detector may interpret the command signal to identify how many data blocks are to be transmitted. The transaction detection unit can move to the CMD_BLK_COUNT state when the command detection unit receives the command signal (CMD23 signal in the case of eMMC) for the number of data blocks. In the CMD_BLK_COUNT state, the transaction detector can identify the number of data blocks and store them in a specific variable. The transaction detector can move to the CMD_RSP_TRANS_COUNT state upon completion of storage. The transaction detector may remain in the CMD_RSP_TRANS_COUNT state while the command signal is received.

Referring again to FIG. 6B, the transaction detector may move to the next state based on the type of command signal and the number of data blocks to be transmitted, when RSP_48_COUNT is ended. When the command signal is a signal for writing one data block, the transaction detection unit can wait for a time period in which one data block is transmitted. When the command signal is a signal for writing a plurality of data blocks, the transaction detection unit can wait for a time period in which a plurality of data blocks are transmitted.

FIG. 6D is a state diagram showing a state change after the RSP_48_COUNT state of the transaction detection unit in a situation where the host writes one data block to or from the memory. FIG.

Referring to FIG. 6D, in the RSP_48_COUNT state, the transaction detection unit can identify the type of command signal. The transaction detection unit can move to the SINGLE_READ_WAIT_BUS_START state when the command signal is a signal (CMD17 in the case of eMMC) from which one data block is fetched from the memory. The transaction detection unit can move to the SINGLE_WRITE_WAIT_BUS_START state when the command signal is a signal (CMD24 in the case of eMMC) that writes one data block to the memory.

The transaction detection unit can confirm the starting point of the data line based on the bus width that has been identified in the SINGLE_READ_WAIT_BUS_START state or the SINGLE_WRITE_WAIT_BUS_START state. In addition, the transaction detector may update the length of the data block. The transaction detector may update the delay count based on the length of the data block and the bus width. Referring to FIG. 6D, each of the transaction detectors can move to the SINGLE_READ_BLK_COUNT state or the SINGLE_WRITE_BLK_COUNT state.

The transaction detection unit may remain in the SINGLE_READ_BLK_COUNT state from the time when the memory starts transferring the data block to the time when the transfer of the data block is completed. The transaction detection unit can maintain the SINGLE_READ_BLK_COUNT state based on the updated delay count in the SINGLE_READ_WAIT_BUS_START state. The transaction detection unit can move to the LAST_READ_BLOCK_DELAY state when the delay count becomes zero.

The transaction detector can operate in the SINGLE_WRITE_BLK_COUNT state, similar to the SINGLE_READ_BLK_COUNT state. That is, the transaction detector may remain in the SINGLE_WRITE_BLK_COUNT state while the data block is being transferred, and may move to the LAST_WRITE_BLOCK_DELAY state when the delay count is zero.

The transaction detector can wait until the next command signal is received in LAST_READ_BLOCK_DELAY state or LAST_WRITE_BLOCK_DELAY state. When the command detection unit notifies the transaction detection unit that the next command signal has been received, the transaction detection unit can move to the next state based on the type of the received command signal.

6E is a state diagram showing a state change after the RSP_48_COUNT state of the transaction detection unit in a situation where the host writes a plurality of predetermined data blocks to the memory or fetches a predetermined plurality of data blocks from the memory.

FIG. 6F is a state diagram showing a state change after the RSP_48_COUNT state of the transaction detection unit in a situation where a host writes a plurality of unspecified data blocks into a memory, or a plurality of unspecified data blocks are fetched from a memory.

Referring to FIGS. 6E to 6F, in the RSP_48_COUNT state, the transaction detection unit can identify the type of command signal. The transaction detection unit can identify whether the command signal is a signal (CMD18 in the case of eMMC) that fetches a plurality of data blocks from the memory. In this case, the transaction detection unit can identify the number of data blocks in the command detection unit. The transaction detector can move to the MP_READ_WAIT_PRE_BUS_START state if the number of data blocks is predetermined. The transaction detector can move to the MP_READ_WAIT_OPEN_BUS_START state if the number of data blocks is not specified.

The transaction detection unit can identify whether the command signal is a signal (CMD25 in the case of eMMC) that writes a plurality of data blocks to the memory. In this case, the transaction detector can identify the number of data blocks, similar to the case where a data block is fetched from memory. The transaction detection unit can move to the MP_WRITE_WAIT_PRE_BUS_START state when the number of data blocks is predetermined. The transaction detector can move to the MP_WRITE_WAIT_OPEN_BUS_START state if the number of data blocks is not specified.

Referring to FIG. 6E, the transaction detection unit can confirm the starting point of the data line based on the bus width, in the MP_READ_WAIT_PRE_BUS_START state or the MP_WRITE_WAIT_PRE_BUS_START state. The transaction detector may update the length of the data block and then move to the MP_READ_1 BLK_LEN_PRE_COUNT state or the MP_WRITE_1 BLK_LEN_PRE_COUNT state, respectively.

Referring to FIG. 6E, the transaction detection unit can remain in the MP_READ_1 BLK_LEN_PRE_COUNT state or the MP_WRITE_1 BLK_LEN_PRE_COUNT state, while one data block is transmitted through the bus. The transaction detection unit can move to the MP_READ_BLK_COUNT state or the MP_WRITE_BLK_COUNT state when the transmission of one data block is completed.

Referring to FIG. 6E, the transaction detection unit can remain in the MP_READ_BLK_COUNT state or the MP_WRITE_BLK_COUNT state until all the data blocks are transferred. The transaction detection unit can identify the number of data blocks from the command signal (CMD23 in the case of eMMC) related to the number of data blocks identified by the command detection unit. Each time a data block is transmitted, the transaction detection unit may reduce the counter storing the number of identified data blocks by one. Therefore, when the counter becomes 0, the transaction detection unit can confirm that the transmission of the data block is completed.

Referring to FIG. 6E, in the MP_WRITE_BLK_COUNT state, the transaction detection unit can move to the DEVICE_BUSY state or the LAST_WRITE_BLOCK_DELAY state when the transmission of the data block is completed. The transaction detection unit can move to the DEVICE_BUSY state when a block of data is written after the transfer of the data block received by the memory is completed. The transaction detection unit can wait in the DEVICE_BUSY state until the memory completes writing the data block. The transaction detection unit can check whether the memory has completed the recording of the data block every preset period.

The transaction detection unit can move to the LAST_READ_BLOCK_DELAY state or the LAST_WRITE_BLOCK_DELAY state as described in FIG. 6D when the transmission of the data block is completed, or when the memory completes the recording of the data block.

Referring to FIG. 6F, when the transaction detector moves to the MP_READ_WAIT_OPEN_BUS_START state or the MP_WRITE_WAIT_OPEN_BUS_START state, it is possible to confirm whether the data block transfer has started. The transaction detection unit can move to the MP_READ_1BLK_OPEN_COUNT state or the MP_WRITE_1BLK_OPEN_COUNT state, respectively, when the transmission of the data block is started.

Referring to FIG. 6F, the transaction detection unit can stay in the MP_READ_WAIT_OPEN_BUS_START state or the MP_WRITE_WAIT_OPEN_BUS_START state while one data block is transmitted, based on the length of the previously identified data block. When the transfer of one data block is completed, the transaction detection unit can detect whether the transfer of all the data blocks is completed. If the transfer has not been completed, the transaction detection unit can move again to the MP_READ_WAIT_OPEN_BUS_START state or the MP_WRITE_WAIT_OPEN_BUS_START state, and then identify whether the transfer of the next data block has started. The transaction detection unit can move to the CMD_BLK_COUNT state when the transmission of the data block is completed.

The host can instruct the memory to abort all operations (CMD12 for eMMC). The command detection unit can notify the transaction detection unit when receiving a command signal to interrupt all operations. Referring to FIG. 6G, in this case, the transaction detection unit can move to the CMD_RSP_TRANS state in any state.

7 is a flowchart illustrating an operation performed by the transaction extracting apparatus according to an embodiment of the present invention.

At step 710, a transaction extraction device according to one embodiment may collect traces between the host and memory. The transaction extractor may store the collected traces in a first-in first-out manner. The traces collected by the transaction extractor may include the clock of the host and the clock of the memory as well as the command signal, the response signal, and the data block.

In step 720, the transaction extraction device according to one embodiment can distinguish the idle period and the transaction from the trace.

More specifically, in step 721, the transaction extraction device may identify the command and response signals in the collected trace. The transaction extraction device can detect the data transfer rate, the bus width, the length of the data block, the number of data blocks, or the data transfer mode of the memory included in the command signal, based on the type of the command signal.

In step 722, the transaction extraction device may track the status of the transaction based on the type of command signal or the type of response signal. In other words, the transaction extractor can track how much data is exchanged between the host and the memory in real time, or whether the transfer of data has been completed.

In step 730, the transaction extraction device according to one embodiment may generate a timestamp for the start and end points of the transaction. The transaction extractor may generate a timestamp based on the format of Table 1. Further, the transaction extracting apparatus can calculate the clock speed of the memory by sampling the clock of the memory based on the clock of the host.

At step 740, a transaction extraction device according to one embodiment may store a transaction with a timestamp. The transaction extractor may store the transaction in a first-in first-out manner. The transaction extraction device can convert the transaction into a form that can be easily analyzed by the analysis software. The transaction extractor can convert the transaction into a user-readable form and store it. The transaction extraction device can transmit the stored transaction and time stamp to the host through the channel interface.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA) , A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

100: Host
101: Host controller
102: Analysis Software
110: Memory
111: Device controller
112: memory array
120: Transaction extractor
130: bus
140: Channel interface

Claims (16)

A trace collector for collecting traces between the host and the memory;
A trace analyzer for analyzing the trace to distinguish the idle section and the transaction;
A time stamp generator for generating a time stamp including the idle period and the time information for the transaction; And
A transaction storage unit for extracting the transaction other than the idle period in the trace and storing the extracted transaction together with the time stamp;
Lt; / RTI >
The trace-
Detecting a data rate of a protocol transmitted between the host and the memory, collecting the trace according to the detected data rate,
The transaction storage unit stores,
Storing the transaction extracted from the collected traces together with the time stamp in different memories according to the data rate,
Wherein the time information for the transaction includes a start time and an end time of the transaction indicated according to the clock of the host,
Wherein the time information on the idle period includes a length of the idle period indicated by using a change amount of a clock cycle of the memory
Transaction extractor. The method according to claim 1,
The trace analyzing unit,
A command detection unit for identifying a command signal or a response signal included in the trace;
Based on the command signal or the response signal, a transaction detection unit
And a transaction extractor. 3. The method of claim 2,
The command detection unit detects,
Wherein the command signal identifies the data transfer rate of the transaction and the bus width of the transaction. delete 3. The method of claim 2,
The transaction detection unit detects,
Based on the command signal, detecting the number and length of data blocks in the trace,
And identifying a section in which the data block is transmitted based on the number and length of the data blocks. The method according to claim 1,
The time stamp may include:
A clock of the host, a clock of the memory, a speed of the clock of the memory, and a data transfer rate of the transaction. The method according to claim 1,
Wherein the time stamp generator comprises:
And detects the speed of the clock of the memory based on the clock of the host. The method according to claim 1,
The transaction storage unit stores,
And outputting the stored transaction and the time stamp through a channel interface. A command detection unit for identifying a command signal or a response signal included in a trace between the host and the memory; And
Based on the command signal or the response signal, a transaction detection unit
Lt; / RTI >
The command detection unit detects,
Identifying a length of a data block from the command signal using a shift register coupled to the bus connecting the host and the memory,
The transaction detection unit detects,
Adjusting a state of the transaction detection unit in response to the state of the transaction based on the command signal or the response signal,
Update the delay count based on the length of the identified data block, and stop adjusting the state of the transaction detector while the delay count is decreasing
Trace analysis device. delete delete 10. The method of claim 9,
The transaction detection unit detects,
And outputs a signal for storing the transaction in accordance with the start and end of the transaction. A transaction extracting method performed by a transaction extracting apparatus,
Collecting traces between a host and a memory coupled to the transaction extraction device;
Analyzing the traces to distinguish between idle periods and transactions;
Generating a timestamp corresponding to a start time and an end time of the transaction; And
Extracting the transaction other than the idle section from among the traces and storing the extracted transaction together with the time stamp
Lt; / RTI >
Wherein the collecting comprises:
Collecting the trace according to a data rate of a protocol transmitted between the host and the memory,
Wherein the storing step comprises:
Storing the transaction extracted from the trace together with the timestamp in a memory corresponding to the data rate
Transaction Extraction Method. 14. The method of claim 13,
The step of distinguishing the idle period and the transaction comprises:
Identifying a command or response signal included in the trace; And
Based on the command signal or the response signal, detecting the start and end of the transaction
/ RTI > 14. The method of claim 13,
The transaction extracting method includes:
Outputting the stored transaction and the timestamp through a channel interface
Further comprising: A computer-readable recording medium on which a program for executing the method of any one of claims 13 to 15 is recorded.

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