KR101715084B1 - Apparatus and method for equalizer smapling error in wireless communication system - Google Patents

Abstract

An apparatus for eliminating equalizer sampling errors in a wireless communication system includes: a rake receiver that performs path-by-path synchronization tracking for multipath; a sampling controller that determines a sampling location based on the path- There is an advantage of including a sampling selector that selects sampling data based on the sampling position, thereby reducing the sampling error without increasing the filter tap.

Description

[0001] APPARATUS AND METHOD FOR EQUALIZER SMAPING ERROR IN WIRELESS COMMUNICATION SYSTEM [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to linear equalizers and, more particularly, to an apparatus and method for eliminating equalizer sampling errors in a wireless communication system.

An optimal receiver for eliminating inter-symbol interference (ISI) is known as an MLSE (Maximum Likelihood Sequence Estimation) receiver, but its implementation is difficult due to its high complexity. Therefore, a linear equalizer or a linear-feedback equalizer that is easy to implement is used. However, when a linear equalizer using an adaptive algorithm is used for wireless communication, there is a disadvantage that performance is degraded in a fast fading environment. In general, training data required for the adaptive algorithm is transmitted periodically. If the channel change is larger than the period, the adaptive algorithm fails to track the channel change and deteriorates receiver performance.

On the other hand, in the Korean patent application (Application No. 10-2008-0057722), the adaptive equalization algorithm using statistical signal regeneration is applied to a code division multiple access (CDMA) (e.g., High Speed Packet Access (HSPA) and performs a function of equalizing the channel of each chip. In the technique of equalizing the chip unit channel, hardware composed of many filter taps is required to improve the performance. In this case, rather than increasing hardware due to the increase in the amount of data input to the equalizer, the input data is adjusted to more optimal data to improve performance. In other words, if an N-tap equalizer is implemented, an arbitrary signal is passed through a filter using N channel responses obtained from the channel estimator as a filter coefficient, thereby generating a statistical signal statistically equivalent to the received signal of the terminal. A Leaky adaptation algorithm is used with the statistical signal and a desired signal to obtain a coefficient value of N taps to be used in a main filter and then a coefficient value of the N taps is used And restores the signal. In other words, an equalizer in a system having input information on a chip basis performs channel estimation in a unit of 1 / 2T _c , and uses the channel estimation value as a leakage adaptive algorithm to calculate a coefficient of a finite impulse response (FIR) And performs channel compensation.

Meanwhile, HS-PDSCH (High Speed Physical Downlink Shared CHannel) is used to process high-speed data in a WCDMA (Wideband Code Division Multiple Access) / HSPA system. The HS-PDSCH uses a QPSK, 16QAM, and 64QAM modulation scheme.

However, when data is sampled by the A / D converter during high-speed data transmission using the 64QAM modulation scheme, it may not operate at an appropriate sampling position due to influence of external channel change or timing drift . Also, if data sampling is not performed at an appropriate sampling location, performance degrades in chip-based equalizer architecture. In other words, unless the equalizer having a 1 / 2T _c interval of taps receives an optimal sampling value located in the middle of the taps as an input, a channel estimation error occurs for this value, and channel compensation is not performed correctly The bit error rate (BER) is increased. To prevent this, it is necessary to increase the tap to 1 / 4T _c or less, but the computation amount (hardware size) increases to twice.

Accordingly, there is a need for an apparatus and method for reducing sampling errors without increasing filter taps when channel equalization is performed on a chip-by-chip basis during high-speed data transmission and reception.

It is an object of the present invention to provide an apparatus and method for channel compensation in a wireless communication system.

It is another object of the present invention to provide an apparatus and method for eliminating equalizer sampling errors in a wireless communication system.

According to a first aspect of the present invention, there is provided an apparatus for eliminating an equalizer sampling error in a wireless communication system, the apparatus comprising: a rake receiver for performing path- A sampling controller for determining a sampling position based on the synchronization trace, and a sampling selector for selecting sampling data based on the determined sampling position.

According to a second aspect of the present invention, there is provided a method for eliminating an equalizer sampling error in a wireless communication system, the method comprising: performing path- Determining a sampling position based on the tracking, and selecting sampling data based on the determined sampling position.

As described above, there is an advantage in that the sampling error can be reduced without increasing the filter tap by receiving the necessary timing displacement information from the rake receiver and adjusting the sampling value input to the equalizer.

1 is a block diagram of an equalizer sampling error eliminator in a wireless communication system according to an embodiment of the present invention,
2 is a functional block diagram of a detailed sampling controller 110 according to an embodiment of the present invention,
3 is a flowchart illustrating a method of removing an equalizer sampling error in a wireless communication system according to an embodiment of the present invention,
4 is a flow chart for sampling position adjustment according to an embodiment of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with respect to an apparatus and a method for removing an equalizer sampling error in a wireless communication system.

Particularly, in the present invention, performance degradation due to sampling error of an ADC (Analog to Digital Converter) of a chip-based equalizer applied to a HSPA (High Speed Packet Access) system is reduced, Performance is guaranteed even in modulation and demodulation. Further, the present invention minimizes the external sampling error occurring in the equalizer, and implements the minimum amount of computation, instead of increasing the tap.

In the present invention, a rake receiver that assures optimum performance in low-speed data transmission in a CDMA (Code Division Multiple Access) receiver is used, and a dual receiver that uses an equalizer for high- Structure. Rake receivers each have a fingering path by path, and the finger includes a time tracker that compensates for timing displacement to actively adapt to the displacement of each path. In contrast, the equalizer is designed in a direction that minimizes interference between input symbols in the entire received signal rather than in each path. However, it is affected by external sampling displacements.

Accordingly, in the present invention, in a system in which a rake receiver and an equalizer are configured in the form of a dual receiver, the sampling displacement of the equalizer is removed using a result of a synchronization track (Time Tracker) in a rake receiver, .

FIG. 1 illustrates an equalizer sampling error removal apparatus in a wireless communication system according to an embodiment of the present invention.

1, the apparatus includes a filter 100, an interpolator 102, a decimator 0 104_2 to a decimator n 104_n, a finger zero sync trace 106_1 to a finger n sync trace 106_n, A path selector 108, a sampling controller 110, a sampling selector 112, an equalizer 114, a MIMO demodulator, and a decoder.

The filter 100 filters a signal converted from an analog signal into a digital signal so as not to cause Inter-symbol Interference (ISI), thereby making the signal suitable for channel transmission. For example, the filter 100 filters a signal converted from an analog signal to a digital signal using a square-root raised cosine (SRRC) filter.

The interpolator 102 estimates sample data between two sample data using the interpolation method. For example, the 1: 8 ratio interpolator 102 outputs 8 sample data when one sample data from the filter 100 is input.

The decimator 0 (104_2) to the decimator n (104_n) each function as a low-pass filter for canceling aliasing on the corresponding path, and the finger zero sync tracker (106_1) to the finger n sync tracker 106_n, and selects one of the M samples and discards the remaining M-1 samples.

The finger zero sync tracker (106_1) to the finger n sync tracker (106_n) perform time tracking on the corresponding path through a first loop, and the sync tracking result is used to adjust the decimation timing It is used as a metric. In other words, the timing information provided from the finger 0 sync tracker 106_1 to the finger n sync tracker 106_n is used as a metric for adjusting the decimation timing in the decimator 0 (104_2) to the decimator 104_n . Further, in addition to the present invention, the timing information is provided to the sampling controller 110 under the control of the path selector 108, and the sampling controller 110 accumulates the timing information to determine a sampling position.

Herein, the filter 100, the interpolator 102, the decimator 0 104_2 to the decimator n 104_n, and the finger zero synchronization trace 106_1 to the finger n synchronization trace 106_n Includes a rake receiver.

As described above, the principle of the RAKE receiver is that a one-bit signal is divided into a plurality of chips by spread spectrum. The transmitted signal is received by a multipath phenomenon, where the multipath is set to the chip spacing here. By separating signals of different paths using PN codes, individual correlation values can be found for each path. This correlation value is added to all paths to determine the received bit. Frequencies larger than the time spread band in the frequency selective channel have different transmission environments. In other words, the signal bandwidth can be divided into several paths in units of time spread band, and if the reciprocal is taken, a signal having no correlation with each other appears at a period of 1 / W during the time spread period. In a rake receiver, it is possible to reduce a bad signal probability of fading by removing a chip interference by using a PN code in an independent signal appearing at a 1 / W cycle and adding a signal taken in several paths to determine a received signal.

The path selector 108 receives information on the synchronization of each finger of the rake receiver (Time Tracker) according to the selection mode. A first mode that operates basically in two modes and reflects all the timing information of the finger assigned to the serving cell among the plurality of fingers and a first mode that selects a reference finger among the fingers belonging to the serving cell and reflects the result There is a second mode.

The sampling controller 110 controls the optimal sampling position using the timing information of the corresponding finger from the path selector 108. A detailed description of the sampling controller 110 will be described with reference to FIG.

The sampling selector 112 selects optimal sampling data among the multiple sampling data values of the interpolator 102 based on the timing information accumulated from the sampling controller 110.

The equalizer 114 receives sampling data from the sampling selector 112 and performs channel compensation. The MIMO demodulator 116 processes the sampled data signal processed from the equalizer 114 for each of a plurality of transmission and reception antenna paths, and the decoder 118 converts the data into LLR (Log-Likelihood Ratio) units to perform decoding.

Figure 2 illustrates a detailed sampling controller 110 in accordance with an embodiment of the present invention.

2, the sampling controller 110 includes MUXs 201, 203 and 205 for outputting an input signal according to a control signal, AND gates 207, 209 and 221 for masking two input signals, OR gates 215 and 217 for performing an OR operation on the output values of the first detection unit 215 and the second detection unit 213, a first detection unit 215, a second detection unit 213, a reset unit 223, A counter 225, an increasing / decreasing counter 219, and an output unit 227.

Here, the sampling controller 110 performs operations according to external control signals (Finger Time Tracker Decrement Decision, HSTM_INT, HSTM_MODE, CELLn_FNG_MAP, HSTM_REF_CELL, Each Finger Indicator, HSTM_REF_FNG, Frame Reference) .

The Finger Time Tracker Decrement Decision and the Finger Time Tracker Increment Decision are timing control information from the corresponding sync trackers 106_1 to 106_n, indicating that the sampling timing is late or advanced (time advanced / retarded). The HSTM_INT is an initial value of the increment / decrement counter 219. The HSTM_MODE indicates whether to use the timing information of the multiple fingers allocated to the serving cell (HSTM_MODE = 0) or the timing information of the reference finger among the fingers belonging to the serving cell (HSTM_MODE = 1). CELLn_FNG_MAP and HSTM_REF_CELL are control signals indicating the number of fingers assigned to the serving cell when HSTM_MODE = 0. That is, the HSTM_REF_CELL indicates cell information of a serving cell, and CELLn_RNG_MAP indicates finger information allocated to a cell indicated by the HSTM_REF_CELL. For example, when the cell index is 1 to 7, and when 2, 3, and 7 fingers are assigned to the cell, the CELLn_FNG_MAP has {1000110}. The HSTM_REF_FNG and the Each Finger Indicator are control signals indicating a reference finger among the fingers allocated to the serving cell when HSTM_MODE = 1. That is, the HSTM_REF_CELL is control information indicating a reference finger, and the finger indicator turns on the finger indicated by the HSTM_REF_FNG among the fingers assigned to the serving cell and turns off the remaining fingers. The Frame Reference is frame reference information.

When the HSTM_MODE is selected to be '0', that is, when the timing information of the multiple fingers allocated to the serving cell in which the equalizer 114 among multiple fingers is used is used, the HSTM_REF_CELL control The information (CELLn_FNG_MAP) of the corresponding fingers is inputted to the MUX 201 according to the signal. The MUX 201 provides the information (CELLn_FNG_MAP) of the fingers to the MUX 205 according to the HSTM_REF_CELL control signal. On the other hand, when the HSTM_MODE is selected as '0', that is, when the timing information of the reference finger among the finger belonging to the serving cell is used, the finger indicator of the reference finger is inputted to the MUX 203 according to the HSTM_REF_FNG control signal . The MUX 203 provides a finger indicator of the reference finger to the MUX 205 and the AND gate 221 according to the HSTM_REF_FNG control signal.

The MUX 205 outputs information of a plurality of fingers from the MUX 201 to the inputs of the AND gates 207 and 209 when HSTM_MODE = 0, and when the HSTM_MODE = 1, And outputs the finger information to the input terminals of the AND gates 207 and 209.

The AND gates 207 and 209 perform AND operation of sampling timing information (timing advance / retard information) from the sync trackers 106_1 to 106_n and information about the corresponding finger from the MUX 205 And outputs the result to the first detection unit 211 or the second detection unit 213.

The first detection unit 211 determines whether the signal from the AND gate 207 is 0 or 1 and transmits the result to the OR gate 215. The second detection unit 213 detects the signal from the AND gate 209, 0 " or " 1 ", and transmits the result to OR gate 217. [

The OR gates 215 and 217 provide signals from the first detection unit 211 and the second detection unit 213 to the increase / decrease counter 219, respectively. That is, if the output value of the first detection unit 211 or the second detection unit 213 is 1, the OR gate 215 or 217 outputs the OR gate 215 Or the output value of the OR gate 215 or 217 is 0 when the output value of the first detection unit 211 or the output value of the second detection unit 213 is 0.

The increase / decrease counter 219 accumulates output values from the OR gates 215 and 217 for a predetermined period. For example, when one signal is input from the OR gate 215, that is, in case of time advance, -1 is added to the value of IncDecCounter (IncDecCnt). When one signal is input from the OR gate 217, that is, , and in case of time retard, +1 is added to the value of IncDecCounter (IncDecCnt).

The reset unit 223 outputs an accumulation period of HSTM_ACC_PERIOD and a periodic trigger signal from the frame counter 225 (for example, when one frame is 10 ms, a trigger signal occurs every 10 m) And provides the accumulation period information to the increment / decrement counter 219 based on the accumulation period information.

The output unit 227 compares the cumulative value of the increment / decrement counter 219 with "HSTM_TH_U" and "HSTM_TH_L" for each frame period determined by "HSTM_ACC_PERIOD" to adjust the sampling position.

3 is a flowchart illustrating a method of removing an equalizer sampling error in a wireless communication system according to an embodiment of the present invention.

Referring to FIG. 3, the filter 100 filters a signal converted from an analog signal to a digital signal in step 300 and converts the analog signal into a signal suitable for channel transmission. For example, the filter 100 filters a signal converted from an analog signal to a digital signal using a square-root raised cosine (SRRC) filter.

Thereafter, the interpolator 102 performs interpolation in step 302. That is, the interpolation method is used to estimate sample data between two sample data.

Thereafter, the decimators 304 perform a decimator for the corresponding path in step 304, respectively. That is, it performs a function of a low-pass filter for removing aliasing, and selects one of M samples and discards the remaining M-1 samples.

Then, the sync tracker 106 performs time tracking on the corresponding path in step 306, respectively.

Then, in step 308, the sampling controller 110 adjusts the sampling position using the time advance / time retard of the corresponding finger through the path selector 108. The operation related to the detailed sampling position adjustment will be described later with reference to FIG.

Thereafter, the equalizer 114 performs channel compensation based on the adjusted sampling position in step 310, and the MIMO demodulator processes the signal-processed data from the equalizer 114 for each of a plurality of transmission / reception antenna paths in step 314, The decoder 118 performs conversion in units of LLR (Log-Likelihood Ratio) in step 314 and performs decoding.

FIG. 4 shows a flow chart for sampling position adjustment according to an embodiment of the present invention.

Referring to FIG. 4, in step 400, the sampling controller 110 determines a path selection mode, and when it is the first mode using the timing information of the fingers allocated to the serving cell, the CELLn_FNG_MAP and the HSTM_REF_CELL control And selects a plurality of paths corresponding to the plurality of fingers assigned to the cell according to the signal.

On the other hand, if it is the second mode using the timing information of the reference finger among the fingers allocated to the serving cell, the flow advances to step 406 to select a path corresponding to the reference finger according to the HSTM_REF-FNG and the finger indicator control signal.

Thereafter, if the MASK_INC signal is generated by increasing the timing of the path selected in step 404 or 406 in step 408, the sampling controller 110 proceeds to step 410 and decrements IncDecCounter.

If the timing of the path selected in step 404 or 406 is decreased in step 408, the sampling controller 110 determines whether a MASK_DEC signal is generated in step 412. If a MASK_DEC signal is generated, the sampling controller 110 proceeds to step 414 to generate an IncDecCounter . The process proceeds to step 412, and if the MASK_DEC signal is not generated, the process proceeds to step 408.

In step 416, the sampling controller 110 determines whether it is the cumulative period of the IncDecCounter. When the cumulative period is not the cumulative period, the sampling controller 110 maintains the signal "oEqMovPosition" for adjusting the position of the input sampled data in step 418 .

On the other hand, when the IncDecCounter is accumulated, the sampling controller 110 proceeds to step 420 and compares the accumulated value IncDecCounter with the "HSTM_TH_U ", and proceeds to step 422 when IncDecCounter> HSTM_TH_U. Set oEqMovPosition to increment (INC) to adjust position. That is, the position of the sampling data is set to be higher than the reference.

If incDecCounter> HSTM_TH_U is not satisfied, it proceeds to step 424 to check whether IncDecCounter <HSTM_TH_L, and proceeds to step 428 where IncDecCounter <HSTM_TH_L, and sets oEqMovPosition for adjusting the position of sampling data to decrease (DEC). That is, the position of the sampling data is set to be later than the reference.

If it is not IncDecCounter <HSTM_TH_L, the process proceeds to step 426 to maintain the signal "oEqMovPosition" for adjusting the position of the input sampling data of the equalizer.

In other words, the equalizer is not intended to track a specific path by its nature, so no quick update is required. Accordingly, the present invention can track the cumulative position of the increase / decrease for each frame in about 10 ms, and adjust the update period according to the value of "HSTM_ACC_PERIOD ". The cumulative value is compared with "HSTM_TH_U" and "HSTM_TH_L " every frame period determined by" HSTM_ACC_PERIOD ". The value "HSTM_TH_U" is a predetermined threshold value. If the value accumulated in IncDecCnt is larger than this value, "oEqMovPosition" which is a signal for adjusting the position of the input sampling data of the equalizer is "INC" . Likewise, when the value of "HSTM_TH_L" is compared with the value of IncDecCnt, the value of "oEqMovPosition" is output as "DEC" (meaning to move backward in time) only when the value becomes smaller.

That is, the oEqMovPosition is applied to the sampling selector 112 to select an optimal sampling value among the outputs of the interpolator 102 of FIG. If the transmitted control signal is "INC", the sampling selector 112 adjusts to the data ahead of the current sampling position. If the control signal is "DEC", the sampling selector 112 adjusts the data backward.

As described above, an optimal sampling value of the A / D-converted data interpolating the equalizer 114 is applied to improve the equalizer performance. The chip unit equalizer is composed of a FIR (Finite Impulse Response) filter. The filter tap that is implemented differently from the ideal filter is inevitably limited. Especially, the chip unit equalizer transmits all chip data and outputs all sampling data output in interpolated units Adding a tab to use all has the disadvantage that the hardware becomes large. Accordingly, the present invention receives the necessary timing displacement information from a rake receiver capable of track-by-path tracking and applies it to the equalizer 114 to achieve a low BLER (BLock Error Rate).

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited by the illustrated embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

108: path selector, 112: sampling selector, 114: equalizer.

Claims (14)

An apparatus for eliminating equalizer sampling errors in a wireless communication system,
An interpolator for interpolating between samples of a signal received via a plurality of paths to generate a plurality of sample data;
A first receiver for performing synchronization tracking on each of the plurality of paths,
And a second receiver for performing equalization of the received signal,
The second receiver comprising:
A sampling controller for determining a sampling position of the received signal based on a synchronization trace for each of the plurality of paths;
A sampling selector for selecting sampling data for equalization among the plurality of sample data based on the determined sampling position,
And an equalizer for performing channel compensation of the received signal based on the sampling data for equalization.
The method according to claim 1,
The first receiver comprising:
A plurality of decimators for performing a decimation for each of the plurality of paths from the plurality of sample data,
And a plurality of synchronization trackers for tracking synchronization traces for each of the plurality of paths after performing the decimation.
The method according to claim 1,
Further comprising a path selector for selecting at least one timing information among a plurality of timing information according to synchronization tracking for each of the plurality of paths.
The method of claim 3,
Wherein the path selector comprises:
And selects the timing information of the reference finger among all of the fingers assigned to the serving cell in which the equalizer operates.
The method according to claim 1,
Wherein the sampling controller comprises:
An AND gate for masking a control signal corresponding to synchronization tracking information for each of the plurality of paths and a control signal corresponding to index information of the corresponding finger,
A detector for detecting whether the masked signal is 1 or 0,
An OR gate for performing an OR operation on the detected result,
An increase / decrease counter for accumulating the result of the OR operation for a predetermined period,
And an output unit for comparing the accumulated value with two threshold values to determine a sampling position.
6. The method of claim 5,
And a reset unit for determining the predetermined period using a frame counter.
6. The method of claim 5,
The output unit includes:
When the accumulated value is greater than the first threshold value, the sampling position is positioned temporally ahead of the current sampling position,
When the accumulated value is smaller than the second threshold value, the sampling position is positioned temporally ahead of the current sampling position,
And maintains the current sampling position when the accumulated value is between the first threshold value and the second threshold value.
A method for eliminating equalizer sampling errors in a wireless communication system,
Generating a plurality of sample data by interpolating samples of a signal received through a plurality of paths,
Performing synchronization tracking for each of the plurality of paths;
And performing equalization of the received signal,
Wherein the step of performing equalization of the received signal comprises:
Determining a sampling position of the received signal based on a synchronization trace for each of the plurality of paths;
Selecting sampling data for equalization among the plurality of sample data based on the determined sampling position,
And performing channel compensation on the received signal based on the sampling data for the equalization.
9. The method of claim 8,
The process of performing synchronization tracking for each of the plurality of paths,
Performing a stepwise decimation for each of the plurality of paths from the plurality of sample data;
And tracking synchronization traces for each of the plurality of paths after performing the decimation.
9. The method of claim 8,
Further comprising the step of selecting at least one timing information among a plurality of timing information according to synchronization tracking for each of the plurality of paths.
11. The method of claim 10,
Wherein the step of selecting at least one timing information among a plurality of timing information according to synchronization tracking for each of the plurality of paths comprises:
Wherein the timing information of the reference finger among all the fingers assigned to the serving cell in which the equalizer operates is selected.
9. The method of claim 8,
The step of determining the sampling position includes:
Masking a control signal corresponding to synchronization tracking information for each of the plurality of paths and a control signal corresponding to index information of the corresponding finger;
Detecting whether the masked signal is 1 or 0,
Performing an OR operation on the detected result,
Accumulating the result of the OR operation for a predetermined period;
And comparing the accumulated value with two threshold values to determine a sampling position.
13. The method of claim 12,
Further comprising the step of determining the predetermined period using a frame counter.
13. The method of claim 12,
The step of comparing the accumulated value and the two threshold values to determine a sampling position includes:
When the accumulated value is greater than the first threshold value, the sampling position is positioned temporally ahead of the current sampling position,
When the accumulated value is smaller than the second threshold value, the sampling position is positioned temporally ahead of the current sampling position,
And maintains the current sampling position when the accumulated value is between the first threshold and the second threshold.

Images