KR101705903B1 - Liquid crystal display - Google Patents

Abstract

A liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel; A backlight unit including a plurality of light sources for irradiating light to a rear surface of the liquid crystal display panel; A backlight driving circuit for driving the light sources on a predetermined block basis based on a dimming value for each block; And a local dimming unit for analyzing input data on a horizontal line basis to derive a representative value for each of the blocks arranged on the corresponding horizontal line in a line sequential manner and for determining the dimming value for each block according to the representative value for each block, And a control circuit.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device capable of improving a contrast ratio of a display image.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. This liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display device displays an image using a thin film transistor (hereinafter referred to as "TFT") as a switching element. A transmissive liquid crystal display device that occupies most of the liquid crystal display device displays an image by controlling an electric field applied to the liquid crystal layer to modulate light incident from the backlight unit.

The image quality of the liquid crystal display device depends on the contrast characteristics. The method of modulating the light transmittance of the liquid crystal layer by controlling the data voltage applied to the liquid crystal layer limits the improvement of the contrast characteristic. In order to improve the contrast characteristic, a backlight dimming method of adjusting the brightness of the backlight unit according to an image has been proposed. The backlight dimming method includes a global dimming method for adjusting the brightness of the entire display surface and a local dimming method for locally adjusting the brightness of the display surface. The global dimming method can improve the dynamic contrast measured between the previous frame and the next frame. The local dimming method can improve the static contrast which is difficult to improve by the global dimming method by locally controlling the brightness of the display surface within one frame period.

The local dimming method divides the backlight into multiple blocks and adjusts the dimming value for each block to increase the backlight luminance of the bright block, while reducing the backlight luminance of the dark block. The dimming value of each block is generated based on the analysis result of the video signal of the corresponding block. Image analysis is done on a frame-by-frame basis. When the image analysis for one frame is completed, the dimming value for each block is transferred to the backlight, and the lighting duty of the light source in each block is adjusted based on the corresponding dimming value.

In the conventional local dimming method, the image is analyzed on a frame-by-frame basis, and dimming values of all blocks are simultaneously generated based on the analysis result. Then, the generated dimming value is compared with a specific time t ) At the same time as the backlight. In FIG. 1, 'Vsync' indicates a vertical synchronization signal. The vertical blank period VB indicates a period during which no valid image is displayed between neighboring frames. However, in order to simultaneously generate dimming values of all the blocks, image analyzers corresponding to the number of light source blocks are required. As the number of image analyzers increases, the hardware resources of FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit) become larger when implementing local dimming. This problem is caused by image analysis on a frame basis.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of reducing hardware resources of an FPGA or an ASIC in a local dimming implementation.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel; A backlight unit including a plurality of light sources for irradiating light to a rear surface of the liquid crystal display panel; A backlight driving circuit for driving the light sources on a predetermined block basis based on a dimming value for each block; And a local dimming unit for analyzing input data on a horizontal line basis to derive a representative value for each of the blocks arranged on the corresponding horizontal line in a line sequential manner and for determining the dimming value for each block according to the representative value for each block, And a control circuit.

Wherein the local dimming control circuit comprises: a maximum value deriving part for deriving maximum values of pixels in each block including a plurality of pixels; A representative value calculation unit for accumulating the derived maximum values for one horizontal period and calculating the accumulated result as the representative value for each block; And a reset unit for generating a reset signal for resetting the representative value calculator at intervals of one horizontal period.

The representative value calculator includes accumulators corresponding to the number of blocks arranged in one horizontal line to accumulate the maximum values; The accumulators are reset according to the reset signal immediately after outputting the representative values for each block of the corresponding horizontal line.

The time point at which the dimming value for each block is applied to the light sources varies in units of horizontal lines.

The dimming values of the first line blocks arranged in the first horizontal line are applied to the first line blocks in the horizontal blanking period between the first horizontal period and the second horizontal period, The dimming values of the blocks are applied to the second line blocks in the horizontal blanking period between the second horizontal period and the third horizontal period, and the dimming values of the m-1th line blocks arranged in the (m-1) 1 line blocks in the horizontal blanking period between the m-1 horizontal period and the m-th horizontal line, and the dimming values of the m-th line blocks arranged in the m-th horizontal line are applied to the m- And applied to the m-th line blocks in the horizontal blank period between +1 horizontal periods.

Wherein the local dimming control circuit comprises a first dimming control circuit for controlling the first dimming value indicating the amount of light reaching each pixel when all of the light sources are turned on at the maximum brightness and the first dimming value indicating the amount of light reaching each pixel at the time of local dimming A light amount deriving unit for deriving a second amount of light to be indicated; A gain value calculation unit for calculating a pixel gain value for each pixel based on the first and second light amounts; And a data modulator for multiplying the input data by the pixel gain value to compensate the input data.

Since the liquid crystal display according to the present invention performs image analysis on a horizontal line basis in accordance with the line sequential method, compared with the prior art in which image analysis is performed frame by frame, The number can be greatly reduced. As a result, according to the present invention, the hardware resources of the FPGA and the ASIC can be significantly reduced compared to the conventional hardware when the local dimming is implemented.

1 is a view showing a timing at which a dimming value is applied in a conventional local dimming implementation;
2 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
Figure 3 shows a local dimming control circuit capable of reducing hardware resources;
FIG. 4 is a detailed view of the image analysis unit and the dimming value determination unit of FIG. 3; FIG.
Figure 5 shows a number of blocks that are partitioned for local dimming implementations.
6 shows a waveform of a reset signal;
7 is a view showing a time point at which a block-by-block dimming value is applied to light sources in a local dimming implementation;
Fig. 8 is a view showing an analysis area having a size of P (number of blocks) x P (number of blocks) surrounding a block including the pixel.
Figure 9 shows the number of registers required in designing a local dimming algorithm for a block number of 5120;

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 9. FIG.

2 shows a liquid crystal display according to an embodiment of the present invention.

2, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, a local dimming control circuit 14 ), A backlight driving circuit 15, and a backlight unit 16.

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL are intersected with each other on a lower glass substrate of the liquid crystal display panel 10. [ The liquid crystal cells Clc are arranged in a matrix form in the liquid crystal display panel 10 by the intersection structure of the data lines DL and the gate lines GL. Each of the liquid crystal cells Clc includes a TFT, a pixel electrode 1 connected to the TFT, and a storage capacitor Cst. On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, a common electrode 2, and the like are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. The liquid crystal cells Clc include R liquid crystal cells for red display, G liquid crystal cells for green display, and B liquid crystal cells for blue display. The R liquid crystal cell, the G liquid crystal cell, and the B liquid crystal cell constitute one unit pixel. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for forming a pre-tilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 11 supplies digital video data RGB input from an external system board (not shown) on which a video source is mounted to the local dimming control circuit 14, And supplies the modulated data (R'G'B ') to the data driving circuit 12. The timing controller 11 generates timing control signals for controlling the operation timings of the data driving circuit 12 and the gate driving circuit 13 based on the timing signals Vsync, Hsync, DE, DCLK from the system board DDC, GDC). The timing controller 11 inserts an interpolation frame between the frames of the input video signal input at a frame frequency of 60 Hz and multiplies the data timing control signal DDC and the gate timing control signal GDC to obtain 60 × N The operation of the data driving circuit 12 and the gate driving circuit 13 can be controlled with a frame frequency of Hz or more.

The data driving circuit 12 includes a plurality of data drive ICs. The data drive IC includes a shift register for sampling a clock signal, a register for temporarily storing input data, a data register for storing data for one line in response to a clock signal from a shift register, A digital / analog converter for selecting a positive / negative gamma voltage under reference to a gamma reference voltage corresponding to digital data values from a latch, latch, and latch, and analog data converted by a positive / negative gamma voltage A multiplexer for selecting the data line DL, and an output buffer connected between the multiplexer and the data line DL. The data driving circuit 12 latches the modulated data R'G'B 'under the control of the timing controller 11 and outputs the latched modulated data R'G'B' to positive / negative polarity gamma compensation Voltage to the positive polarity / negative polarity analog data voltage, and supplies it to the data lines DL.

The gate drive circuit 13 includes a plurality of gate drive integrated circuits. The gate drive integrated circuit includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer. The gate drive circuit 13 sequentially outputs a scan pulse (or a gate pulse) under the control of the timing controller 11 and supplies it to the gate lines GL to select a horizontal line to which the data voltage is to be applied. The gate driving circuit 13 may be formed directly on the lower glass substrate of the liquid crystal display panel 10 according to a GIP (Gate In Panel) method. In the GIP scheme, the level shifter can be mounted on a control board (not shown) together with the timing controller 11. [

The local dimming control circuit 14 analyzes the input data RGB on a horizontal line basis to derive a representative value for each block and generates a representative value for each block for controlling the light sources of the backlight unit 16 on a block- To determine the dimming value (DIM). Then, a pixel gain value for compensating for the luminance drop due to the block-specific dimming value (DIM) is calculated, and the input data RGB is compensated based on the pixel gain value. Then, the compensated data is output as the final modulated data R'G'B '.

The backlight driver circuit 15 supplies the light sources of the backlight unit 16 to the block 12 by a pulse width modulation (PWM) whose duty ratio is varied in accordance with the block-by-block dimming value DIM input from the local dimming control circuit 14. [ . The lighting duty of the light sources is controlled according to the PWM duty ratio.

The backlight unit 16 includes a plurality of light sources, and divides the surface light source irradiated on the liquid crystal display panel 10 into blocks in the form of a matrix. The backlight unit 16 may be implemented as either a direct type or an edge type. The direct-type backlight unit 16 has a structure in which a plurality of optical sheets and a diffusion plate are stacked under the liquid crystal display panel 10, and a plurality of light sources are disposed under the diffusion plate. The edge type backlight unit 16 has a structure in which a plurality of optical sheets and a light guide plate are stacked below a liquid crystal display panel 10 and a plurality of light sources are disposed on a side surface of the light guide plate. The light sources may be realized by point light sources such as a light emitting diode (LED).

FIG. 3 shows an example of a local dimming control circuit 14 capable of reducing hardware resources.

Referring to FIG. 3, the local dimming control circuit 14 includes an image analysis unit 141 and a dimming value determination unit 142 to derive a dimming value (DIM) for each block.

The image analysis unit 141 includes a maximum value derivation unit 141A, a representative value calculation unit 141B, and a reset unit 141C as shown in FIG. The maximum value derivation unit 141A divides the input digital data RGB into virtual blocks BLK [1,1] to BLK [n, n] divided into a matrix form on the display screen of the liquid crystal display panel 10, m]) and derives the maximum values (MAX_D) of the pixels in each block. The virtual blocks BLK [1,1] to BLK [n, m] correspond to the light source blocks in a one-to-one correspondence. A plurality of pixels are included in each block. The maximum value MAX_D of the pixel is selected as the maximum gradation value among the RGB values of the pixel. The representative value calculation unit 141B includes accumulators AC # 1 to AC # m corresponding to the number of blocks arranged on one horizontal line. Each of the accumulators AC # 1 to AC # m accumulates the maximum values MAX_D of the corresponding block input from the maximum value derivation unit 141A for one horizontal period and outputs the accumulated result to the block representative value RV_D . The reset unit 141C generates a reset signal RST every one horizontal period H based on a timing signal such as a horizontal synchronization signal Hsync or a data enable signal DE as shown in FIG. AC # 1 to AC # m). The accumulators AC # 1 to AC # m are reset immediately after outputting the block specific value RV_D of the corresponding horizontal line. Each of the accumulators AC # 1 to AC # m accumulates the maximum values MAX_D of the corresponding block line by line from the first horizontal line to the nth horizontal line and outputs the accumulated values. The number of the accumulators AC # 1 to AC # m is reduced to 1 / n compared with the conventional one.

The dimming value determination unit 142 determines a dimming value (DIM) for each block by mapping a block-specific representative value RV_D from the image analysis unit 141 to a predetermined dimming curve. The dimming value (DIM) for each block can be determined to be high in a block having a high representative value of data and low in a block having a low representative value. The dimming value determining unit 142 includes a dimming value mapping unit 142A and a lookup table 142B for dimming curve implementation. In the look-up table 142B, a dimming value (DIM) for each block of j (j < k) bits corresponding to the representative value RV_D for each block of k bits is stored in advance. The dimming value mapping unit 142A maps the block-specific representative value RV_D to the look-up table 142B, determines a dimming value DIM for each block, and supplies the dimming value to the backlight driving circuit.

In the present invention and the related art, the point at which the dimming value (DIM) for each block is applied to the light sources of the backlight unit is as follows. In the prior art, as shown in FIG. 1, the dimming value (DIM) for each block is simultaneously applied to the light sources of the backlight unit in the vertical blank period VB after the image analysis for one frame is completed. On the other hand, in the present invention, as shown in FIG. 7, the time point at which the dimming value (DIM) for each block is applied to the light sources of the backlight unit varies in units of horizontal lines. That is, the dimming values DIM of the first line blocks arranged in the first horizontal line HL # 1 are supplied to the first line blocks in the horizontal blanking period HB between the first horizontal period and the second horizontal period And the dimming values DIM of the second line blocks arranged in the second horizontal line HL # 2 are applied to the second line blocks BL in the horizontal blanking period HB between the second horizontal period and the third horizontal period And the dimming values DIM of the (m-1) th line blocks disposed in the (m-1) th horizontal line HL # m-1 are applied to the horizontal blank period And the dimming values DIM of the m-th line blocks disposed in the m-th horizontal line HL # m are applied to the m-th horizontal line and the (m + 1) To the m-th line blocks in the horizontal blanking period HB between them. In FIG. 7, 'Vsync' indicates a vertical synchronization signal and 'Hsync' indicates a horizontal synchronization signal.

On the other hand, the local dimming control circuit 14 further includes a light amount deriving section 143, a gain calculating section 144 and a data modulating section 145 so as to compensate for the luminance reduction due to local dimming through modulation of pixel data .

The light amount deriving unit 143 calculates the amount of light (non-dimming amount) reaching the corresponding pixel at the time of non-local dimming and the amount of light reaching the corresponding pixel at the time of local dimming by the dimming value (DIM) Light amount) for each pixel. When dimming, the amount of light indicates the total amount of light reaching the corresponding pixel when all the light sources of the backlight are turned on at the maximum brightness. As shown in FIG. 8, the amount of light at the time of dimming has a value of P (number of blocks) × P (number of blocks) (P is an odd number of 3 or more) surrounding the block including the pixel at the time of local dimming Indicating the total amount of light reaching the pixel in the area. The dimming amount of light is determined by the block-by-block dimming value (DIM) of the blocks in the analysis area.

The gain calculating unit 144 calculates the pixel gain value G for each pixel based on the amount of light at the time of non-dimming and the amount of light at the time of dimming from the light amount deriving unit 143. [ The gain calculating unit 144 divides the amount of light at the time of non-dimming by the dimming amount of light, and performs a 1 /? Exponent operation on the result to calculate the pixel gain value G.

The data modulating section 145 modulates the input data RGB by multiplying the input data RGB by the pixel gain value G from the gain value calculating section 144. [ The input data (RGB) is modulated to a value (R'G'B ') that can compensate for the luminance reduction due to local dimming.

Figure 9 compares the number of registers required when designing a local dimming algorithm for a block number of 5120 (i.e., 80 horizontal by 60 vertical). In FIG. 9, '15' indicates the number of data bits of the representative value RV_D for each block to be stored for each block, '8' indicates the number of data bits of the dimming value DIM for each block Indicate.

As can be seen from FIG. 9, since image analysis is performed frame by frame in the past, 194,560 registers are required to store representative values (RV_D) for each frame and dimming values (DIM) for each block at a time Respectively. In contrast, according to the present invention, image analysis is performed on a horizontal line basis in accordance with the line sequential method. Therefore, only 3,040 registers are used for storing the representative values RV_D and the dimming values DIM for each block It suffices.

According to the present invention, the hardware resources of the FPGA or the ASIC can be greatly reduced compared with the conventional FPGA when the local dimming is implemented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: local dimming control circuit 15: light source driving circuit
16: backlight unit 141: image analysis unit
141A: maximum value derivation unit 141B: representative value calculation unit
141C: reset section 142: dimming value determining section
142A: dimming value mapping unit 142B: lookup table
143: light amount deriving unit 144: gain value calculating unit
145: Data modulation section

Claims (6)

A liquid crystal display panel;
A backlight unit including a plurality of light sources for irradiating light to a rear surface of the liquid crystal display panel;
A backlight driving circuit for driving the light sources on a predetermined block basis based on a dimming value for each block; And
A local dimming control unit for analyzing input data on a horizontal line basis to derive a representative value for each of the blocks arranged on the corresponding horizontal line in a line sequential manner and for determining a dimming value for each block according to the representative value for each block, Circuit,
The local dimming control circuit comprising:
A maximum value derivation unit for deriving maximum values of pixels in each block including a plurality of pixels;
A representative value calculation unit for accumulating the derived maximum values for one horizontal period and calculating the accumulated result as the representative value for each block; And
And a reset unit for generating a reset signal for resetting the representative value calculating unit at intervals of one horizontal period. delete The method according to claim 1,
The representative value calculator includes accumulators corresponding to the number of blocks arranged in one horizontal line to accumulate the maximum values;
Wherein the accumulators are reset in response to the reset signal immediately after outputting representative values of the respective blocks of the corresponding horizontal line. The method according to claim 1,
Wherein a time point at which the dimming value for each block is applied to the light sources varies in units of horizontal lines. 5. The method of claim 4,
The dimming values of the first line blocks arranged in the first horizontal line are applied to the first line blocks in the horizontal blanking period between the first horizontal period and the second horizontal period, The dimming values of the blocks are applied to the second line blocks in the horizontal blanking period between the second horizontal period and the third horizontal period, and the dimming values of the m-1th line blocks arranged in the (m-1) 1 line blocks in the horizontal blanking period between the m-1 horizontal period and the m-th horizontal line, and the dimming values of the m-th line blocks arranged in the m-th horizontal line are applied to the m- And the horizontal blanking period is applied to the m-th line blocks. The method according to claim 1,
The local dimming control circuit comprising:
A first light amount indicating a light amount reaching each pixel when all of the light sources are turned on at maximum brightness and a second light amount indicating a light amount reaching each pixel at the time of local dimming with the dimming value for each block A light amount deriving unit;
A gain value calculation unit for calculating a pixel gain value for each pixel based on the first and second light amounts; And
And a data modulator for multiplying the input data by the pixel gain value to compensate the input data.

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