KR101702393B1 - Semiconductor storage device and method for throttling performance of the semiconductor storage device - Google Patents

Abstract

A semiconductor storage device and a method for controlling performance of the semiconductor storage device are disclosed. A method for controlling performance of a semiconductor storage device including a nonvolatile memory device of the present invention and a controller for controlling the nonvolatile memory device includes: operating the semiconductor storage device according to a first performance level; Calculating a new performance level; Comparing the calculated performance level with a predetermined criterion; Determining the calculated performance level as a second performance level according to the comparison result; And operating the semiconductor storage device according to the second performance level.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor storage device and a method for controlling the performance of the semiconductor storage device.

The present invention relates to a data storage device, and more particularly, to a semiconductor storage device for storing data in a nonvolatile memory and a performance adjustment method thereof.

Semiconductor storage devices are devices that store data using semiconductors (particularly, nonvolatile memory), and are faster in speed and stronger in physical shock than disk storage media (hard disk drives), which have hitherto been widely used as mass storage devices It has less heat and noise, and can be miniaturized. An example of a semiconductor storage device is a solid state drive (SSD).

On the other hand, semiconductor storage devices may have a limited service life. For example, NAND flash memory is a typical example. In a NAND flash memory, a memory element is divided into block units, and a plurality of pages exist in one block. The user first uses the NAND flash memory by erasing the block and sequentially programming the pages in the block with specific data. To program all pages as new data with programmed blocks, the corresponding block must be erased again. This sequence of processes is called the program-erase cycle (PE-cycle), and in the case of NAND flash memory, the number of PE cycles that a block can withstand is limited. This is called the endurance of the NAND flash memory.

If the number of PE-cycles experienced by one block exceeds the endurance limit, then the block has a higher probability of malfunctioning in the future. Causes of malfunction of the memory include read operation, natural charge loss, and the like in addition to the program and erase operations described above. As the probability of malfunction increases, it should no longer be used for data integrity of semiconductor storage devices. For this reason, semiconductor storage devices employing NAND flash memory have a limitation in their lifetime.

In the above example, when an excessive workload is applied to the semiconductor storage device, for example, a write operation, an erase operation, a read operation, or the like, the life of the semiconductor storage device may be shortened or the expected life may not be guaranteed. Therefore, in order to ensure the expected lifetime of the semiconductor storage device, the processing capacity of the semiconductor storage device needs to be adjusted depending on the strength or amount of the workload applied to the semiconductor storage device.

This case can be found in a solid state drive (SSD) composed of a multi-level cell (MLC) NAND flash memory for a server application. Server-oriented storage devices require high performance, that is, high I / O per second (I / O), as well as a large change in the amount of workload applied to the storage device. Application of MLC NAND flash memory with limited endurance limitations to such applications has difficulties in guaranteeing the lifetime of the SSD.

However, the storage device to which the life is to be guaranteed is not limited to the above-described server-oriented storage device, and the lifetime of a storage device to be applied to a PC (personal computer), a notebook computer,

In addition to the NAND flash memory described above, examples of the memory having the limit of the degree of freedom include PRAM (Phase Change Memory), MRAM (Magnetic Random Access Memory), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM, Ferroelectric RAM ) And the like. In addition, NAND flash memory with the limit of the limit includes a NAND flash memory using a floating gate and a NAND flash memory based on a charge trap flash (CTF) method.

Thus, there is a need for a method for extending the life of a semiconductor storage device using a nonvolatile memory having an endurance limit, or for assuring a life expectancy.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a semiconductor storage device capable of adjusting the performance of the semiconductor storage device adaptively according to a workload.

According to another aspect of the present invention, there is provided a method of controlling performance of a semiconductor storage device including a nonvolatile memory device and a controller for controlling the nonvolatile memory device, Operating according to a level; Calculating a new performance level; Comparing the calculated performance level with a predetermined criterion; Determining the calculated performance level as a second performance level according to the comparison result; And operating the semiconductor storage device according to the second performance level.

As described above, according to the present invention, the performance can be adaptively adjusted according to the workload of the semiconductor storage device. Thereby, there is an effect that the lifetime of the semiconductor storage device can be extended or the required lifetime can be guaranteed.

1 is a schematic block diagram of a data storage system in accordance with an embodiment of the present invention.
2 is a schematic block diagram of a controller according to an embodiment of the present invention.
FIG. 3 is a view schematically showing the structure of the nonvolatile memory device shown in FIG. 2. FIG.
4 is a schematic block diagram of a host according to an embodiment of the present invention.
FIG. 5A is a flowchart illustrating a method of adjusting performance of a semiconductor storage device according to an embodiment of the present invention. Referring to FIG.
FIG. 5B is a flowchart illustrating a method of adjusting the performance of a semiconductor storage device according to an exemplary embodiment of the present invention. Referring to FIG.
5C is a flowchart illustrating a method of adjusting performance of a semiconductor storage device according to another embodiment of the present invention.
FIG. 6 is a graph illustrating a change in performance level according to a performance adjustment method of the semiconductor storage device shown in FIG. 5B.
7 is a flowchart illustrating a method of adjusting performance of a semiconductor storage device according to another embodiment of the present invention.
FIG. 8 is a graph showing a change in the performance level according to the performance adjustment method of the semiconductor storage device shown in FIG.
9 is a flowchart illustrating a method of adjusting the performance of a semiconductor storage device according to another embodiment of the present invention.
FIG. 10 is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device shown in FIG.
11 is a flowchart illustrating a method of adjusting the performance of a semiconductor storage device according to another embodiment of the present invention.
12A is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device shown in FIG.
12B is a graph for explaining a method of selecting a discrete level according to the calculated performance level.
13 is a table showing a format of a host command according to an embodiment of the present invention.
14 is a block diagram of an electronic system including a semiconductor storage device according to an embodiment of the present invention.
15A and 15B are block diagrams of an electronic system according to another embodiment of the present invention, respectively.
16 is a block diagram of a computing system having a semiconductor storage device according to an embodiment of the present invention.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

For example, when one component 'transmits or outputs' data or signals to another component, the component may 'transmit or output' the data or signal directly to the other component, and at least one Quot; means that the data or signal can be " transmitted or outputted " to another element through another element of the system.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a schematic block diagram of a data storage system 1 according to an embodiment of the present invention. A data storage system 1 according to an embodiment of the present invention includes a semiconductor storage device 10 and a host 20. [ The semiconductor storage device 10 may include a controller 100 and a non-volatile memory device 200.

The host 20 is connected to a semiconductor device 20 using interface protocols such as peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA) And can communicate with the storage device 10. However, the interface protocols between the host 20 and the semiconductor storage device 10 are not limited to the above-described examples, and may be a USB (Universal Serial Bus), a multi-media card (MMC), an enhanced small disk interface (ESDI) (Integrated Drive Electronics), and the like.

The semiconductor storage device 10 according to an embodiment of the present invention may be a solid state drive (SSD). In addition, non-volatile memory device 200 may be a flash memory device, but is not limited thereto.

The controller 100 controls the overall operation of the semiconductor storage device 10 and also controls all data exchange between the host 20 and the nonvolatile memory device 200. For example, the controller 100 controls the nonvolatile memory device 200 at the request of the host 20 to write data or read data. In addition, the controller 100 controls a series of internal operations (e.g., performance adjustment, merge, wear leveling, etc.) necessary for the characteristics of the non-volatile memory and for efficient management of the non-volatile memory.

The non-volatile memory device 200 is a storage location for storing data non-volatile, and stores user data and metadata. The non-volatile memory device 220 may store an operating system (OS), various programs, and various data.

2 is a schematic block diagram of a controller 100 according to one embodiment of the present invention. 2, the controller 100 includes a host interface 110, a DRAM 120, an SRAM 130, a non-volatile memory interface 140, a CPU 150, a system bus 160, a workload module 170, a timer 180, a performance adjustment module 190, and a clock generator 195.

The host interface 110 has an interface protocol for communicating with the host 20. DRAM 120, and SRAM 130 volatile store data and / or programs, respectively. Non-volatile memory interface 140 interfaces with non-volatile memory device 200.

The CPU 150 performs all control operations for writing / reading data to and from the nonvolatile memory device 200. [

The workload module 170 may collect workload data associated with the workload being applied to the semiconductor storage device 10 and may predict the workload based on the collected workload data.

The performance adjustment module 190 determines the target performance level according to the workload predicted by the workload module 170 and adjusts the performance of the semiconductor storage device 10 by applying the determined performance level.

 The timer 180 provides time information to the CPU 150, the workload module 170, and the performance adjustment module 190. The workload module 170 and the performance adjustment module 190 may be implemented in hardware, software, or a combination of hardware and software.

When the workload module 170 and the performance adjustment module 190 are implemented in software, the program is stored in the nonvolatile memory device 200 and when the semiconductor storage device 10 is powered on, May be loaded into SRAM 130 from CPU 200 and executed by CPU 150.

The timer 180 may also be implemented in hardware or software.

The clock generator 195 generates a clock signal necessary for the operation of the CPU 150, the DRAM 120, and the nonvolatile memory device 200, and provides the generated clock signal to the corresponding component. The speeds of the clock signals provided to the CPU 150, the DRAM 120, and the nonvolatile memory device 200 may be different from each other. The clock generator 195 adjusts the speed of the clock signal applied to the CPU 150, the DRAM 120, and the nonvolatile memory device 200, respectively, according to the performance level determined in the performance adjustment module 190, The performance of the storage device 10 can be adjusted.

Although not shown in the figure, the semiconductor storage device 10 includes a ROM (not shown) for storing code data to be executed upon power-on of the semiconductor storage device 10, a nonvolatile memory device 200, And an ECC engine (not shown) for encoding the data to be stored in the nonvolatile memory device 200 and decoding the data read from the nonvolatile memory device 200.

FIG. 3 schematically shows the structure of the nonvolatile memory device 200 shown in FIG. With reference thereto, the non-volatile memory device 200 may include a plurality of memory chips. In FIG. 3, a non-volatile memory device 200 having a 4-channel / 3-bank hardware structure is illustrated by way of example, but the present invention is not limited thereto.

In the semiconductor storage device 10 shown in FIG. 3, the controller 100 and the non-volatile memory device 200 are connected by four channels (Channels A, B, C, and D) Chip (CA0 to CA2, CB0 to CB2, CC0 to CC2, CD0 to CD2) are connected. However, it goes without saying that the number of channels and the number of banks are not limited thereto and can be changed.

In the semiconductor storage device 10 having such a structure, the performance control unit of the semiconductor storage device 10 is a unit in which the entire nonvolatile memory device 200, the individual memory devices (memory chips) of the nonvolatile memory device 200 May be a bus (channel) unit, a bank unit, or an individual device unit. Here, a bank is a group of memory devices located at the same offset on different channels.

4 is a schematic block diagram of a host 20 in accordance with one embodiment of the present invention. 4, the host 20 includes a CPU 210, a memory 220, a bus 230, an SSD interface 240, a workload module 250, a timer 260, and a performance adjustment module 270 ).

The SSD interface 240 has an interface protocol for communicating with the semiconductor storage device 10.

The CPU 210 performs all control operations for writing / reading data to / from the semiconductor storage device 10.

The workload module 250 may collect workload data associated with the workload being applied to the semiconductor storage device 10 and may predict the workload based on the collected workload data.

The performance adjustment module 270 determines the target performance level according to the workload predicted by the workload module 250 and adjusts the performance of the semiconductor storage device 10 by applying the determined performance level.

 The timer 260 provides time information to the CPU 210, the workload module 250, and the performance adjustment module 270. The workload module 250, the timer 260, and the performance adjustment module 270 may be implemented as software, hardware, or a combination of software and hardware, respectively.

FIG. 5A is a flowchart illustrating a method of adjusting the performance of the semiconductor storage device 10 according to an embodiment of the present invention. The method for controlling the performance of the semiconductor storage device 10 according to an embodiment of the present invention is a method for controlling the performance of the semiconductor storage device 10, the host 20 or the semiconductor storage device 10 and the host 20 .

The performance control method according to an embodiment of the present invention is described with reference to an example implemented in the semiconductor storage device 10, but the present invention is not limited thereto as described above.

5A, the controller 100 may collect workload data related to the workload applied to the semiconductor storage device 10 (S100), and may predict the workload based on the collected workload data (S110) . The controller 100 may calculate the performance level according to the predicted workload and determine the performance level according to the performance control policy (S120). The next determined performance level may be applied to the operation of the semiconductor storage device 10 (S130).

Embodiments of the present invention provide a concrete method for determining the performance level (S120) according to the performance control policy among the steps shown in FIG. 5A.

FIG. 5B is a flowchart illustrating a method of adjusting the performance of the semiconductor storage device 10 according to an embodiment of the present invention. FIG. 6 is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device 10 shown in FIG. 5B.

The controller 100 calculates a new performance level (S121). The new performance level can be calculated using the workload prediction value, but is not limited thereto (S121). Next, the new performance level, i.e., the calculated performance level is compared with a predetermined criterion (S122). In this embodiment, the predetermined criterion is the minimum performance level. Therefore, in order to confirm that the calculated new performance level is lower than the minimum performance level, the new performance level is compared with a predetermined minimum level (S122). As a result of the comparison, if the new performance level is lower than the minimum performance level, the minimum performance level is selected and the selected minimum performance level is applied (S123).

As a result of the comparison, if the new performance level is higher than or equal to the minimum level, the new performance level is selected as it is, and the selected new performance level is applied (S124).

The steps shown in Fig. 5B may correspond to steps S120 and S130 in Fig. 5A.

FIG. 6 is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device 10 shown in FIG. 5B. Referring to this, it can be seen that as the workload changes, the performance level is also adjusted but does not go below the lowest performance level.

As described above, according to the embodiment of the present invention, if the newly calculated performance level is equal to or higher than the minimum performance level, the calculated performance level is directly applied and determined as a new performance level, but if the newly calculated performance level is the minimum performance level , The minimum performance level is selected so that the performance level is not lower than the minimum performance level. Thus, the semiconductor storage device 10 is guaranteed to have the minimum performance even under the worst conditions in which the workload is at its maximum.

FIG. 5C is a flowchart illustrating a method of adjusting the performance of the semiconductor storage device 10 according to another embodiment of the present invention.

Referring to FIG. 5C, the controller 100 calculates a new performance level (S121). The new performance level may be calculated using the workload prediction value, but is not limited thereto (S131). Next, the new performance level, i.e., the calculated performance level is compared with a predetermined criterion (S132). In this embodiment, the predetermined criterion is the maximum performance level. Therefore, in order to check whether the calculated new performance level is higher than the maximum performance level, a new performance level is compared with a predetermined maximum level (S132). As a result of the comparison, if the new performance level is higher than the maximum performance level, the maximum performance level is selected and the selected maximum performance level is applied (S133).

As a result of the comparison, if the new performance level is lower than or equal to the maximum performance level, the calculated performance level is directly selected and the selected performance level is applied (S134).

As described above, according to another embodiment of the present invention, if the newly calculated performance level is lower than or equal to the maximum performance level, the calculated performance level is directly applied and determined as a new performance level, but if the newly calculated performance level is the maximum If it is higher than the performance level, the maximum performance level is determined as a new performance level so that the performance level is not higher than the maximum performance level.

The steps shown in Fig. 5C may correspond to steps S120 and S130 in Fig. 5A.

7 is a flowchart illustrating a method for adjusting the performance of the semiconductor storage device 10 according to another embodiment of the present invention. Referring to FIG. 7, when a new performance level is calculated and set (S210 and S220), the performance level is maintained unchanged for a predetermined period (S230).

For this purpose, it is checked whether a predetermined period has elapsed from the time when the new performance level is applied (S240). When a predetermined period elapses from the application of the new performance level, a new performance level is calculated (S210) (S230).

Alternatively, a new performance level may be calculated for each predetermined performance adjustment period, and the calculated new performance level may be applied to the semiconductor storage device 10. In this case, the applied performance level is maintained during a predetermined performance adjustment period, and a new performance level can be calculated and applied again at the end of the performance adjustment period. Here, the predetermined period or the performance adjustment period may be a unit such as hour, day, week, month, and the like, but is not limited thereto. Also, the performance adjustment cycle may or may not match the performance prediction cycle. For example, the performance prediction is on a time-by-time basis, but performance tuning can be up once and vice versa.

The predetermined period or performance adjustment period may be set in response to the period setting command received from the host. The period setting command may have the host command format shown in Fig. The format of the period setting command of the host will be described later with reference to FIG.

The host can set the viewpoint and the length of the performance control cycle as needed using the above-described period setting command. The predetermined period or the performance adjustment period may be set by an instruction from the host, but it may be preset in the semiconductor storage device 10. [

Adjusting the performance of a storage device only once for a predetermined period (for example, 24 hours, 12 hours, 6 hours), and keeping the performance of the storage device constant during the one period causes the performance of the storage device to be too frequent In order to prevent the degradation of the performance of the storage device from the viewpoint of the host.

FIG. 8 is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device 10 shown in FIG. Referring to this, it can be seen that as the workload changes, the performance level is adjusted for each performance adjustment period.

FIG. 9 is a flowchart showing a method of adjusting the performance of the semiconductor storage device 10 according to another embodiment of the present invention. Referring to FIG. 9, a new performance level is calculated (S310). The difference between the calculated performance level and the current performance level (hereinafter, referred to as a first performance level) is compared with a predetermined reference difference (x%) (S320). As a result of the comparison, If the difference between the levels is lower than the reference difference, the calculated performance level is determined as a new performance level (S350).

If the difference between the calculated performance level and the first performance level is higher than the reference difference, the difference between the calculated performance level and the first performance level is smaller than the reference difference (e.g., x%) The calculated performance level is adjusted to be the second performance level (S340), and the adjusted performance level is determined to be the second performance level (S340).

The reference difference may be preset to any value or any ratio (e.g., x%). When the reference difference is set to a ratio (e.g., x%), the ratio (e.g., x%) may be, but is not limited to, the ratio between the immediately preceding performance and the highest performance.

According to an embodiment of the present invention, when adjusting the performance of the semiconductor storage device 10, the performance difference (+/- x%) relative to the performance immediately before the adjustment of the adjusted performance (or maximum performance) , 10%, 20%, 5%). This is to prevent deterioration of the performance of the semiconductor storage device 10 from the viewpoint of the host when the performance of the semiconductor storage device 10 suddenly changes greatly.

In an embodiment of the present invention, the performance adjusted for a successive period is less than or equal to +/- y% (y value is, for example, 3%, 4%, 2% (N) (more than two integers) more than once, the reference difference (x) can be adjusted upward. This is to ensure that the performance of semiconductor storage devices that are well adapted to regular workloads can effectively respond to sudden changes in workload.

In another embodiment of the present invention, the performance adjusted for a continuous period has a value greater than or equal to +/- z% (where z is, for example, 8%, 16%, 4% If it is maintained continuously for more than m (more than 2 integers) times, the reference difference (x) can be adjusted downward. This is to effectively adapt the performance of the semiconductor storage device to the volatile workload.

In another embodiment of the present invention, as opposed to the above-described embodiment, the performance adjusted for successive periods is +/- y% relative to the previous performance (or minimum performance) (for example, the value of y is 3% 4%, 2%) is continuously maintained for n or more times (integer number of 2 or more), the reference difference (x) is adjusted downward, and the performance adjusted for a continuous period is compared with the previous performance The reference difference (x) may be adjusted upward if the value of +/- z% (z value is 8%, 16%, 4%, for example)

FIG. 10 is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device 10 shown in FIG. Referring to this, as the workload changes, the performance level is adjusted. At this time, it is understood that the new performance level is adjusted within a predetermined reference difference (+/- x%) with respect to the previous performance level. However, as described above, in other embodiments, the new performance level may be adjusted to within a predetermined reference difference (+/- x%) versus the highest performance level.

11 is a flowchart showing a method of adjusting the performance of the semiconductor storage device 10 according to another embodiment of the present invention. 12A is a graph showing a change in performance level according to a performance adjustment method of the semiconductor storage device 10 shown in FIG. 12B is a graph for explaining a method of selecting a discrete level according to the calculated performance level.

Referring to FIGS. 11 to 12B, a new performance level is calculated (S410). The discrete level closest to the calculated performance level among the plurality of predetermined discrete levels (Lv.1 to Lv.9) is selected (S420). In this embodiment, the plurality of discrete levels Lv. 1 to Lv. 9 have different levels of performance in nine stages, but the number of discrete levels and intervals between the levels may vary.

Referring to FIG. 12B, when the current performance level (first performance level) is Lv.5 and the calculated performance level is CL1, CL1 is greater than Lv.5. Assuming that the value is closer to 6, Lv, which is the closest discrete level to the calculated performance level CL1. 6 is selected. Therefore, if the calculated performance level CL1 belongs to the interval D6, Lv. 6 is selected. If it is an intermediate value between neighboring discrete levels, the closest discrete level may be two levels, in which case either one of the two levels may be selected.

The level gap between the selected discrete level and the current performance level (first performance level) is calculated, and the calculated level gap is compared with a predetermined reference gap at step S430. The level gap means a number of steps different from the current performance level (first performance level) of the selected discrete level. For example, if the current performance level (first performance level) is Lv.4 and the selected discrete level is Lv.3 or Lv.5, then the level gap is 1 and the current performance level (first performance level) is Lv. 4 and the selected discrete level is Lv.2 or Lv.6, the level gap is 2.

As a result of the comparison, if the calculated level gap is lower than or equal to a predetermined reference gap (i, i is an integer of 1 or more), the selected discrete level is determined as a new performance level (S460). For example, when the calculated level gap is 1 and the reference gap is 2, the selected discrete level is directly determined as a new performance level (second performance level) and applied.

As a result of the comparison, if the calculated level gap is higher than the reference gap (i), the calculated level gap is adjusted so that the calculated level gap becomes the reference gap (S440) Level is determined to be the second performance level (S450).

For example, instead of determining the selected discrete level as a new performance level (second performance level) when the calculated level gap is 3 and the reference gap is 2, the calculated level gap is not the reference gap (for example, 2 ), And a discrete level corresponding to the adjusted level gap (for example, 2) is determined as the second performance level.

Referring back to FIG. 12B, when the current performance level (first performance level) is Lv.6 and the calculated performance level is CL2, Lv.3, which is the closest discrete level to CL2, is selected in step S420.

Then, a level gap (Lv.6-Lv.3 = 3) between the selected discrete level Lv.3 and the current performance level (first performance level, Lv.6) is calculated and the calculated level gap 3 ) With a predetermined reference gap (e.g., 2) (S430). Since the calculated level gap 3 is larger than the reference gap (for example, 2), the calculated level gap is adjusted to be the reference gap (S440), and the discrete level Lv corresponding to the adjusted level gap 2 is obtained. 4) is determined as the second performance level. The finally selected discrete level is Lv.4 instead of Lv.3.

As described above, when the reference gap is 2, the performance level changes only within two steps at a time, and can not be changed beyond two steps.

In another embodiment of the present invention, when the difference between the second performance level (i.e., the performance level to be newly applied) and the first performance level (the currently applied performance level) has a plurality (two or more) The level can be moved through at least one intermediate level without moving at a time.

For example, if the second performance level is Lv.5 and the first performance level is Lv.2, then instead of directly changing from Lv.2 to Lv.5 and applying it, an intermediate level between Lv.5 and Lv.2 (LV3, Lv4), and then the target performance is changed to Lv.5.

When moving through the intermediate performance level, the minimum time may be maintained for each level (step), and then it may be automatically or again confirmed whether to move again, and then moved to the next performance level.

13 is a table showing a format of a host command according to an embodiment of the present invention. Referring to FIG. 13, the host 20 receives a command signal, which is composed of a feature field, a count field, a logic block address (LBA) field, a device field, and a command field in association with the performance adjustment of the semiconductor storage device 10, May be applied to the semiconductor storage device 10. Each field included in the instruction may be composed of predetermined bits. For example, each of the command field, the device field, and the count field may be composed of 8 bits.

The above-described period setting command may also be defined to have a format similar to the host command shown in Fig. However, the period setting command includes information on the period. The information on the period may be included in one of a feature field, a count field, and a logic block address (LBA) field.

The method for adjusting the performance of the semiconductor storage device 10 according to the embodiment of the present invention may be implemented by hardware, software, or a combination thereof. When the embodiment of the present invention is implemented in software, the performance adjustment program code including a plurality of subroutines for executing the performance adjustment method of the semiconductor storage device 10 according to the embodiment of the present invention is stored in the semiconductor storage device 10, Lt; RTI ID = 0.0 > non-volatile memory.

In this case, the controller can execute the performance adjustment method of the semiconductor storage device 10 according to the embodiment of the present invention by executing the performance adjustment program code stored in the nonvolatile memory.

14 is a block diagram of an electronic system including a semiconductor storage device according to an embodiment of the present invention.

14, an electronic system 900 according to an embodiment of the present invention includes a semiconductor storage device 10, a power supply 910, a central processing unit (CPU) 920 (RAM) 930, a user interface 940, and a system bus 950 for electrically connecting these components.

The CPU 920 controls the overall operation of the system 900 and the RAM 930 stores the information necessary for the operation of the system 900. The User Interface 940 controls the interface between the system 900 and the user Lt; / RTI > The power supply 910 supplies power to the internal components (i.e., CPU 920, RAM 930, user interface 940, memory system 500, etc.).

The CPU 920 may correspond to the host 20 described above and the semiconductor storage device 10 may store or read data in response to the command of the host 20. [

15A and 15B are block diagrams of an electronic system according to another embodiment of the present invention, respectively.

The electronic system 900 'shown in FIG. 15A has a configuration similar to that of the electronic system 900 shown in FIG. 14, so the differences are mainly described in order to avoid duplication of explanation.

The electronic system 900 'shown in FIG. 15A further includes a RAID controller card 960 as compared to the electronic system 900 shown in FIG. The semiconductor storage device 10 can be mounted on the RAID controller card 960 and can interface with the host via the RAID controller card 960 instead of directly interfacing with the host. At this time, a plurality of (two or more) semiconductor storage devices 10-1 to 10-k (k is an integer of 2 or more) may be mounted on the RAID controller card 960. [ The RAID controller card 960 of the electronic system 900 'shown in FIG. 15A is implemented as a separate product outside the semiconductor storage devices 10-1 to 10-k.

The electronic system 900 "shown in FIG. 15B has a similar configuration to the electronic system 900 'shown in FIG. 15A, and therefore focuses on differences to avoid duplication of description.

The RAID controller card 960 of the electronic system 900 "shown in Fig. 15B is implemented as a single product with the semiconductor storage devices 10-1 through 10-k, Gt; 900 '. ≪ / RTI >

In the case where the RAID controller card 960 is provided as described above, the performance control method according to the embodiment of the present invention described above can be implemented by the RAID controller card 960. To this end, the above-described timer, performance adjustment module, and the like may be provided in the RAID controller card 960.

16 is a block diagram of a computing system 1000 (PC) having a semiconductor storage device 10 according to an embodiment of the present invention. The computing system 1000 includes a central processing unit 1110, an accelerated graphics port 1120, a main memory 1130, a north bridge 1140, a semiconductor storage device An SSD 10, a keyboard controller 1160, a printer controller 1170, and a south bridge 1180, for example.

The computing system 1100 may also be a block of a personal computer or notebook computer that the SSD 10 uses as the primary storage device on behalf of the hard disk drive. However, the scope of the present invention is not limited thereto.

In the computing system 1000, the central processing unit 1110, the AGP unit 1120, and the main memory 1130 are connected to the north bridge 1140 and are connected to the SSD 10, the keyboard controller 1160, And various peripheral devices (not shown) are connected to the south bridge 180.

The north bridge 1140 is an integrated circuit on the socket of the central processing unit 1110 with respect to the center of the main board 1110 and generally refers to a system controller including a host interface for connecting to the central processing unit 1110 do. The south bridge 1180 is an integrated circuit on the peripheral component interconnect (PCI) slot in the center of the main board, and generally refers to a bridge from a host bus to a bus connected via a PCI bus.

AGP is a bus specification that enables rapid realization of 3D graphical representations. The AGP device 1120 may include a video card or the like for playing back a monitor image. The main memory 1130 may be implemented as a RAM (Random Access Memory), which is a volatile memory device, but the scope of the present invention is not limited thereto.

In the computing system 1100 according to an embodiment of the present invention, the SSD 10 may be connected to the south bridge 180, but the present invention is not limited thereto. The SSD 10 may be connected to the north bridge 1140 Or may be a structure directly connected to the CPU 1110.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Semiconductor storage: 10
Host: 20
Controller: 100
Nonvolatile memory device: 200
CPU: 150, 210
Host interface: 110
DRAM: 120
SRAM: 130
Memory interface: 140
Timers: 150, 260
Buses: 160, 230
Workload modules: 170, 250
Performance Control Modules: 190, 270
Clock Generator: 195
Storage interface: 240

Claims (40)

A nonvolatile memory device for nonvolatilely storing data; And
And a controller for controlling the nonvolatile memory device,
The controller
Calculating a new performance level of the non-volatile memory device, comparing the calculated performance level with a predetermined criterion, the predetermined criterion being a minimum level,
The controller
If the calculated performance level is lower than or equal to the minimum level, determining the minimum level as the updated performance level, and if the calculated performance level is equal to or higher than the minimum level, ≪ / RTI > wherein the performance adjustment module determines the performance level of the semiconductor memory device based on the performance level. delete The method according to claim 1,
The non-volatile memory device stores a performance adjustment program code,
And the controller executes the performance adjustment program code to calculate the new performance level. A nonvolatile memory device for nonvolatilely storing data; And
And a controller for controlling the nonvolatile memory device,
The controller comprising:
Calculating a new performance level of the non-volatile memory device, comparing the difference between the calculated performance level and the first performance level with a predetermined criterion,
Wherein the first performance level is a currently applied performance level, the second performance level is a performance level to be newly applied,
Wherein the predetermined criterion is a first criterion difference,
Determining the calculated performance level as a second performance level if the difference between the calculated performance level and the first performance level is lower than the first reference level,
If the difference between the calculated performance level and the first performance level is higher than or equal to the first reference level and the difference between the calculated performance level and the first performance level is greater than or equal to the first reference level, Adjust the performance level, and determine the adjusted performance level as a second performance level. delete 5. The method of claim 4,
The non-volatile memory device stores a performance adjustment program code,
And the controller executes the performance adjustment program code to calculate the new performance level. delete The method of claim 4 or 6, wherein the first reference difference
A ratio with respect to the first performance level, or a ratio with respect to the highest performance level. The method of claim 4 or 6, wherein the first reference difference
And changes depending on a command from the host or a plurality of performance adjustment results. A nonvolatile memory device for nonvolatilely storing data; And
And a controller for controlling the nonvolatile memory device,
The controller comprising:
Calculating a new performance level, selecting a discrete level closest to the calculated performance level among a plurality of predetermined discrete levels,
Comparing the difference between the calculated performance level and the first performance level with a predetermined reference gap,
Determining the selected discrete level as a second performance level if the calculated level gap is lower than or equal to the reference gap,
If the calculated level gap is higher than the reference gap as a result of the comparison, the calculated level gap is adjusted so that the calculated level gap becomes the reference gap, and the discrete level corresponding to the adjusted level gap is referred to as a second performance Level of the performance adjustment module. 11. The method of claim 10,
The non-volatile memory device stores a performance adjustment program code,
Wherein the controller executes the performance adjustment program code to calculate the new performance level and to select a discrete level closest to the calculated performance level among a plurality of predetermined discrete levels. delete A nonvolatile memory device for nonvolatilely storing data; And
And a controller for controlling the nonvolatile memory device,
The controller comprising:
Determining a second performance level using the calculated performance level and operating according to a first performance level, and if the second performance level is determined, Period, and when the performance adjustment period ends, a new performance level is calculated again,
Wherein the performance adjustment period is set in response to a period setting command received from a host. 14. The method of claim 13,
The non-volatile memory device stores a performance adjustment program code,
Wherein the controller executes the performance adjustment program code to calculate the new performance level and to determine the second performance level using the calculated performance level. The semiconductor storage device according to claim 13, wherein the semiconductor storage device
SSD or SD card. 1. A method for adjusting the performance of a semiconductor storage device including a nonvolatile memory device and a controller for controlling the nonvolatile memory device,
(a) operating the semiconductor storage device according to a first performance level;
(b) calculating a new performance level;
(c) comparing the calculated performance level with a predetermined criterion;
(d) determining the calculated performance level as a second performance level according to the comparison result; And
(e) operating the semiconductor storage device according to the second performance level,
Wherein the controller is operative for at least a performance adjustment period in accordance with the second performance level, and further calculates a new performance level at the end of the performance adjustment period,
Wherein the performance adjustment period is set in response to a period setup command received from a host. 17. The method of claim 16,
The predetermined criterion is a minimum level,
The step (d)
Determining the minimum level as the second performance level if the calculated performance level is lower than the minimum level as a result of the comparison; And
And determining the calculated performance level as the second performance level if the calculated performance level is higher than or equal to the minimum level as a result of the comparison. 18. The method of claim 17,
The predetermined criterion is a maximum level,
The step (d)
Determining the maximum level as the second performance level if the calculated performance level is higher than the maximum level as a result of the comparison; And
And determining the calculated performance level as the second performance level if the calculated performance level is lower than or equal to the maximum level as a result of the comparison. 17. The method of claim 16,
Wherein the write performance level of the semiconductor storage device is expressed by any one of a number of write commands processed per unit time, a data amount recorded per unit time, or a plurality of level values. 17. The method of claim 16,
Wherein the read performance level of the semiconductor storage device is expressed by any one of a number of read commands processed per unit time, a data amount read per unit time, or a plurality of level values. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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