KR101695275B1 - Analog to Digital Converter, Image Sensor Having The Same And Method of Converting Analog to Digital - Google Patents

Abstract

Disclosed are an analog-digital converting device, an image sensing device including the same, and a method for the same. According to an aspect of an embodiment, a successive approximation register (SAR) analog-digital converting device comprises: a comparator for generating a comparison result signal by comparing a comparison signal and an input signal obtained from a pixel array including a plurality of unit pixels; a digital-analog converter (DAC) for generating the comparison signal using a reference signal applied from the outside and a switching operation and supplying the comparison signal to the comparator; and an SAR logic unit for sequentially determining digital signals from the highest bit to the lowest bit by using the comparison result signal, outputting a switching signal for adjusting the switching operation to the DAC, and outputting a finally determined digital signal. The SAR logic unit determines whether the input signal is included in a voltage range of the comparison signal by using the comparison signal during a predetermined clock. When the input signal is not included in the voltage range of the comparison signal as a result of determination, the switching operation is adjusted to increase or decrease a level of the comparison signal as much as a predetermined voltage level.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital conversion apparatus, an image sensing apparatus including the same,

The present embodiment relates to an analog-to-digital conversion apparatus, an image sensing apparatus and method including the same, and the like.

The contents described in this section merely provide background information on the present embodiment and do not constitute the prior art.

An image sensing apparatus is an apparatus for converting an optical image signal into an electrical image signal. The image sensing apparatus includes an analog-to-digital converter (ADC) for converting an analog signal (hereinafter referred to as a pixel output voltage) output from a unit pixel into a digital signal.

Generally, when an analog-to-digital conversion device converts an analog signal to a digital signal, each pixel output voltage is individually sensed and converted. However, when the size difference of light incident on a plurality of adjacent pixels is not large, this conversion method consumes excessive power and the conversion speed is slow. Moreover, as the display technology advances, the pixel array becomes HD (High Definition) level or higher, and the power consumption is further increased and the conversion speed is greatly delayed.

Embodiments of the present invention are directed to an analog-to-digital conversion apparatus that reduces power consumption and improves a sensing speed, and an image sensing apparatus and method including the same.

According to an embodiment of the present invention, a comparator that compares an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal to generate a comparison result signal, an externally applied reference signal, A DAC (Digital to Analog Converter) that generates a comparison signal using a switching signal, and supplies the generated comparison signal to a comparator, and sequentially determines a digital signal from a most significant bit to a least significant bit using a comparison result signal, And a SAR (Successvie Approximation Register) logic section for outputting a switching signal for adjusting the SAR signal to generate a comparison signal to the DAC and outputting a finally determined digital signal, wherein the SAR logic section comprises: Is within the voltage range of the comparison signal, and if it does not belong, It provides digital converter - SAR analog that generates a switching signal so as to increase or decrease the level of the comparison signal by.

In an embodiment of the present invention, when the input signal does not fall within the voltage range of the comparison signal, the SAR logic unit continuously lowers the level of the comparison signal by a predetermined voltage level until the state transition of the comparison result signal occurs Or a switching signal to be continuously raised.

In an embodiment of the present invention, the SAR logic section generates a switching signal so that the level of the comparison signal is held from the clock after the point in time at which the state transition of the comparison result signal occurs.

In an embodiment of the invention, the SAR logic portion determines the digital signal such that the comparison signal approximates the input signal if the input signal falls within the voltage range of the comparison signal.

In the embodiment of the present invention, the comparison signal is an analog signal corresponding to the upper N bits (N is a natural number) of the previously stored reference pixel output signal when determining the most significant bit of the digital signal.

According to an embodiment of the present invention, a process of generating a comparison result signal by comparing an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal, Generating a comparison signal by using the comparison result signal, sequentially determining a digital signal from a most significant bit to a least significant bit, generating a switching signal for adjusting to generate a comparison signal, and outputting a finally determined digital signal The process of determining a digital signal and adjusting a switching operation includes a process of determining whether an input signal falls within a voltage range of a comparison signal using a comparison signal during a predetermined clock, The switching signal is set to either lower or raise the level of the comparison signal by the set voltage level (SAR) analog-to-digital conversion method including a process of generating an A / D converter.

In the embodiment of the present invention, in the case where the input signal is not within the voltage range of the comparison signal, the process of generating the switching signal changes the level of the comparison signal by a predetermined voltage level until the state transition of the comparison result signal occurs This is the process of generating a switching signal that is continuously lowered or continuously increased.

In the embodiment of the present invention, the SAR analog-to-digital conversion method further includes a step of generating a switching signal so that the level of the comparison signal is held from the clock after the time point at which the state transition of the comparison result signal occurs.

In an embodiment of the present invention, the SAR analog-to-digital conversion method further comprises the step of determining a digital signal such that, when the input signal falls within the voltage range of the comparison signal, the comparison signal approximates the input signal.

In the embodiment of the present invention, the comparison signal is an analog signal corresponding to the upper N bits (N is a natural number) of the previously stored reference pixel output signal when determining the most significant bit of the digital signal.

According to an embodiment of the present invention, there is provided a liquid crystal display device including a pixel array including a plurality of unit pixels, a timing controller for outputting at least one timing signal for adjusting the operation of the pixel array, And a SAR (Successvie Approximation Register) analog-to-digital conversion device for converting an input signal obtained from a plurality of unit pixels into a digital signal, wherein the SAR analog-digital conversion device compares an input signal with a comparison signal, A comparator for generating a result signal, a comparator for generating a comparison signal using an externally applied reference signal and a switching signal, a digital to analog converter (DAC) for supplying the generated comparison signal to the comparator, To sequentially determine the digital signal from the most significant bit to the least significant bit, and when the DAC generates a comparison signal (SAR) logic section for outputting a switching signal for adjusting the DAC and outputting a finally determined digital signal, wherein the SAR logic section uses the comparison signal during a predetermined clock to determine whether the input signal is within a voltage range of the comparison signal And generates a switching signal to lower or raise the level of the comparison signal by a predetermined voltage level when the determination result does not belong to the determination result.

According to an embodiment of the present invention, a comparator that compares an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal to generate a comparison result signal, an externally applied reference signal, A DAC (Digital to Analog Converter) that generates a comparison signal using a switching signal, and supplies the generated comparison signal to a comparator, and sequentially determines a digital signal from a most significant bit to a least significant bit using a comparison result signal, And a SAR (Successvie Approximation Register) logic section for outputting a switching signal for adjusting the SAR signal to generate a comparison signal to the DAC and outputting a finally determined digital signal, wherein the SAR logic section uses the comparison signal for a pre- It is determined whether it is within the voltage range of the comparison signal. If the DAC is in the coarse mode It provides digital converter - Fine SAR analog mode of generating the switching signal to operate as (Fine Mode).

A process of generating a comparison result signal by comparing an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal, a process of generating a comparison signal using an externally applied reference signal and a switching signal And a step of determining a digital signal sequentially from the most significant bit to the least significant bit using the comparison result signal, generating a switching signal for adjusting to generate a comparison signal, and finally outputting the determined digital signal, And generating a switching signal includes the steps of determining whether the input signal is within the voltage range of the comparison signal using the comparison signal during a predetermined clock period and determining whether the input signal is in a coarse mode or a fine mode Mode (SAR) < / RTI > that includes generating a switching signal to operate with a Successvie Approxim ation Register) analog-to-digital conversion method.

As described above, according to the embodiments of the present invention, there is an effect of reducing the power consumption and improving the sensing speed in the analog-to-digital conversion.

According to the embodiment of the present invention, power consumed in analog-to-digital conversion can be reduced by analog-to-digital converting the target pixel output signal using the upper bits of the stored reference pixel output signal. In particular, when the reference pixel and the target pixel to be converted are adjacent to each other, the power saving effect is large.

According to an embodiment of the present invention, in SAR analog-to-digital conversion, the analog signal to be compared with the subject pixel output signal is based on the upper bits of the stored reference pixel output signal. Therefore, it is not necessary to digitally convert all the bits from the most significant bit to the least significant bit of the target pixel output signal, and only digital conversion is performed on the remaining lower bits except the bit corresponding to the upper bit of the pre-stored reference cell output signal. Thus, there is an effect that analog-to-digital conversion can be performed at high speed.

According to the embodiment of the present invention, it is determined whether it is effective to use the upper bits of the stored reference pixel output signal by sensing the current value. If it is determined that it is invalid, the comparison signal level is increased or decreased by a predetermined voltage level And converts the target pixel output signal into a digital signal in a coarse manner. Thus, the digital conversion is performed in detail only when the signal difference between the reference pixel output signal and the target pixel output signal is small, thereby further improving the speed of analog-to-digital conversion.

In addition, in the case where the digital conversion is performed according to the embodiment of the present invention, since the difference between the reference pixel output signal and the target pixel output signal is large, the difference between the two signals can be determined as an edge. Therefore, it is possible to output the edge information together with the digital conversion without performing a separate image processing process in order to detect an edge like a conventional general image sensor.

1 is a block diagram showing an image sensing apparatus according to an embodiment of the present invention.
2 is a block diagram illustrating a SAR analog-to-digital conversion apparatus according to an embodiment of the present invention.
3 is a circuit diagram showing a part of a SAR analog-digital conversion apparatus according to an embodiment of the present invention.
4A is a circuit diagram for explaining the operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention.
4B is a conceptual diagram for explaining a digital signal determination method by the SAR analog-digital conversion apparatus according to the embodiment of the present invention.
5A is another circuit diagram for explaining the operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention.
5B is another conceptual diagram for explaining a digital signal determination method by the SAR analog-digital conversion apparatus according to the embodiment of the present invention.
6A is another circuit diagram for explaining the operation of the SAR analog-digital conversion device according to the embodiment of the present invention.
6B is another conceptual diagram for explaining a digital signal determination method by the SAR analog-digital conversion apparatus according to the embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. Throughout the specification, when an element is referred to as being "comprising" or "comprising", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise . In addition, '... Quot ;, " module ", and " module " refer to a unit for processing at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description, together with the accompanying drawings, is intended to illustrate exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced.

1 is a block diagram showing an image sensing apparatus according to an embodiment of the present invention.

1, the image sensing apparatus 100 includes a pixel array 110, a timing controller 120, a row selector 130, a readout 140, A register 150, an H-Scanner 160, and a reference generator 170. The H-

The pixel array 110 includes a plurality of photo sensing devices, such as photo diodes or pinned photo diodes. The pixel array 110 senses light using a plurality of photo-sensing elements, converts the light into electrical signals, and generates an image signal. The pixel array 110 may include a plurality of pixels in matrix form, each of which is connected to a plurality of row lines and a plurality of column lines. Each of the plurality of pixels includes a red filter for passing light in a red wavelength region, a green filter for passing light in a green wavelength region, and a blue filter for passing light in a blue wavelength region can do. According to an embodiment, the pixel may comprise a cyan filter, a magenta filter and a yellow filter.

The timing controller 120 outputs a signal capable of adjusting the operation of each of the row selecting unit 130, the reading unit 140, and the reference signal generator 170.

The row selection unit 130 drives the pixel array 110 on a row-by-row basis. For example, the row selection unit 130 can generate a row selection signal. That is, it is possible to decode the row operation signal (for example, the address signal) generated by the timing controller 120 and to output at least one of the row lines constituting the pixel array 110 in response to the decoded row operation signal You can choose. The pixel array 110 outputs the reset signal and the video signal from the row selected by the row selection signal provided from the row selection unit 130 to the reading unit 140.

The reading section 140 includes a CDS (Correlated Double Sampling) circuit 141 and an analog-to-digital conversion device 143. The CDS circuit 141 can perform correlated double sampling of the input reset signal and the video signal. The analog-to-digital converter 143 converts analog signals into digital codes using the reference signals provided from the reference signal generator 170 and the correlated double-sampled signals output from the CDS circuit 141. Although FIG. 1 illustrates CDS circuit 141 and analog-to-digital conversion device 143 as being independently present, it is not necessarily limited thereto and may be a component that performs correlated double sampling and analog-to-digital conversion together Can be implemented.

2 is a block diagram illustrating a SAR analog-to-digital conversion apparatus according to an embodiment of the present invention.

The analog-to-digital converter 143 according to the embodiment of the present invention is a successive approximation register (SAR) analog-digital converter.

2, a SAR analog-digital converter 143 according to an embodiment of the present invention includes an input signal Vin obtained from a pixel array including a plurality of unit pixels, a comparison signal Vdac, A comparator 220 for generating a comparison result signal Vcomp and a comparison signal Vdac using an externally applied reference signal Vref and a switching signal to generate a comparison signal Vdac, (DAC) 240 and a comparison result signal (Vcomp) for supplying the comparison signal Vdac to the comparator 220. The DAC 240 compares the comparison signal Vdac (SAR) logic unit 230 for outputting a switching signal for adjusting the DAC to generate a digital signal, and outputting a finally determined digital signal. The S / H unit 210 may further include an S / H unit 210 for sampling the analog input signal Vin and holding the sampled input signal so that the level of the input signal is not distorted.

The comparator 220 continuously compares the level of the input signal Vsh sampled and held through the S / H unit 210 with the level of the comparison signal Vdac and outputs a high level or a low level Row ) Level comparison result signal Vcomp. For example, if the input signal Vsh is greater than or equal to the comparison signal Vdac to be compared, the comparator 220 can output a signal of a high level, that is, a logic value 1. On the contrary, if the comparison signal Vdac is larger than the input signal Vsh, the comparator 220 can output a signal of a low level, that is, a logic value 0.

The DAC 240 converts a digital signal sequentially input from the SAR logic unit 230 at least one bit unit into an analog comparative signal Vdac. In the case of the most significant bit of the digital signal input to the DAC 240, for example, the value may be arbitrarily set to a logical value 1, and the value of the comparison signal Vdac output from the DAC may be determined by comparing the input signal Vsh have. The output of the comparator 220 is stored in the SAR logic unit 230 and the finally determined digital signal is output to the output of the comparator 220. In this case, do. The number of repetitions can be increased by a desired resolution.

Specifically, when a start signal is applied to the SAR logic unit 230 from the outside, the start signal and the start signal are generated in response to the clock signal CLK from the timing controller 120 and the comparison result signal Vcomp from the comparator 220, Generates a switching signal having a phase difference. The switching signal here is for determining the most significant bit. At this time, the generated switching signal is directly inputted to the DAC 240. The SAR logic unit 230 generates a switching signal for determining a bit having a phase difference from the most significant bit in response to the clock signal CLK and the comparison result signal Vcomp input with the next phase difference, . Further description of the internal configuration and operation of the DAC 240 will be described later with reference to other drawings.

The SAR logic unit 230 sequentially determines the digital signal from the most significant bit to the least significant bit using the high or low level comparison result signal Vcomp input at least one bit unit from the comparator 220, To the DAC 240 to adjust the operation of the DAC 240. The SAR logic unit 230 includes a register (not shown) to store the determined digital signal and finally outputs the determined digital signal.

The clock signal CLK input to the SAR analog-to-digital converter 143 may be generated in the timing controller 120 and the reference signal Vref input to the DAC 240 may be generated in the reference signal generator 170 .

3 is a circuit diagram showing a part of a SAR analog-digital conversion apparatus according to an embodiment of the present invention.

Referring to FIG. 3, the DAC 240 according to the embodiment of the present invention may be a Capacitor Digital Analog Converter (CDAC), but is not limited thereto. The circuit diagram shown in Fig. 3 is merely an example, and may further include other components. However, for convenience of explanation, the DAC 240 is a CDAC and the input signal Vin is converted into a 5-bit digital signal.

The DAC 240 according to the embodiment of the present invention has a structure in which the upper ends of a plurality of capacitors are connected in parallel to output nodes. The plurality of capacitors have a size corresponding to the number of bits, such as C, 2C, 4C, 8C, and 16C (C is a unit capacitor). The DAC 240 includes a dummy capacitor C to which the common mode voltage Vcm is always applied at the lower end without participating in the operation. At least one switching element is connected to the lower end of each capacitor to input a value corresponding to the corresponding bit. Specifically, the DAC 240 performs a switching operation in accordance with a digital signal sequentially input in units of at least one bit from the SAR logic unit 230 to generate a common mode voltage (Vcm), a non-inverted reference voltage ( Vrefp) or an inversion reference voltage (Vrefn). Thereby generating an analog signal corresponding to the input digital signal, that is, a comparison signal Vdac. The noninverting reference voltage Vrefp and the inverting reference voltage Vrefn may be included in the reference signal Vref and the common mode voltage Vcm may be the intermediate value between the noninverting reference voltage Vrefp and the inverting reference voltage Vrefn . FIG. 3 shows an initialization state in which all the charges remaining in the capacitor are removed by applying the common mode voltage Vcm to the upper and lower ends of all the capacitors.

The SAR logic unit 230 according to the embodiment of the present invention determines whether the input signal Vsh falls within the voltage range of the comparison signal Vdac using the comparison signal Vdac during a predetermined clock period, The DAC 240 is adjusted to operate in any one of a coarse mode and a fine mode. When the input signal Vsh is not within the voltage range of the comparison signal Vdac as a result of the determination during the predetermined clock period, the DAC 240 operates in the course mode. On the other hand, when the input signal Vsh is within the voltage range of the comparison signal Vdac And operates in the fine mode.

Referring to FIG. 3, the first capacitor unit 310 determines the most significant bit of the digital code corresponding to the input signal Vin. According to an embodiment, the first capacitor unit 310 may include N capacitors (N is a natural number). According to the embodiment of the present invention, the voltage applied to each of the N capacitors included in the first capacitor unit 310 is determined to output an analog signal Vdac corresponding to the upper N bits of the previously stored reference pixel output signal .

The reference pixel output signal means a signal output from a pixel which is a reference in reading a signal level of a target pixel existing in a pixel array. The signal voltage accumulated in the target pixel is not grasped independently as in the conventional image sensing device but the signal voltage accumulated in the target pixel based on the signal voltage accumulated in the previously obtained reference pixel is determined from the difference do. In order to reduce the power consumption, the difference value is determined and the pixel signal is read. The reference pixel output signal may be stored in a memory unit (not shown) provided in the image sensing device 100. [

According to an embodiment, the reference pixel is located in the same column as the target pixel and may be set to the pixel located in the previous row. Also, according to the embodiment, the reference pixel may be located in the same row as the target pixel, and may be set to the pixel located in the previous column. Further, according to the embodiment, the reference pixel may be set to a pixel located in a predetermined column or row, regardless of the row or column of the target pixel. Further, according to the embodiment, the reference pixel may be set in each of the sections when the pixel array is divided into a plurality of sections including a predetermined number of columns or rows.

The process of determining the operation mode of the DAC 240 is a process for determining whether it is effective to use the upper N bits of the previously stored reference pixel output signal in the digital conversion of the input signal Vin. That is, when the difference between the pre-stored reference pixel output signal and the input signal Vin is small, it is determined to be valid, and when the signal difference is large, it can be determined that the difference is not valid. When it is determined that it is effective to use the upper N bits of the previously stored reference pixel output signal, the DAC 240 operates in the fine mode and conversely operates in the course mode.

The second capacitor unit 320 is for determining the operation mode of the SAR analog-digital conversion device by determining whether the input signal Vin is within the voltage range of the comparison signal Vdac. In accordance with an embodiment of the present invention, the second capacitor portion 320 may be comprised of one capacitor (e.g., 320 to 8C) and may include one or more capacitors (e.g., 4C). That is, a step for determining the operation mode of the SAR analog-digital conversion device is added by further including a capacitor.

3, a capacitor (for example, 8C) included in the second capacitor unit 320 may be connected to a capacitor having the smallest specific gravity among the capacitors included in the first capacitor unit 310 ) May be the same size.

The third capacitor unit 330 may be configured such that when the DAC 240 operates in the fine mode and the most significant bit of the digital code corresponding to the input signal Vin and the input signal Vin are within the voltage range of the comparison signal Vdac And determines the remaining bits excluding the determined bits in the process of determining whether the bits belong to the group.

The fourth capacitor unit 340 may be configured such that when the DAC 240 operates in the course mode, the most significant bit of the digital code corresponding to the input signal Vin and the input signal Vin are within the voltage range of the comparison signal Vdac And determines the remaining bits excluding the determined bits in the process of determining whether the bits belong to the group.

4A is a circuit diagram for explaining the operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention.

4B is a conceptual diagram for explaining a digital signal determination method by the SAR analog-digital conversion apparatus according to the embodiment of the present invention.

4A and 4B, the operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention to output a 5-bit digital signal in the fine mode will be described.

4A shows a circuit diagram of the DAC 240 in the step of determining the most significant bit after the initialization state. In order to determine the most significant bit, the SAR logic 230 outputs a switching signal, which is a digital signal generated using the upper two bits of the stored reference pixel output signal, to the DAC 240. 4 illustrates the use of the upper 2 bits of the previously stored reference pixel output signal, it is not necessarily limited to this, but may vary depending on the embodiment. In the DAC 240, a switching signal having the upper two bits equal to the upper two bits of the reference pixel output signal stored therein and the remaining lower bits except for the upper two bits is input. As a result, the initial comparison signal Vdac, prev output from the DAC 240 of FIG. 4A is Vcm-16LSB + 8LSB. Referring to FIG. 4B, since the input signal Vsh is larger than the initial comparison signal Vdac, prev, the comparator 220 outputs the comparison result signal Vcomp having the logical value 1. SAR logic 230 determines the most significant bit of the digital code to be 1 and generates a switching signal to apply a noninverting reference voltage Vrefp to the lower end of capacitor 8C 420 of DAC 240 to DAC 240 Output.

When the MSB is determined, the SAR analog-to-digital converter performs a determination process to determine an operation mode of the DAC 240 during a predetermined clock. In FIG. 4, the determination process is performed while determining the lower two bits following the most significant bit. If the input signal Vsh does not fall within the voltage range of the comparison signal Vdac in the step of determining one bit, it is determined again in the step of determining the next bit and the operation mode of the DAC 240 is finally determined. Referring again to FIG. 4, the DAC 240 is brought into a state as shown in FIG. 4 (b) by a switching signal input from the SAR logic unit 230. In this case, the comparison signal (Vdac) is the Vcm-16LSB + 8LSB + 8 LSB . Referring to FIG. 4B, since the input signal Vsh is larger than the comparison signal Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logical value 1. SAR logic 230 determines the second bit to be 1 and generates a switching signal such that a noninverting reference voltage Vrefp is applied to the bottom of capacitor 4C 430 of DAC 240. [ The circuit diagram of the DAC 240 to which the switching signal is applied is shown in (c) of FIG. In this case, the comparison signal (Vdac) is the Vcm-16LSB + 8LSB + 8LSB + 4 LSB. Referring to FIG. 4B, since the input signal Vsh is smaller than the comparison signal Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logical value 0. Accordingly, the SAR logic unit 230 determines the third bit to be 0 and determines that the input signal Vsh is within the voltage range of the comparison signal Vdac, Thereby generating a switching signal.

According to the fine mode operation, the remaining lower two bits are determined so that the comparison signal Vdac approximates the input signal Vsh. After determining the third bit, the SAR logic 230 outputs a switching signal such that the inverted reference voltage Vrefn is applied to the lower end of the capacitor 2C 440 of the DAC 240, (D) of Figure 4a. In this case, the comparison signal Vdac becomes Vcm-16LSB + 8LSB + 8LSB + 4LSB -2 LSB. Referring to FIG. 4B, since the input signal Vsh is larger than the comparison signal Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logical value 1. Accordingly, the SAR logic unit 230 determines the fourth bit to be 1 and generates the switching signal so that the non-inverted reference voltage Vrefp is applied to the capacitor C 450 of the DAC 240. The circuit diagram of the DAC 240 to which the switching signal is applied is shown in (e) of FIG. In this case, the comparison signal (Vdac) is the Vcm-16LSB + 8LSB + 8LSB + 4LSB-2LSB + 1 LSB. Referring to FIG. 4B, since the input signal Vsh is smaller than the comparison signal Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logical value 0. Accordingly, the SAR logic unit 230 determines the least significant bit to be 0, and outputs the final digital signal [11010] including the digital signal of the determined upper bit.

5A is another circuit diagram for explaining the operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention.

5B is another conceptual diagram for explaining a digital signal determination method by the SAR analog-digital conversion apparatus according to the embodiment of the present invention.

5A and 5B, an operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention to output a 5-bit digital signal in the course mode will be described.

5A shows a DAC 240 circuit diagram in the step of determining the most significant bit after the initialization state. The description of the step of determining the most significant bit is the same as the description of (a) in FIG.

The most significant bit is determined and a determination process is performed to determine the operating mode of the SAR analog-to-digital converter. As described above, in Fig. 5, a determination is made as to the operation mode in the step of determining two lower bits next to the most significant bit. The description of the step of determining the second bit following the most significant bit is also the same as the description of FIG. 4A (b) described above.

As a result of the comparison in the step of determining the second bit, since the input signal Vsh does not fall within the voltage range of the comparison signal Vdac, determination for determining the operation mode is also performed in the step of determining the third bit. The SAR logic unit 230 outputs a switching signal to the DAC 240 so that the non-inverting voltage Vrefp is applied to the lower end of the capacitor 4C 530 of the DAC 240, The circuit diagram is shown in (c) of FIG. In this case, the comparison voltage (Vdac) is the Vcm-16LSB + 8LSB + 8LSB + 4 LSB. Referring to FIG. 5B, since the input signal Vsh is greater than the comparison voltage Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logical value 1. The SAR logic unit 230 receiving the comparison result signal Vcomp determines that the input signal Vsh does not fall within the voltage range of the comparison voltage Vdac and determines the operation mode as the course mode. Also, the SAR logic unit 230 determines the digital signal of the third bit to be 1.

In the course mode, the SAR logic 230 adjusts the DAC 240 to lower or raise the level of the comparison signal Vdac by a predetermined voltage level. In the case of the fine mode, the increase / decrease width of the comparison signal (Vdac) in the step of determining lower bits below the most significant bit was half of the increase / decrease width of the comparison signal (Vdac) in the previous step. However, in the case of the course mode, the comparison signal Vdac changes by a predetermined voltage level. According to the embodiment of the present invention, the voltage level can be set to be equal to the width of the comparison signal (Vdac) in the step of determining the lower bit after the most significant bit, that is, the second bit.

Referring back to FIG. 5A, the operation of the SAR mode logic circuit 230 will be described with reference to FIG. 5A. The SAR logic 230 determines whether the DAC 240 has increased by a comparison signal Vdac in the step of determining a predetermined voltage level, And generates a switching signal to output the comparison signal Vdac. The circuit diagram of the DAC 240 to which the switching signal is applied is shown in (d) of FIG. In this case, the comparison voltage (Vdac) is the Vcm-16LSB + 8LSB + 8LSB + 4LSB + 8 LSB. Referring to FIG. 5B, since the input signal Vsh is smaller than the comparison voltage Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logic value 0. The SAR logic unit 230 uses the comparison result signal Vcomp to determine the fourth bit as zero.

On the other hand, the comparison result signal Vcomp in the step of determining the third bit has the logical value 1, but the comparison result signal Vcomp in the step of determining the fourth bit has the logic value of 0, State transition occurs. The SAR logic unit 230 according to the embodiment of the present invention adjusts the switching operation so that the level of the comparison signal Vdac is held from the clock after the state transition of the comparison result signal occurs. Therefore, in the step of determining the fifth bit, the comparison signal Vdac remains the same as the previous step, and thus the SAR logic unit 230 determines the least significant bit digital signal to be zero. The finally determined digital signal of the input signal Vin is [11100].

6A is another circuit diagram for explaining the operation of the SAR analog-digital conversion device according to the embodiment of the present invention.

6B is another conceptual diagram for explaining a digital signal determination method by the SAR analog-digital conversion apparatus according to the embodiment of the present invention.

6A and 6B, an operation of the SAR analog-digital conversion apparatus according to the embodiment of the present invention to output a 5-bit digital signal in the course mode will be described.

It is assumed that the determination process up to the third bit described with reference to FIGS. 5A to 5D is performed in the same manner. Referring to FIG. 6B, in the step of determining the fourth bit, since the input voltage Vsh is larger than the comparison voltage Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logical value 1. The SAR logic unit 230 uses the comparison result signal Vcomp to determine the digital signal of the fourth bit to be 1. According to the embodiment of the present invention, the SAR logic unit 230 continuously lowers the level of the comparison signal Vdac every clock by a predetermined voltage level until a state transition of the comparison result signal Vcomp occurs in the course mode Or adjusts the switching operation of the DAC 240 so that it is continuously increased. 6B, since the state transition of the comparison result signal Vcomp has not occurred, the SAR logic 230 sets the comparison signal Vdac at a predetermined voltage level, for example, And adjusts the DAC 240 to increase it by the increase of the comparison signal Vdac. In this case, the circuit diagram of the DAC 240 is shown in FIG. The non-inverting reference voltage Vrefp is applied to the lower end of the capacitor 8C 610 of the fourth capacitor unit 340 and the comparison signal Vdac is Vcm-16LSB + 8LSB + 8LSB + 4LSB + 8LSB + 8LSB. Since the input signal Vsh is smaller than the comparison signal Vdac, the comparator 220 outputs the comparison result signal Vcomp having the logic value 0 and the SAR logic 230 determines the least significant bit as zero. Finally, the digital signal [11110] is output.

When the SAR analog-to-digital conversion apparatus according to the embodiment of the present invention operates in the course mode, that is, when the input signal is not within the voltage range of the comparison signal, the digital signal output from the SAR logic unit 230 is output to the edge Edge information.

The edge information is information indicating a boundary between areas having different gray levels in the image, and mainly occurs between the object and the background, and between the object and another object.

The operation in the course mode means that the signal difference between the pre-stored reference pixel output signal and the input signal Vin is large, so that the digital signal determined in the course mode also includes edge information.

For example, when the SAR analog-to-digital conversion apparatus operates in the course mode because the signal difference between the pixels # 1 and # 2 is large, and the comparison signal level is continuously increased three times, the digital signal [1110] is output. The output digital signal is the digital conversion result of the input signal and also the edge information. For example, if the size of one step in the course mode is 10 LSB, it can be judged that an edge change of 10 + 10 + 10 LSB has occurred relative to the previous value.

In the embodiment of the present invention, the extent to which the signal difference is judged as an edge depends on the designer's setting. For example, if the designer is set to use only 10 LSBs of the output edge information, only the first code of the total 4 codes, '1', is taken.

The image sensing apparatus including the SAR analog-to-digital converter according to the embodiment of the present invention does not need to perform a separate image processing process for edge detection because it can output edge information together with digital conversion. Therefore, edge detection can be performed simply compared with a general image sensor.

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

100: image sensing device 110: pixel array
120: timing controller 130:
140: reading unit 141: CDS
142: ADC 150:
160: H scanner 170: Reference signal generator
210: S / H 220: comparator
230: SAR logic section 240: DAC

Claims (17)

A comparator that compares an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal to generate a comparison result signal;
A DAC (Digital to Analog Converter) for generating the comparison signal using a reference signal and a switching signal applied from an external source, and supplying the generated comparison signal to the comparator; And
A digital signal is sequentially determined from a most significant bit to a least significant bit using the comparison result signal, a switching signal for adjusting the DAC to generate the comparison signal is output to the DAC, and a finally determined digital signal is output A Successive Approximation Register (SAR) logic unit,
The SAR logic unit,
The comparator determines whether the input signal falls within a voltage range of the comparison signal from the comparison result signal during a predetermined clock period and generates the switching signal so as to lower or raise the level of the comparison signal by a predetermined voltage level SAR analog-to-digital converter. The method according to claim 1,
The SAR logic unit,
Wherein when the input signal does not fall within the voltage range of the comparison signal, the level of the comparison signal is continuously lowered or continuously increased for every clock by the predetermined voltage level until a state transition of the comparison result signal occurs, A SAR analog-to-digital converter for generating a switching signal. 3. The method of claim 2,
The SAR logic unit,
And generates the switching signal so that the level of the comparison signal is held from a clock after a time point at which a state transition of the comparison result signal occurs. The method according to claim 1,
The SAR logic unit,
And determines the digital signal such that the comparison signal approximates the input signal if the input signal falls within a voltage range of the comparison signal. The method according to claim 1,
Wherein the digital signal output by the SAR logic comprises edge information when the input signal is not within the voltage range of the comparison signal. 6. The method according to any one of claims 1 to 5,
Wherein the comparison signal comprises:
Wherein when the most significant bit of the digital signal is determined, an analog signal corresponding to the upper N bits (N is a natural number) of the pre-stored reference pixel output signal. Generating a comparison result signal by comparing an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal;
Generating the comparison signal by using a reference signal and a switching signal applied from the outside; And
Determining a digital signal sequentially from a most significant bit to a least significant bit using the comparison result signal, generating a switching signal for adjusting the comparison signal to generate the comparison signal, and outputting a finally determined digital signal,
Wherein the step of determining the digital signal and generating the switching signal comprises:
Determining whether the input signal falls within a voltage range of the comparison signal from the comparison result signal during a predetermined clock; And
And generating the switching signal to lower or raise the level of the comparison signal by a predetermined voltage level when the determination result does not belong to the successive approximation register (SAR) analog-to-digital conversion method. 8. The method of claim 7,
The step of generating the switching signal includes:
Wherein when the input signal does not fall within the voltage range of the comparison signal, the level of the comparison signal is continuously lowered or continuously increased for every clock by the predetermined voltage level until a state transition of the comparison result signal occurs, A SAR analog-to-digital conversion method that is a process of generating a switching signal. 9. The method of claim 8,
And generating the switching signal so that the level of the comparison signal is held from a clock after a time point at which a state transition of the comparison result signal occurs. 8. The method of claim 7,
And determining the digital signal such that the comparison signal approximates the input signal if the input signal falls within a voltage range of the comparison signal. 8. The method of claim 7,
Wherein the determined digital signal comprises edge information when the input signal is not within a voltage range of the comparison signal. 12. The method according to any one of claims 7 to 11,
Wherein the comparison signal comprises:
Wherein when the most significant bit of the digital signal is determined, an analog signal corresponding to an upper N bits (N is a natural number) of a previously stored reference pixel output signal. A pixel array including a plurality of unit pixels;
A timing controller for outputting at least one timing signal for adjusting the operation of the pixel array and the output of the plurality of unit pixels;
And a SAR (Successive Approximation Register) analog-to-digital converter for converting an input signal obtained from the plurality of unit pixels into a digital signal,
The SAR analog-to-
A comparator for comparing the input signal with a comparison signal to generate a comparison result signal;
A DAC (Digital to Analog Converter) for generating the comparison signal using a reference signal and a switching signal applied from an external source, and supplying the generated comparison signal to the comparator; And
A digital signal is sequentially determined from a most significant bit to a least significant bit using the comparison result signal, a switching signal for adjusting the DAC to generate the comparison signal is output to the DAC, and a finally determined digital signal is output SAR Logic portion,
The SAR logic unit,
The comparator determines whether the input signal falls within a voltage range of the comparison signal from the comparison result signal during a predetermined clock period and generates the switching signal so as to lower or raise the level of the comparison signal by a predetermined voltage level An image sensing device. 14. The method of claim 13,
The SAR logic unit,
Wherein when the input signal does not fall within the voltage range of the comparison signal, the level of the comparison signal is continuously lowered or continuously increased for every clock by the predetermined voltage level until a state transition of the comparison result signal occurs, An image sensing device for generating a switching signal. 15. The method of claim 14,
The SAR logic unit,
And generates the switching signal such that a level of the comparison signal is held from a clock after a time point at which a state transition of the comparison result signal occurs. A comparator that compares an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal to generate a comparison result signal;
A DAC (Digital to Analog Converter) for generating the comparison signal using a reference signal and a switching signal applied from an external source, and supplying the generated comparison signal to the comparator; And
A digital signal is sequentially determined from a most significant bit to a least significant bit using the comparison result signal, a switching signal for adjusting the DAC to generate the comparison signal is output to the DAC, and a finally determined digital signal is output A Successive Approximation Register (SAR) logic unit,
The SAR logic unit,
Wherein the DAC determines whether the input signal falls within a voltage range of the comparison signal from the comparison result signal during a predetermined clock period and outputs the comparison signal to the switching unit so that the DAC operates in a coarse mode or a fine mode, SAR analog-to-digital converter for generating a signal. Generating a comparison result signal by comparing an input signal obtained from a pixel array including a plurality of unit pixels with a comparison signal;
Generating the comparison signal by using a reference signal and a switching signal applied from the outside; And
Determining a digital signal sequentially from a most significant bit to a least significant bit using the comparison result signal, generating a switching signal for adjusting the comparison signal to generate the comparison signal, and outputting a finally determined digital signal,
Wherein the step of determining the digital signal and generating the switching signal comprises:
Determining whether the input signal falls within a voltage range of the comparison signal from the comparison result signal during a predetermined clock; And
And generating the switching signal to operate in a coarse mode or a fine mode according to a result of the determination.

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