KR101689527B1 - Apparatus and method for searching address based on hashing using temporal locality - Google Patents

Abstract

A hash-based address search apparatus includes a controller receiving an address input signal according to an address search request, an address pair synthesizer generating an address pair from a command address and a destination address, A hash generating unit for generating a hash key for search, an address information storing unit for receiving a pair of addresses and a hash key and synthesizing one address information, a hash table for receiving address information, And an address retrieval unit for retrieving whether the input address information is stored in the address pair hash table and outputting the retrieval result.

Description

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a hash-based address search apparatus and method using temporal locality,

The present invention relates to an address searcher for searching an address value of an inspection target in an address pair table. More specifically, the present invention relates to an address reader for searching a string of addresses, The present invention relates to an address search apparatus and method capable of determining at a high speed whether address values match based on a hashing technique.

의 비교가 필요하며, 이를 적용한 실험에서도 약 25%의 과부하를 보였다.The address detector is a device for searching the address pair to be inspected in the address pair table, and the address pair table is a memory device for storing a pair of an instruction address and a destination address. The address search technique is performed by comparing the address of the object to be tested with the address table to confirm whether or not the address is matched. This technique has a drawback in that the number of comparisons increases as the size of the address table increases, and the overload increases accordingly. Therefore, in order to improve the performance of the address search, the number of comparisons must be reduced. According to the prior art documents presented below, when binary search is used to reduce the number of address search comparisons,

, And it was found that the overload was about 25% even in the experiment using this.

As an alternative to this, if the hashing technique is applied to the address pair table, the comparison frequency can be maintained even when the size of the table is increased. That is, constructing a uniformly distributed hash table and retrieving only the data with the same index will reduce the overload than when performing the full test. Therefore, a more specific technical means for implementing such a hash table in an address searcher is required.

 Ellis Horowitz, Sartaj Sahni, Dinesh P.Mehta, Fundamentals of Data Structures in C ++, 2nd edition, Silicon Press, pp. 27-29, 2006.  T. H. Kim, I. H. Seong, K. S. Han, C. W. Pyo, "Effect of Integrity Checking for Indirect Branch Address Using Binary Search," Proc. of the KIISE 2012 Fall Conference, vol.39, no.2 (A), pp.43-45, 2012.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problem that the number of comparisons increases as the size of the address table increases in the conventional address search technique, To overcome the technical limitations in which there is no practical technical means for finding the address pair.

According to an aspect of the present invention, there is provided an address search apparatus comprising: a controller receiving an address input signal according to an address search request; An address pair synthesizer for generating one address pair from the command address and the destination address; A hash generating unit for generating a hash key for searching from the instruction address and the destination address; An address information storage unit for receiving the address pair and the hash key and synthesizing one address information; An address collector for receiving the address information and recording the address information in an address pair hash table; And an address search unit for searching whether the received address information is stored in the address pair hash table, and outputting the search result.

In the address searching apparatus according to an embodiment, a hash address for accessing the address pair hash table is generated by extracting and connecting a predetermined number of lower bit values from the command address and the destination address. The hash address may be obtained by extracting lower m bits (m is a positive integer smaller than the total number of bits) from each of the instruction address and the destination address and outputting one of the extracted two bit values as a left shift shifted to an upper bit through a left shift operation, and then combined with the remaining one of the extracted two bit values through a bit sum operation.

In the address searching apparatus according to an embodiment, the address pair combining unit positions the (m-1) th to (0th) bit strings of the instruction address in the (k-1) (m is the number of bits of the command address and the destination address, k is the number of bits of the composite bit (m-1) to 0th bit) K = 2m as the number of bits of the column).

In the address searching apparatus according to an embodiment, the hash generation unit extracts a bit string of i bits from an arbitrary position of the instruction address, extracts a bit string of j bits from an arbitrary position of the destination address, (K is the number of bits of the composite bit string, k = i + j) by combining the bit strings.

In the address search apparatus according to an embodiment, the address pair hash table includes an address pair pool storing all address pairs; A chain index table for forming pairs of addresses causing conflicts when address pairs are stored in a bucket chain of a circular linked list structure; And a bucket header table storing an index value of the address pair pool and a length of the bucket chain. If the index stored in the bucket header table is not a search target address pair, the address search unit searches for a pair of addresses in the bucket header table until the search target address pair is found, Chain, and when the search target address pair is found in the bucket chain, the chain start index stored in the bucket header may be updated to a pool index of the search target address pair.

Furthermore, the present invention provides a computer-readable recording medium having recorded thereon a program for causing a computer to execute a method of controlling each element of the address search apparatus described above.

In embodiments of the present invention, a hashing technique is applied to extract a certain number of lower-order bit values from a command address and a destination address, thereby ensuring a fast access speed to the address pair table, and a low- In addition, it is possible to improve the retrieval efficiency by reducing the number of collisions of hash addresses by introducing a circular list structure in the address storing process, and by using indexes of data recently retrieved from the buckets in the address pair retrieval process It is possible to obtain a caching effect that can always obtain the address pair index searched recently, and as a result, the search time can be shortened.

1 is a block diagram illustrating a hash-based address search apparatus according to an embodiment of the present invention.
2 is a diagram illustrating a process of generating an address pair combining unit address pair in the address searching apparatus of FIG. 1 according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining a process of generating a hash key by a hash generating unit in the address searching apparatus of FIG. 1 according to an embodiment of the present invention.
4A and 4B are diagrams illustrating an address search process and an address pair hash table applied with hashing in the address search apparatus of FIG. 1 according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a bucket chain ratio with a chain length of 1 for a bit number as a simulation result using an address search apparatus according to embodiments of the present invention.
FIG. 6 is a diagram illustrating a ratio of the number of address pair search times to the number of bits as a simulation result using the address search apparatus according to the embodiments of the present invention.
FIG. 7 is a diagram illustrating a bit position of a destination address according to a bit pattern combination as a simulation result using an address search apparatus according to embodiments of the present invention.

Before describing embodiments of the present invention in detail, technical solutions adopted by embodiments of the present invention will be introduced to solve the problems of the conventional address search technology. In the following description, a hash-based address detector for a 32-bit memory is described as an embodiment. However, those skilled in the art will recognize that the technical principles of the present invention are limited to such a limited number of bits of memory It can be seen that it is not.

와 목적지 주소

의 쌍

의 집합으로 해시 테이블(hash table)을 구성한다. 검색 성능은 주소 쌍 테이블의 키 값을 구하기 위한 해시 함수와 해시 값의 충돌 처리 방식에 따라 결정된다.As noted above, a good data structure is needed to quickly determine whether two address values match. Instruction address that occurs at execution time

And destination address

Pair of

And a hash table. The search performance is determined by the hash function for obtaining the key value of the address pair table and the collision processing method of the hash value.

라 하면 각 주소로부터 하위

비트와 하위

비트를 추출하여 다음의 수학식 1과 같은 해시 함수를 제시할 수 있다.The hash address for accessing the address pair table can be extracted by connecting the lower bit of the address value. The total number of bits

If you want to

Bit and sub

Bits can be extracted to present a hash function as shown in Equation 1 below.

와 목적지 주소

의 하위

비트를 입력 값으로 받는 해시 함수

을 나타낸다.

와

각각에서 하위

비트를 추출하여, 이 중 하나의 비트 값을 길이

만큼 레프트 시프트(left shift) 연산으로 상위 비트로 옮긴 후 비트 합 연산으로 두 비트 값을 합친다. 본 발명의 실시예들에서는 명령어 주소

를 상위 비트의 대상으로 구성하였다. 주소의 하위

비트는 값의 변화가 가장 빈번한 부분이기 때문에 다른 부분의 비트들을 사용하는 것보다 해시 주소의 충돌을 감소시키는데 효과적이다.The above equation (1)

And destination address

Child

A hash function that takes a bit as an input value

.

Wow

In each sub

Extracts one bit of the bit length,

Shift to the upper bit by a left shift operation, and add the two bit values by the bit sum operation. In the embodiments of the present invention,

Is composed of the upper bits. Child of address

Since bits are the most frequent part of the change in value, it is more effective to reduce the collision of hash addresses than to use bits in other parts.

Particularly, in the address pair table adopted by the embodiments of the present invention, iterative search of the same address pair information occurs. In order to improve the performance, it is necessary to utilize the time locality in the retrieval in consideration of the case where the repetitive operation always occurs like the server program. For this, the overhead can be reduced by continuously searching the address pair table adopted by the embodiments of the present invention in the order of addition from the address pairs newly searched for. In particular, this temporal locality can be achieved by forming a bucket of the hash into a circular structure and storing the index for recently retrieved data.

Hereinafter, embodiments of the present invention for solving the above-mentioned technical problems will be described in detail with reference to the drawings. In the following description and the accompanying drawings, detailed description of well-known functions or constructions that may obscure the subject matter of the present invention will be omitted. It is to be noted that the same components are denoted by the same names and reference numerals as possible throughout the drawings.

1 is a block diagram illustrating a hash-based address search apparatus 100 according to an embodiment of the present invention.

The control unit 10 receives an address input signal corresponding to an address search request and controls other components of the address search apparatus 100. When an address search request is generated, an address input signal is input to the control unit.

The address pair combining unit 20 generates one address pair from the command address and the destination address, and the hash generation unit 30 generates a hash key for searching from the command address and the destination address. The address pair combining unit 20 and the hash generating unit 30 generate an address pair and a hash key, respectively, to which an instruction address and a destination address are applied, respectively, and output the address pair and the hash key to the address information storage unit 40.

The address information storage unit 40 receives the address pair and the hash key, combines the address information, and outputs the combined address information to the address collection unit 50 and the address search unit 60.

The address collecting unit 50 receives the address information from the address information storage unit 40 and records the address information in an address pair hash table 70.

The address searching unit 60 receives the address information from the address information storing unit 40 and searches whether the inputted address information is stored in the address pair hash table 70 and outputs the search result. At this time, the retrieved result can be outputted as true or false.

In particular, the hash address for accessing the address pair hash table 70 takes advantage of a hashing technique for ensuring a fast access speed by extracting and connecting a certain number of lower bit values from the instruction address and the destination address, , And at the same time, the lower bit having the most frequent change in the value is used, so that the search delay due to the hash address collision can be prevented.

More specifically, the hash address extracts lower m bits (m is a positive integer smaller than the total number of bits) from the instruction address and the destination address, and extracts any one of the extracted two bit values by a length m Shifted to an upper bit through a left shift operation, and then combined with the remaining one of the extracted two bit values through a bit sum operation.

FIG. 2 is a diagram for explaining a process of generating an address pair by the address pair combiner 20 in the address search apparatus of FIG. 1 according to an embodiment of the present invention. The conceptual structure of the address pair combiner 20 Respectively.

First, the address pair combining unit 20 receives an instruction address and a destination address as inputs. In order to combine the instruction address and the destination address, the 31st to 0th bit of the instruction address is placed in the 63th to 32nd synthesis bitstream, and the 31st to the 0th bitstream of the destination address 31 to the 0th synthesis bit string. The value of the 64-bit address pair thus synthesized is transferred to another device (for example, the address information storage unit 40 in FIG. 1) via the output.

In summary, the address pair combining unit 20 places the (m-1) th to (0) th bit strings of the instruction address in the (k-1) Th bit stream to the (m-1) th to the 0th synthesized bit stream, thereby generating a synthesized k bit address pair. Here, m is the number of bits of the command address and the destination address, and k is the number of bits of the composite bit string, which is k = 2m.

FIG. 3 is a diagram for explaining a process of generating a hash key by the hash generation unit 30 in the address search apparatus of FIG. 1 according to an embodiment of the present invention. The conceptual structure of the hash generation unit 30 is shown in FIG. Respectively.

First, the hash generation unit 30 receives an instruction address and a destination address as inputs. As described above, in the case of a 32-bit memory, a hash key is generated by extracting arbitrary j-bit strings from an arbitrary i-bit string and a destination address bit string in an instruction address bit string. An arbitrary i bit string is located above the hash bit string and any j bit string can be located below the hash bit string. The combined hash key is passed through the output to another device (e.g., address information storage 40 in FIG. 1).

In summary, the hash generation unit 30 extracts a bit string of i bits from an arbitrary position of the address of the instruction, extracts a bit string of j bits from an arbitrary position of the destination address, and then combines the bit string And generates a synthesized k-bit hash key. Here, k is the number of bits of the composite bit stream and k = i + j is satisfied.

4A and 4B are diagrams illustrating a structure of an address search process and an address pair hash table 70 to which hashing is applied in the address search apparatus 100 of FIG. 1 according to an embodiment of the present invention.

에 저장하고, 충돌을 일으키는 주소 쌍들은 체인 인덱스 테이블(chain index table)(73)

를 사용하여 원형 연결 리스트(circular linked list) 구조로 버킷 체인(bucket chain)을 이루게 한다. 버킷 헤더 테이블(bucket header table)(71)

의 각 레코드는 주소 쌍 풀

의 인덱스 값과 버킷 체인의 길이를 저장한다.The address search apparatus 100 according to the embodiments of the present invention has a bucket chaining table structure. For this purpose, all address pairs are address pool pool 72,

The address pairs causing the collision are stored in a chain index table 73,

To form a bucket chain with a circular linked list structure. A bucket header table (71)

Each record in the address pair pool

And the length of the bucket chain.

에 저장된 색인이 찾고 있는 주소 쌍이 아니면, 주소 쌍을 찾을 때까지 혹은 체인 길이만큼 원형 체인을 검사한다. 체인 내에서 주소 쌍이 확인되면 버킷 헤더에 저장된 체인 시작 인덱스를 검색된 주소 쌍의 풀 인덱스로 갱신한다. 이러한 갱신 방식에 따를 경우, 버킷 체인의 헤더는 항상 최근에 검색한 주소 쌍 인덱스를 갖고 있게 되어 캐싱(caching) 효과를 볼 수 있다. 반복문 안에서 발생하는 간접 분기는 동일한 목적지로 제어 흐름을 이동할 가능성 높기 때문에 주소 쌍 풀(72)

의 동일 주소 쌍을 반복해서 검색하게 되는데, 두 번째 검색부터는 1 회의 검색으로 두 주소 값의 일치 여부를 판단할 수 있게 되는 장점을 갖는다.When retrieving the address pair, the bucket header table (71)

If the stored index is not the address pair you are looking for, check the circular chain until you find the address pair or by the chain length. If an address pair is found in the chain, the chain start index stored in the bucket header is updated with the full index of the retrieved address pair. According to this update method, the header of the bucket chain always has the address pair index searched recently, and the caching effect can be seen. Since the indirect branching occurring in the loop is highly likely to move the control flow to the same destination,

It is possible to judge whether the two address values coincide with each other by searching one time from the second search.

In summary, the address pair hash table 70 adopted by the embodiments of the present invention includes an address pair pool 72 for storing all address pairs, address pairs for causing conflicts during address pair storage, a chain index table 73 formed by a bucket chain of a circular linked list structure and a bucket header table 73 for storing the index value of the address pair pool and the length of the bucket chain. table (71).

In particular, when the address pair is searched, the address searching unit (60) determines whether the index stored in the bucket header table (71) is not a search target address pair, until the search target address pair is found, It is preferable to check the bucket chain of the connection list structure and update the chain start index stored in the bucket header to the pool index of the search target address pair when the search target address pair is found in the bucket chain Do.

Hereinafter, a performance test is performed to verify the efficiency of the address searcher according to the embodiments of the present invention, and the results are analyzed. The experimental environment consisted of a Fedora Core 14 Linux (kernel version 2.6.35.14-106) system with a network with Intel Core 2 Quad Q6600 2.40GHz x86 processor and 4GB memory. Pin (version 2.11 (49303)) and compiler gcc (version 4.6.3) were used for the dynamic measurement tool. Performance tests of the address pair table were performed on the SPECint 2006 (version 112 (v1.1)) benchmark.

(1) Collision check of hash address

5 is a diagram illustrating a bucket chain ratio having a chain length of 1 for a number of bits as a simulation result using an address search apparatus according to embodiments of the present invention. The ratio of one bucket chain length was measured. The address pair table was formed by the address pair trace generated by the program measurement tool and the address pair search experiment was performed by the same trace. The number of bits extracted from source address and destination address was varied from 5 to 10.

에 대한 체인 길이가 1인 버킷 체인의 비율을 나타낸다. 이 지표는

이 주는 해시 주소의 충돌 가능성이 얼마나 높은지를 간접적으로 보여주고 있다. 모든 벤치마크에 대하여

이 커질수록 길이가 1인 버킷 체인의 비율이 증가한다.

이면 길이가 1인 비율이 최대 99%, 평균 97%를 나타냈다. 즉,

이 일정 수준 이상으로 커지면 해시 주소가 거의 충돌하지 않음을 알 수 있다.5 shows the number of bits per program in SPECint 2006

Lt; RTI ID = 0.0 > 1 < / RTI > This indicator

This note indirectly shows how likely the hash address is likely to collide. For all benchmarks

The larger the ratio, the greater the ratio of the bucket chain with a length of one.

The ratio of one person to the other person was 99% and 97%, respectively. In other words,

If it is larger than a certain level, the hash address hardly collides.

(2) Caching function of address pair table

FIG. 6 is a diagram illustrating a ratio of the number of address pair search times to the number of bits as a result of a simulation using the address search apparatus according to the embodiments of the present invention. The number of searches was 1.

에 대한 주소 쌍 검색 횟수가 1인 비율을 나타낸다. 이 지표는 체인을 원형 연결 리스트로 구성하였을 때의 캐싱 효과를 보여 준다. 표의 가장 왼쪽 열은 프로그램 명을, 오른쪽 열은 간접 분기 명령어 주소와 목적지 주소에서 추출한 비트 수

에 따라 나타나는 비율을 의미한다. 모든 프로그램에 대하여

이 커질수록 비율이 증가함을 알 수 있다.

이상이면 정상적인 간접 분기 명령의 경우 평균 1.01회의 비교로 검색을 마칠 수 있음을 확인할 수 있다. 이와 같은 현상은 비트 수

이 작아서 해시 테이블에 길이 1을 가지는 주소 쌍의 체인 비율이 낮더라도 원형 체인 구조가 주는 캐시 효과로 성능이 향상될 수 있음을 보여준다. 실험을 통해 활발히 변화하는 하위 주소 비트 범위는

정도임을 확인하였다.

이상일 경우는 성능에 별다른 영향을 주지 않는다. 이 현상은 대부분의 간접 분기가 64 KB 범위 내에서 이동함을 의미한다.FIG. 6 shows the number of bits per program of SPECint 2006

The number of address pair search times is 1. This indicator shows the caching effect when a chain is composed of circular linked lists. The leftmost column of the table shows the program name, the right column shows the number of bits extracted from the indirect branch instruction address and destination address

. ≪ / RTI > About all programs

It is seen that the ratio increases.

, It can be confirmed that the search can be terminated by an average of 1.01 times in the case of the normal indirect branch instruction. This phenomenon occurs when the number of bits

Shows that even if the chain ratio of the address pair having the length 1 in the hash table is low, the cache effect of the circular chain structure can improve the performance. Experimental results show that the active sub-address bit range

Respectively.

The performance is not significantly affected. This phenomenon means that most of the indirect branches move within the 64 KB range.

(3) Bit pattern analysis

The hash value is generated according to the lower bit combination of the address pair. As the hash value collision increases, the number of objects to be compared increases, which is a major cause of performance overload. Analyzing a bit pattern with fewer collisions reduces the number of address lookups required to search and reduces overload.

For the bit pattern analysis, an experiment was performed to compare the number of indirect branch address pairs collected. In the experiment, 403.GCC of SPEC2006 was utilized. In this program, we collected 1,968,445,893 indirect branch instruction address pairs to identify 18,729 unique address pairs that do not overlap. The unique address pair contains 17,500 unique instruction addresses and 3,675 unique destination addresses. We confirmed that the command address has a minimum distance of 2 bytes from the adjacent command address and the destination address has the minimum distance of 3 bytes from the adjacent destination address. This means that it is not necessary to use the least significant bit when generating the hash value.

FIG. 7 is a diagram illustrating a bit position of a destination address according to a bit pattern combination as a simulation result using an address search apparatus according to embodiments of the present invention.

와 목적지 주소

의 하위 비트를 추출하여 활용하였다. 도 7의 (a)는

와

각각에서 하위 12번부터 1번까지의 12비트를 추출하여 24비트로 조합한 경우로 18,645개의 고유 주소 쌍을 생성하였다. 도 7의 (b)는

와

각각에서 하위 10번부터 1번까지의 10비트를 추출하여 20비트로 조합한 경우로 18,265개의 고유 주소 쌍을 생성하였다. 도 7의 (c)는

와

각각에서 하위 9번부터 0번까지의 10비트를 추출하여 20비트로 조합한 경우로 18,168개의 고유 주소 쌍을 생성하였다. 도 7의 (d)는

로부터 하위 9번부터 0번까지의 10비트를,

로부터 하위 9번부터 1번까지의 9비트를 추출하여 19비트로 조합한 경우로 17,716개의 고유 주소 쌍을 생성하였다.The bit pattern combination includes a command address

And destination address

And extracts the low - order bits. Figure 7 (a)

Wow

In the case of extracting the 12 bits from the lower 12th to the 1th in each and combining them with 24 bits, 18,645 unique address pairs are generated. 7 (b)

Wow

In the case of extracting 10 bits from the lower 10th to 1st in each and combining them with 20 bits, 18,265 unique address pairs are generated. 7 (c)

Wow

In the case of extracting 10 bits from the lower 9th to 0th in each and combining them with 20 bits, 18,168 unique address pairs are generated. 7 (d)

10 bits from the lower 9th to the 0th bit,

9 bits from the lower 9th to the 1st 9th bit are extracted and combined into 19 bits to generate 17,716 unique address pairs.

It can be seen that the combination of bit patterns is appropriate in Fig. 7 (b). FIG. 7A requires space for storing 16 megabytes (MB), but space is wasted because the number of address pairs required for actual storage is small. 7 (c) has a smaller number of unique address pairs as compared with FIG. 7 (b), so that more collisions may occur. 7 (d) generates 17,716 unique address pairs less than the actual number of unique address pairs of 18,729, so that the number of comparisons increases because the number of collisions increases.

As described above, in order to improve the performance of the address detector, it is necessary to reduce the number of comparisons. Using a bit combination of at least 10 bits from an address pair as a hash value, most of the address pairs can be retrieved at a time. Also, repeated addresses can be searched at once, which can effectively reduce the overload due to the search. As a result of the above bit pattern analysis, it is confirmed that the bit combination except for the least significant bit is more effective in performance.

According to the embodiments of the present invention, a hashing technique is applied to extract a certain number of lower-order bit values from the instruction address and the destination address and to connect them, thereby ensuring a fast access speed to the address pair table, By extracting and using frequent lower bits, it is possible to prevent waste of space and reduce the number of collisions of hash addresses, thereby improving search efficiency. In addition, a circular list structure is introduced in the address storing process, By utilizing the temporal locality of storing the index of the retrieved data, it is possible to obtain a caching effect that always obtains the address pair index searched recently, and as a result, the search time can be shortened.

In particular, there is a difference in the search method between the conventional cache apparatus and the cache scheme proposed by the embodiments of the present invention. A common cache device quickly accesses data values copied from memory in advance using a hash table. At this time, if the hash value collides with each other, it is necessary to perform sequential search to check the presence or absence of the data value in the cache device, so that an additional overload occurs. However, in this address search device, the data values are sequentially searched and the data is searched from the last confirmed data value. This has the advantage of being able to effectively utilize the locality in case of referring to the same address value continuously, such as a loop statement. In addition, since data values are linked in a circular list form, data values having the same hash value can be searched without missing.

Meanwhile, in the embodiments of the present invention, in particular, a series of operation methods for controlling each component of the address search apparatus can be implemented by a computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device and the like, and also a carrier wave (for example, transmission via the Internet) . In addition, the computer-readable recording medium may be distributed over network-connected computer systems so that computer readable codes can be stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for implementing the present invention can be easily deduced by programmers skilled in the art to which the present invention belongs.

The present invention has been described above with reference to various embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

100: address search device
10:
20: address pair combining unit
30: hash generating unit
40: address information storage unit
50: address collecting section
60: address search section
70: Address pair hash table
71: Bucket header table
72: address pair pool
73: Chain index table

Claims (7)

A control unit receiving an address input signal according to an address search request;
An address pair synthesizer for generating one address pair from the command address and the destination address;
A hash generating unit for generating a hash key for searching from the instruction address and the destination address;
An address information storage unit for receiving the address pair and the hash key and synthesizing one address information;
A bucket chain of a circular linked list structure is formed by combining the address pairs causing the collision when the address information is stored upon receipt of the address information, and an address pair hash table an address collecting unit for storing the address in a hash table; And
And an address pair search unit for searching whether or not the input address information is stored consecutively in the order in which the address pair is added to the address pair hash table from the recently searched address pair, And an address search unit for searching for an address. The method according to claim 1,
The hash address for accessing the address pair hash table may be,
And extracting and connecting a predetermined number of lower bit values from the command address and the destination address. 3. The method of claim 2,
The hash-
(M is a positive integer smaller than the total number of bits) from the instruction address and the destination address, and performs a left shift operation on any one of the extracted two bit values by a length m And then combining the bit values of the remaining one of the two extracted bit values through a bit sum operation. The method according to claim 1,
The address pair combiner comprises:
(M-1) to (0) th bit string of the address of the instruction is located in the (k-1) th to (M is the number of bits of the command address and the destination address, and k is the number of bits of the composite bit string, k = 2m). The method according to claim 1,
Wherein the hash-
Extracts a bit string of i bits from an arbitrary position of the instruction address, extracts a bit string of j bits from an arbitrary position of the destination address, and combines the bit strings to generate a synthesized k-bit hash key k Is a number of bits of the composite bit string, k = i + j). The method according to claim 1,
Wherein the address pair hash table comprises:
An address pair pool storing all address pairs;
A chain index table for forming pairs of addresses causing conflicts when address pairs are stored in a bucket chain of a circular linked list structure; And
And a bucket header table storing an index value of the address pair pool and a length of the bucket chain. The method according to claim 6,
When searching for an address pair,
If the index stored in the bucket header table is not a search target address pair, checks the bucket chain of the circular linked list structure until the search target address pair is found or by the length of the chain,
And updates the chain start index stored in the bucket header to a pool index of the search target address pair when the search target address pair is found in the bucket chain.

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