KR101658076B1 - DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same - Google Patents
DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same Download PDFInfo
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- KR101658076B1 KR101658076B1 KR1020150008929A KR20150008929A KR101658076B1 KR 101658076 B1 KR101658076 B1 KR 101658076B1 KR 1020150008929 A KR1020150008929 A KR 1020150008929A KR 20150008929 A KR20150008929 A KR 20150008929A KR 101658076 B1 KR101658076 B1 KR 101658076B1
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- impulse receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
- H04L25/0296—Arrangements to ensure DC-balance
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- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
Abstract
The DC compensator of the UWB impulse receiver according to the present invention includes an analog circuit for receiving a first signal and a second signal as differential signals through a first stage and a second stage, A DC comparator of an ultra-wideband impulse receiver comprising a comparator for outputting a first signal; a switch connected between said first stage and said second stage; And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal, and the switch is turned on and off according to the control signal.
Description
The present invention relates to an ultra-wideband (UWB) impulse receiver. More particularly, it relates to an analog DC correction circuit of an ultra-wideband impulse receiver and to an ultra wideband impulse receiver including the same.
In an application field of an ultra-wideband wireless communication chip or a radar sensor, in a receiver circuit using a semiconductor integrated circuit, a base-band analog (BBA) processing an envelope signal of an impulse removing a high- ) Low frequency noise, DC offset and / or DC noise of the circuit may cause problems such as lowering the sensitivity of the receiver and further saturating the circuit.
In particular, in the case of an ultra-wideband signal, the baseband signal is also difficult to configure as a signal having a high bandwidth of 500 MHz or more. At this time, DC noise and / or DC voltage may be generated due to the non-ideal characteristics of the circuit, which may degrade receiver performance.
When the frequency of the baseband signal is relatively low, a technique of removing DC noise, low frequency noise, and / or DC offset voltage through a circuit such as conventional DC offset canceling (DCOC) has been used. However, since the baseband signal has a very high frequency in the case of an ultra-wideband receiver, the DCOC circuit for this purpose is very difficult to design and the possibility of oscillation is high. In addition, current consumption of the DCOC circuit and a chip area . In addition, in the UWB receiver, since the frequency of the baseband signal is high, it is difficult to use the conventional circuit structure, which makes it difficult to configure a circuit for setting the common mode voltage to the intermediate voltage of the power supply voltage, Since the common mode voltages are different from each other in each constitution of the band circuit, separation of the bias voltage is required.
There is a technique in which a DC block capacitor is connected in series to a signal line between circuit configurations in order to eliminate a DC voltage without using a DCOC circuit and solve a problem in which common mode voltages are different from each other. However, in this case, the DC voltage may shake for a certain period of time after the envelope voltage of the impulse is generated due to the DC blocking capacitor. Such shaking of the DC voltage may be mistaken as a signal, and erroneous data recognition may occur. Therefore, it is necessary to prevent the undesired fluctuation of the DC voltage generated by the DC blocking capacitor while reducing the current consumption and the circuit area of the chip.
It is an object of the present invention to provide a DC compensator of an ultra-wideband impulse receiver that eliminates undesired DC offset and / or DC voltage shaking in a baseband analog circuit of an ultra-wideband impulse receiver receiving a high frequency impulse signal, To provide an ultra wideband impulse receiver.
It is another object of the present invention to provide a DC compensator of an ultra-wideband impulse receiver capable of solving the problem of reception sensitivity deterioration due to generation of undesired DC voltage and / or shaking caused by using a DC blocking capacitor in an ultra-wideband impulse receiver To provide an ultra wideband impulse receiver.
The DC compensator of the UWB impulse receiver according to the present invention includes an analog circuit for receiving a first signal and a second signal as differential signals through a first stage and a second stage, A DC comparator of an ultra-wideband impulse receiver comprising a comparator for outputting a first signal; a switch connected between said first stage and said second stage; And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal, and the switch is turned on and off according to the control signal.
An ultra-wideband impulse receiver according to the present invention includes: an analog circuit unit receiving a first signal and a second signal, which are differential signals, through a first stage and a second stage; A comparator that receives a signal of the analog circuit unit and outputs a data signal as an output signal; A switch connected between said first end and said second end; And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal. The turn-on and turn-off of the switch are controlled according to the control signal.
Embodiments of the disclosed technique may have effects that include the following advantages. It should be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, since the embodiments of the disclosed technology are not meant to include all such embodiments.
According to the present invention, there is provided a DC compensator of an ultra-wideband impulse receiver that eliminates unwanted DC offset and / or DC voltage fluctuation in a baseband analog circuit of an ultra-wideband impulse receiver that receives an impulse signal of a high frequency, Thereby providing an ultra wideband impulse receiver including the same.
Also, according to the present invention, there is provided a DC compensator of an ultra-wideband impulse receiver capable of solving the problem of undesired DC voltage generation and / or deterioration of reception sensitivity due to shaking phenomenon caused by using a DC blocking capacitor in an ultra-wideband impulse receiver, To provide an ultra wideband impulse receiver.
Also, according to the present invention, it is possible to provide an ultra-wideband impulse receiver capable of eliminating a shaking phenomenon of a DC voltage without using a DCOC circuit and thereby optimizing sensitivity by eliminating a shaking noise voltage signal other than an envelope signal.
1 is a structural diagram of an ultra-wideband impulse receiver according to an embodiment.
2 is a voltage signal graph illustrating the problem caused by a DC blocking capacitor in an ultra-wideband impulse receiver.
3 is a structural diagram of an ultra wideband impulse receiver including a DC compensator according to an embodiment.
FIG. 4 is a circuit diagram of a switch disposed at an input terminal of an analog circuit of an ultra-wideband impulse receiver according to an embodiment.
5 is a structural diagram of a control signal generator included in an ultra-wideband impulse receiver according to an embodiment.
6 illustrates a signal output from each circuit of the UWB impulse receiver according to the embodiment.
The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive.
1 is a structural diagram of an ultra-wideband impulse receiver according to an embodiment. More specifically, FIG. 1 is an overall configuration diagram of an analog baseband circuit portion of an ultra-wideband impulse receiver according to an embodiment. 1, an envelope signal obtained by removing a high frequency carrier from an envelope detector (not shown) through an envelope detector is input to the analog baseband circuit portion of the UWB impulse receiver shown in FIG. 1 .
1, an
The
At this time, the
The
In an embodiment, the analog circuitry that receives the first signal and the second signal, which are differential signals, through the first and second stages, may include at least one of a
Unless a DC offset eliminating circuit (DCOC) which removes the DC offset and the shaking of the DC voltage is used in the operation of the
In order to solve this problem without using the DC offset elimination circuit (DCOC), the common mode voltage between each circuit can be separated by using a DC blocking capacitor.
For example, assuming that a DC blocking capacitor is disposed between the
2 is a voltage signal graph illustrating the problem caused by a DC blocking capacitor in an
In order to solve the problems that may occur by using such a DC blocking capacitor, the embodiment may further include a
3 is a structural diagram of an ultra wideband impulse receiver including a DC compensator according to an embodiment. 3, an
4 is a switch circuit diagram 180 disposed at the input of the analog circuitry of the
In Fig. 4, only a
At this time, the
The
At this time, the
5 is a structural diagram of a control signal generator included in the
The
At this time, the required delay time can be determined in consideration of signal delay and the like in the circuit so as not to affect the primary envelope pulse D. For example, the
6 illustrates a signal output from each circuit of the UWB impulse receiver according to the embodiment. 6 (a) illustrates a differential signal that is input to an
The
6 (f), the control signal c is delayed from the output signal P0 of the
In this specification, the DC compensator of
The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
100: Ultra-wideband impulse receiver
110: Variable gain amplifier
130: integrator
140: D2S amplifier
150: comparator
150 ': control signal generator
171, 172: DC blocking capacitors
181: Switch
190: delay section
Claims (12)
A switch connected between said first end and said second end;
A DC blocking capacitor coupled to the first and second ends, respectively; And
And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal,
Wherein the switch is turned on and off according to the control signal and the first stage and the second stage are shorted to each other when the switch is turned on,
A DC compensator of an ultra wideband impulse receiver.
Wherein the circuitry comprises at least one of a variable gain amplifier, an integrator, and a D2S amplifier.
Wherein the voltage of the circuit portion is set to 1/2 of the power supply voltage (VDD).
Wherein the first signal and the second signal are envelope signals of an impulse with the carrier signal removed.
Wherein the switch is turned on after a predetermined time delay from a time when a pulse corresponding to the envelope is generated in the output signal.
A comparator that receives a signal of the analog circuit unit and outputs a data signal as an output signal;
A switch connected between said first end and said second end;
A DC blocking capacitor coupled to the first and second ends, respectively; And
And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal,
Wherein the switch is turned on and off according to the control signal and the first stage and the second stage are shorted to each other when the switch is turned on,
Ultra wideband impulse receiver.
Wherein the circuitry comprises at least one of a variable gain amplifier, an integrator, and a D2S amplifier.
And the voltage of the circuit portion is set to 1/2 of the power supply voltage (VDD).
Wherein the first signal and the second signal are envelope signals of an impulse with the carrier signal removed.
Wherein the switch is turned on after a predetermined time delay from a time when a pulse corresponding to the envelope is generated in the output signal.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150008929A KR101658076B1 (en) | 2015-01-19 | 2015-01-19 | DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same |
PCT/KR2015/001153 WO2016117747A1 (en) | 2015-01-19 | 2015-02-04 | Dc corrector for ultra-wideband impulse receiver, and ultra-wideband impulse receiver including same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020150008929A KR101658076B1 (en) | 2015-01-19 | 2015-01-19 | DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same |
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KR20160089233A KR20160089233A (en) | 2016-07-27 |
KR101658076B1 true KR101658076B1 (en) | 2016-09-30 |
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KR1020150008929A KR101658076B1 (en) | 2015-01-19 | 2015-01-19 | DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same |
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KR (1) | KR101658076B1 (en) |
WO (1) | WO2016117747A1 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003060540A (en) | 2001-08-10 | 2003-02-28 | Pioneer Electronic Corp | Receiver |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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KR910002355B1 (en) * | 1988-03-24 | 1991-04-20 | 삼성전자 주식회사 | Serial data transmitting and receiving circuit between the main system and the keyphone |
NO329890B1 (en) * | 1999-11-15 | 2011-01-17 | Hitachi Ltd | The mobile communication apparatus |
WO2005074150A1 (en) | 2004-01-02 | 2005-08-11 | International Business Machines Corporation | Robust non-coherent receiver for pam-ppm signals |
JP4332095B2 (en) * | 2004-10-01 | 2009-09-16 | パナソニック株式会社 | DC offset calibration system |
JP5376581B2 (en) * | 2009-03-06 | 2013-12-25 | 独立行政法人情報通信研究機構 | IR-UWB transceiver |
KR101058703B1 (en) * | 2009-08-31 | 2011-08-22 | 삼성전기주식회사 | Time Division Frequency Correction and DC Offset Rejection Circuit for Continuous-Time Analog Filters |
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2015
- 2015-01-19 KR KR1020150008929A patent/KR101658076B1/en active IP Right Grant
- 2015-02-04 WO PCT/KR2015/001153 patent/WO2016117747A1/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003060540A (en) | 2001-08-10 | 2003-02-28 | Pioneer Electronic Corp | Receiver |
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KR20160089233A (en) | 2016-07-27 |
WO2016117747A1 (en) | 2016-07-28 |
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