KR101653999B1 - Storage system based on nand flash and data retention improving method - Google Patents

Storage system based on nand flash and data retention improving method Download PDF

Info

Publication number
KR101653999B1
KR101653999B1 KR1020150046818A KR20150046818A KR101653999B1 KR 101653999 B1 KR101653999 B1 KR 101653999B1 KR 1020150046818 A KR1020150046818 A KR 1020150046818A KR 20150046818 A KR20150046818 A KR 20150046818A KR 101653999 B1 KR101653999 B1 KR 101653999B1
Authority
KR
South Korea
Prior art keywords
nand flash
period
flash memory
parity information
garbage collection
Prior art date
Application number
KR1020150046818A
Other languages
Korean (ko)
Inventor
이동희
박희진
김재호
Original Assignee
서울시립대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 서울시립대학교 산학협력단 filed Critical 서울시립대학교 산학협력단
Priority to KR1020150046818A priority Critical patent/KR101653999B1/en
Application granted granted Critical
Publication of KR101653999B1 publication Critical patent/KR101653999B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The present invention provides a flash memory device comprising: at least one NAND flash memory including a plurality of blocks for recording data; And a controller for managing data by executing data retention enhancement firmware. At this time, the controller writes parity information for error correction to an arbitrary page of a predetermined block among a plurality of blocks by execution of the firmware, and writes the parity information to a plurality of blocks by using the error correction code and parity information at a predetermined timing Scrubbing is performed on the recorded data.

Description

{STORAGE SYSTEM BASED ON NAND FLASH AND DATA RETENTION IMPROVING METHOD}

The present invention relates to a NAND flash-based storage system and a method for enhancing data retention.

NAND flash-based storage is used as computer systems and mobile device storage devices because of its high speed and low power consumption. NAND flash-based storage can be classified into a single level cell (SLC), a multi level cell (MLC), and a triple level cell (TLC) according to a method of storing data in a cell, which is a minimum unit for storing data .

The SLC stores one bit in one cell included in the NAND flash memory. The MLC stores two bits of information in one cell, and the TLC stores three bits of information in one cell. Compared to SLC, MLC and TLC are cheaper because of higher storage density. When the MLC and the TLC are the same size, the time required for the read, write, and erase operations is smaller than that of the SLC.

However, according to the characteristics of NAND flash-based storage having a limited number of program erase cycles, the number of P / E times of MLC and TLC is smaller than that of SLC, so that the life of NAND flash-based storage can be shortened . Also, as MLC and TLC are used for a long time, the bit error rate is increased and the stability is lowered.

In particular, in the case of NAND flash-based storage, the bit error rate increases as the number of P / E increases or the data retention period increases. In addition, since random read errors often occur in NAND flash-based storage, error correction codes (ECC) are required to maintain data integrity.

In this regard, Korean Patent Registration No. 10-2009-7009421 entitled " Flash Memory Device, System and Method for Rendering for Error Suppression " describes a non-volatile memory and a non- A controller and circuitry for original landing to be stored in memory, storing original data in memory, responding to a request for original data, retrieving and deranding original data, and exporting the requesting entity. Lt; / RTI >

In addition, Korean Patent Registration No. 10-2010-0075352 (entitled "Nonvolatile Memory Device and Its Operation Method") discloses a nonvolatile memory device and its operation method in which the number of error bits generated per unit group in a memory cell block during a read operation If the number of bits is equal to or less than the maximum number of bits that can be compensated, but the number of bits is greater than the number of bits set, the memory cell block is not used after copying back the data stored in the memory cell block to another memory cell block Discloses a technique for performing an invalidity block in which the invalidity block is set.

An object of the present invention is to provide a NAND flash-based storage system and a method of enhancing data retention that can reduce errors that may occur as the data retention period increases, thereby preserving data and extending the life span .

It should be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to a first aspect of the present invention, there is provided a storage system based on NAND flash, comprising: at least one NAND flash memory including a plurality of blocks for recording data; And a controller for managing data by executing data retention enhancement firmware. At this time, the controller writes parity information for error correction to an arbitrary page of a predetermined block among a plurality of blocks by execution of the firmware, and writes the parity information to a plurality of blocks by using the error correction code and parity information at a predetermined timing Scrubbing is performed on the recorded data.

According to a second aspect of the present invention, there is provided a method for enhancing data retention in a NAND flash-based storage system, the method comprising: storing parity information for error correction in an arbitrary page of a predetermined block among a plurality of blocks for recording data in a NAND flash memory Recording; And performing scrubbing on the data recorded in the plurality of blocks using the parity information at a predetermined timing.

The NAND flash memory according to the third aspect of the present invention includes a specific block in which parity information for error correction is recorded in an arbitrary page of a plurality of blocks for recording data. At this time, the data recorded in the plurality of blocks is scrubbed using the error correction code and the parity information at a predetermined timing.

According to any one of the above-mentioned problems, an embodiment of the present invention performs scrubbing on data in which a plurality of blocks are recorded using an error correction code and parity information at a predetermined timing, The error rate can be reduced, and the life of the NAND flash memory can be extended.

One embodiment of the present invention can perform garbage collection and scrubbing by comparing the garbage collection period and the safing period, thereby reducing the number of read, write, and erase operations that can affect the performance and lifetime of the NAND flash memory have. In addition, since an embodiment of the present invention uses an error correction code and parity information to perform scrubbing, an error of a large amount of data can be corrected as compared with the case of using only an error correction code.

1 is an exemplary diagram illustrating a change in the uncalibrable page error rate over time in a NAND flash-based storage system.
2 is a configuration diagram of a NAND flash-based storage system according to an embodiment of the present invention.
3 is a diagram illustrating parity information recording in a NAND flash-based storage system according to an embodiment of the present invention.
4 is a diagram illustrating parity information recording in a NAND flash-based storage system according to an embodiment of the present invention.
5 is a view for explaining scrubbing according to an embodiment of the present invention.
Figure 6 is an illustration of scrubbing and performing garbage collection according to one embodiment of the present invention.
7 is a flowchart illustrating a method for enhancing data retention in a NAND flash-based storage system according to an embodiment of the present invention.
8 is a flowchart illustrating a method of performing scrubbing and garbage collection of a storage system based on NAND flash according to an embodiment of the present invention.
9 is a block diagram of a NAND flash memory according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly explain the present invention in the drawings, parts not related to the description are omitted.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when a part is referred to as "including " an element, it does not exclude other elements unless specifically stated otherwise.

The following describes an uncorrectable error in the NAND flash-based storage system with reference to FIG.

1 is an exemplary diagram illustrating a change in uncorrectable page error rate over time in a NAND flash based storage system.

NAND flash-based storage systems can increase the uncorrectable page error rate as the number of P / E increases. In addition, the NAND flash-based storage system can increase the non-calibrable page error rate as the number of days to retain the data becomes longer. This phenomenon can be more serious in MLC or TLC storing a lot of data in a single cell than in SLC.

In particular, a NAND flash-based storage system can not perform overwriting due to the inherent characteristics of the NAND flash memory. Therefore, a NAND flash-based storage system writes data to an unused page of a NAND flash memory when performing a write operation. In addition, when the data already recorded in the NAND flash memory is updated, the NAND flash-based storage system invalidates the page on which the original data was recorded and writes the updated data in a free page at another position. At this time, a page in which new data is recorded is called a valid page, and a page invalidated after data is previously recorded is referred to as an invalid page.

NAND flash-based storage systems can run out of space to store data as the number of invalid pages increases. Thus, a NAND flash-based storage system performs garbage collection to erase invalid pages.

At this time, the NAND flash-based storage system can correct an error of a hot block frequently updated through garbage collection. However, in the case of a cold block where the update does not occur frequently and the data retention period is relatively long, the error may not be corrected because the garbage collection is not performed. Therefore, NAND flash-based storage systems require data recovery in such a way that data can be held for long data retention periods for cold blocks and the like.

Conventional NAND flash based storage systems periodically scrub to solve this problem. At this time, scrubbing is one of the techniques based on error correction codes to correct errors detected through periodic memory inspection. The execution of the scrubbing is relatively simple. However, frequent scrubbing has the disadvantage of degrading the performance of the NAND flash-based storage system and shortening its lifespan.

Also, referring to FIG. 1, in the conventional NAND flash-based storage system, as the number of times of P / E increases, even if the garbage collection and scrubbing techniques are performed, irrecoverable page errors of data may increase over time . In particular, conventional NAND flash based storage systems may not be able to guarantee the stability of the NAND flash memory and system when exceeding 10xE -15 , which is known as the threshold of non-calibrable page error. Therefore, there is a need for an apparatus and method for enhancing data retention of a NAND flash-based storage system.

Next, a NAND flash-based storage system 200 according to an embodiment of the present invention will be described with reference to FIGS. 2 to 8. FIG.

2 is a configuration diagram of a storage system 200 based on a NAND flash according to an embodiment of the present invention.

The NAND flash based storage system 200 according to an exemplary embodiment of the present invention includes at least one NAND flash memory 210, a memory 220, and a controller 230.

At this time, the NAND flash memory 210 includes a plurality of blocks for recording data. In the NAND flash memory 210, a block includes a plurality of pages, which are basic units in which data is stored. The NAND flash memory 210 performs reading and writing operations on a page-by-page basis, and performs erase operations on a block-by-block basis.

The memory 220 stores data retention enhancement firmware. Here, the memory 220 is collectively referred to as a non-volatile storage device that keeps stored information even when no power is supplied, and a volatile storage device that requires electricity to maintain stored information. In addition, the memory 220 may be included in the NAND flash-based storage system 200 as a separate device, and may be integrated with the controller 230.

The controller 230 provides a common file system interface so that the NAND flash-based storage system 200 can be used as a disk drive such as a hard disk drive. At this time, the controller 230 can control the NAND flash memory 210 as a system on chip (SoC) independently of the computer device.

Alternatively, the controller 230 may control the NAND flash memory 210 through a flash translation layer (FTL). At this time, in order to use the NAND flash memory 210 in which the file system of the existing OS does not have a physical sector unlike the hard disk drive, the flash conversion layer converts the physical blocks and pages into a logical sector structure .

The controller 230 executes data retention enhancement firmware stored in the memory 220 to manage data to be written to the NAND flash memory 210. [ To this end, the controller 230 records parity information for error correction in a predetermined page of a predetermined block among a plurality of blocks of the NAND flash memory 210. [ The controller 230 performs scrubbing on the data recorded in the plurality of blocks based on the parity information and the error correction code recorded at a predetermined timing.

At this time, the specific block in which the parity information is stored may be a cold block. A block can be divided into a hot block and a cold block. At this time, since the data of the hot block is frequently updated, the storage period of the stored data is shorter than that of the cold block. Also, hot blocks are likely to perform garbage collection on invalid pages, which can be caused by frequent updates, so that garbage collection can correct errors without additional parity information. Therefore, the controller 230 can record parity information in a cold block having a relatively long storage period of stored data and a low possibility of performing garbage collection.

The controller 230 can perform scrubbing on the data recorded in the plurality of blocks based on the parity information and the error correction code recorded at a predetermined timing. This will be described with reference to FIG. 3 and FIG.

FIG. 3 and FIG. 4 are diagrams for illustrating parity information recording in the NAND flash-based storage system 200 according to an embodiment of the present invention.

Referring to FIG. 3, the NAND flash-based storage system 200 includes four NAND flash memories 310 to 340. In addition, the NAND flash-based storage system 200 can exchange data with a host, such as a computing device, through a host interface 300.

At this time, the host interface 300 may include an integrated driver electronics (IDE), a peripheral component interconnect bus (PCI), a parallel ATA (PATA), a serial ATA (SATA) universal serial bux). < / RTI > In addition, the host interface 300 may be a network module of a computer device connected to the NAND flash-based storage system 200 via a network.

The NAND flash memories 310 to 340 may include one or more blocks. A block may also include one or more pages. For example, referring to FIG. 3, the first NAND flash memory 310 may include one or more blocks, and a physical block number (PBN) may be assigned to each block. Further, each block includes one or more pages, and each page may be assigned a physical block number (PPN) which is a physical page number.

The controller 230 included in the NAND flash-based storage system 310 classifies the blocks included in each NAND flash memory 210 into hot blocks or cold blocks according to a predefined hot / cold block classification criterion . At this time, the classification criterion for the predefined hot / cold block may be a default value preset to the NAND flash-based storage system 200 and may be a value preset by the user of the NAND flash- have. The predefined hot / cold block classification criteria can be defined by the host.

For example, the controller 230 may classify a block including three or more valid pages into a hot block, and classify a block that does not include at least three valid pages as a cold block, according to a classification criterion for a predefined hot / cold block .

3, the 'PBN 0 block' (P300) of the first NAND flash memory 310 does not include the invalid page, and the 'PBN 0 block' (P310) of the second NAND flash memory 320 includes one Of invalid pages. Therefore, the controller 230 sets the 'PBN 0 blocks' (P300 and P310) of the first NAND flash memory 310 and the second NAND flash memory 320 as a cold block, respectively, according to a predetermined hot / Can be classified.

In addition, 'PBN 0 block' (P 320) of the third NAND flash memory 330 and 'PBN 0 block' (P 330) of the fourth NAND flash memory 340 each include three invalid pages. Therefore, the controller 230 sets the 'PBN 0 blocks' (P 320 and P 330) of the third NAND flash memory 330 and the fourth NAND flash memory 340 as hot blocks, respectively, according to a predetermined hot / Can be classified.

4, the controller 230 controls the 'PBN 0 block' P401 of the first NAND flash memory 310 and the 'PBN 0 block' P411 of the second NAND flash memory 320 classified as the cold block (P400, P410) among the plurality of pages included in the block, respectively, to record the parity information. Thereafter, the controller 230 may perform scrubbing and use the parity information recorded in the 'PPN 0 pages' (P400 and P410) (P400 and P410) to correct the error.

At this time, the controller 230 may record parity based on vertical striping. Therefore, the parity information may be recorded in one or more pages located at the end of the plurality of pages of the block for which parity information is to be recorded.

In the case of the PBN 0 block P320 of the third NAND flash memory 330 classified as the hot block and the PBN 0 block P330 of the fourth NAND flash memory 340 classified by the controller 230, It may not be recorded. Therefore, the controller 230 can write data to the unused block.

The controller 230 writes the parity information in the NAND flash memory 210 and then writes the data in the plurality of blocks of the NAND flash memory 210 using the parity information and the error correction code recorded at the predetermined timing The scrubbing is performed.

At this time, as described above, scrubbing can be a solution to an error that occurs as the data retention period of the NAND flash-based storage system 200 becomes longer. However, the disadvantage is that scrubbing can shorten the life of the NAND flash-based storage system 200 due to an increase in the amount of reading and writing.

Therefore, the controller 230 according to an embodiment of the present invention performs garbage collection without performing scrubbing if the possibility of performing garbage collection is higher than scrubbing before performing scrubbing. If garbage collection is less likely to be performed than scrubbing, the controller 230 performs scrubbing.

For this, the controller 230 may calculate the garbage collection period and the safing period for the NAND flash memory 210 before recording the parity information, and may perform scrubbing or garbage collection according to the calculated garbage collection period and the safing period have.

Specifically, the controller 230 first calculates the garbage collection period and the safing period before writing the parity information in the NAND flash memory 210. [ At this time, the safe period is calculated on the basis of the time when the data preservation error can be accepted without performing the scrubbing. Therefore, the controller 230 models the relationship between the use time of the NAND flash memory 210 and the error rate that changes as the NAND flash memory 210 is used, thereby calculating the safe period.

The garbage collection period is calculated based on the remaining time until the garbage collection for the NAND flash memory 210 is performed. Therefore, the controller 230 can be calculated based on the number of blocks in use in the NAND flash memory 210 and the number of blocks updated every day.

As a result of the comparison of the safing period and the garbage collection period, if the safing period is shorter than the garbage collection period, the controller 230 calculates the safing period at a predetermined timing. Conversely, if the safe period is longer than or equal to the garbage collection period, the controller 230 calculates the garbage collection period at a predetermined timing.

The controller 230 performs scrubbing or garbage collection according to the calculated predetermined timing.

As a result of the comparison of the garbage collection period and the safing period, if the safing period is short, the controller 230 can perform scrubbing in the safing period. At this time, the controller 230 can extend the safing period by recording the parity information without scrubbing it directly in order to improve the performance and life of the NAND flash-based storage system 200. That is, when the safing period is reached, the controller 230 may perform the scrubbing by deleting the parity information on an arbitrary page without performing the scrubbing. Further, after recording the parity, the controller 230 may recalculate the safing period based on the parity information and the error correction code, and compare the safing period with the garbage collection period again.

If the recalculated safe period is short, the controller 230 may perform scrubbing based on the error correction code and the written parity information in the recalculated safe period have.

In addition, when the garbage collection period is short compared with the safing period or the re-calculated safing period, the controller 230 may perform garbage collection on the data recorded in the plurality of blocks included in the NAND flash memory 210 . At this time, the garbage collection is to erase the data recorded in the invalid page or the invalid block included in the NAND flash memory 210, as described above. The scrubbing and the safety cycle will be described in detail with reference to FIG.

5 is a view for explaining scrubbing according to an embodiment of the present invention.

The safing period according to an embodiment of the present invention can be calculated by modeling the time required until the non-calibratable page error rate ( UPER ) approaches a predetermined threshold value. At this time, the predetermined threshold value may be 10xE- 15 , which is known as the American standard for the hard disk drive.

The controller 230 can calculate the safing period using a predetermined threshold value. For example, the safing period may be calculated as a ratio of the allowed uncorrectable page error rate threshold value to the number of P / E times of the NAND flash based storage system 200.

After reaching the safing period, the controller 230 may record the parity information for the blocks included in the NAND flash memory 210, and recalculate the safing period in which the scrubbing is performed. In this manner, the controller 230 uses the parity information to reduce the data retention error of the NAND flash-based storage system 200, records the parity information on the block to be scrubbed, , It is possible to extend the safing period.

At this time, the parity information can be recorded in an arbitrary page of the block subjected to scrubbing. For example, the parity information may be written to one or more pages located at the end of a plurality of pages of a block for which parity information is to be recorded.

In addition, the controller 230 may use the error correction code and the parity information to recalculate the safing period after performing the parity information recording. The recalculated safe period can be calculated by modeling the relationship between the use time of the NAND flash memory 210 and the uncorrectable page error rate after the parity information is recorded. For example, the changing error rate after the page is modified by scrubbing may be calculated from the uncorrectable page error rate < RTI ID = 0.0 >

Figure 112015032433274-pat00001
).

When the safing period is recalculated, the controller 230 may compare the re-calculated safing period and the garbage collection period to calculate a predetermined timing again. Then, scrubbing or garbage collection can be performed according to the calculated predetermined timing.

At this time, the size of the scrubbed data (

Figure 112015032433274-pat00002
) Can be derived based on the amount of write requests occurring in one day and the probability that data will not be updated during the safing period. The size of the scrubbed data is shown in Equation (1).

Figure 112015032433274-pat00003

At this time, D write is the amount of write request in one day. And s t is the probability that the data will not be updated during the safekeeping period t .

The scrubbing performance according to the comparison between the recalculated safe period and the garbage collection period will be described with reference to FIG.

Figure 6 is an illustration of scrubbing and performing garbage collection according to one embodiment of the present invention.

If the garbage collection period is shorter than the recalculated safe period as shown in FIG. 6A, the controller 230 can perform garbage collection when the garbage collection period is reached.

However, if the recalculated safe period is shorter than the garbage collection period as shown in (b) of FIG. 6, the predetermined timing may be a recalculated safing period. Then, the controller 230 can perform scrubbing when the recalculated safe period is reached.

6 (a), when the block P600 included in the unused block pool performs the scrubbing of FIG. 6 (b), the block P610 included in the unused block pool, Lt; / RTI > Therefore, when scrubbing is performed, unused blocks may be increased. A space including such an unused block may be referred to as an over provisioning (OP) space.

At this time, the over-provisioning space is a preliminary space prepared in advance so that the NAND flash-based storage system 200 can operate smoothly. When a large amount of overprovisioning space is occupied in the NAND flash-based storage system 200, the NAND flash-based storage system 200 can smoothly perform garbage collection or scrubbing, but space can be wasted. Therefore, the controller 230 should set an optimal over-provisioning space.

The controller 230 may calculate an over provisioning (OP) space size at the time of performing scrubbing when performing scrubbing, in order to set an optimal over-provisioning space. And the controller 230 may set a first overprovisioning space for the hot blocks classified based on the calculated size and a second over-provisioning space for the classified cold blocks. At this time, the first over-provisioning space can be calculated based on the number of blocks in use. Further, the second over-provisioning space can be calculated based on the number of blocks used for scrubbing.

At this time, the ratio of the overprovisioning space ( a effective ) for setting the optimal overprovisioning space is expressed by Equation (2).

Figure 112015032433274-pat00004

In Equation (2), u scrub is the amount of data block selected to perform scrubbing.

Meanwhile, the NAND flash-based storage system 200 according to an embodiment of the present invention can provide a grace period until scrubbing, thereby lowering a write amplification factor (WAF). At this time, the write amplification factor determines the performance and lifetime of the NAND flash-based storage system 200. The smaller the write amplification factor, the better the performance and lifetime.

The recording amplification factor WAF according to the scrubbing and the garbage collection performance in the NAND flash-based storage system 200 is calculated according to the scrubbing and the garbage collection performance for the hot / cold block, respectively, and is expressed by Equations (3) to (6).

Equation (3) represents a write amplification coefficient for a case where garbage collection is performed on the hot block and the cold block. At this time, the write amplification coefficient for the garbage collection of the hot block is WAF hotGC and the write amplification coefficient for the garbage collection of the cold block is WAF coldGC .

Figure 112015032433274-pat00005

Equation (4) represents a write amplification coefficient for performing a garbage collection on a hot block and scrubbing on a cold block. Equation (5) represents the write amplification coefficient for the case where the cold block is subjected to the garbage collection and the hot block is scrubbed. In these two cases, the recording amplification factor can be proportional to the size of the optimal overprovisioning space.

For example, when the hot-block is subjected to the garbage collection and the cold block is scrubbed, if the over-provisioning space of the cold block is larger than the optimal over-provisioning space, the NAND flash- Can improve the performance by tuning the overprovisioning space of the hot block. Therefore, the recording amplification factor in this case is expressed by Equation (4), and the opposite case is expressed by Equation (5).

Figure 112015032433274-pat00006

Figure 112015032433274-pat00007

At this time,

Figure 112015032433274-pat00008
And
Figure 112015032433274-pat00009
Means a recording amplification coefficient for a case where an optimal over-provisioning space is tuned for each of the hot block and the cold block. In addition, WAF hot _scrub and WAF cold _scrub are recording amplification coefficients for scrubbing the hot block and the cold block, respectively.

Finally, Equation (6) is a write amplification coefficient for a case where scrubbing is performed on both the hot block and the cold block. At this time, the over-provisioning space of the hot block and the cold block can be utilized for data copy for scrubbing. Hence, the recording amplification factor in Equation (6) may not consider over provisioning space.

Figure 112015032433274-pat00010

Next, referring to FIGS. 7 and 8, a method of enhancing data retention of the NAND flash-based storage system 200 according to an embodiment of the present invention will be described.

FIG. 7 is a flowchart of a method for enhancing data retention of a NAND flash-based storage system 200 according to an embodiment of the present invention. 8 is a flowchart of a method of performing scrubbing and garbage collection of the NAND flash-based storage system 200 according to an embodiment of the present invention.

The NAND flash-based storage system 200 is configured to store parity for error correction in an arbitrary page of a predetermined block among a plurality of blocks for recording data in the NAND flash memory 210 included in the NAND- Information is recorded (S700). The NAND flash-based storage system 200 performs scrubbing on the data recorded in the plurality of blocks using the error correction code and the parity information at a predetermined timing (S710).

At this time, the specific block storing the parity information may be a cold block that is less likely to perform garbage collection because the update is not frequent compared to the hot block.

To this end, the NAND flash-based storage system 200 may classify a plurality of blocks into a hot block and a cold block according to a predefined hot / cold block classification criterion. At this time, the predefined hot / cold block classification criteria can be set by a computing device that exchanges data with the NAND flash-based storage system 200 or the NAND flash-based storage system 200.

The predetermined timing for performing the scrubbing can be calculated based on the remaining safing period until the NAND flash based storage system 200 performs scrubbing and the remaining garbage collection period until the garbage collection is performed.

At this time, the safing period can be calculated by modeling the relationship between the use time of the NAND flash memory 210 and the error rate that is changed according to the use of the NAND flash memory 210 in the storage system 200 based on the NAND flash. The garbage collection period is calculated based on the remaining time until garbage collection for the NAND flash memory 210 is performed.

The scrubbing and garbage collection will be described in detail. First, the NAND flash-based storage system 200 can calculate a safing period and a garbage collection period (S800).

The NAND flash-based storage system 200 can compare the safing period and the garbage collection period (S810 and S820). As a result of comparison between the two cycles, if the safing period is shorter than the garbage collection period, the NAND flash-based storage system 200 can record the parity information on an arbitrary page without performing scrubbing when the safing period is reached (S830 ).

After recording the parity information, the NAND flash-based storage system 200 can recalculate the safing period (S840). At this time, the re-computed safe period can be calculated using the error correction code and the parity information.

When the safing period is recalculated, the NAND flash-based storage system 200 may compare the garbage collection period and the recalculated safing period again (S850).

If the recalculated safe period is shorter than the garbage collection period, the storage system 200 of the NAND flash-based system may calculate the re-calculated safing period at a predetermined timing . The NAND flash-based storage system 200 may perform scrubbing based on the error correction code and the parity information at a predetermined timing (S860).

If the safing period and the re-calculated safing period are longer than or equal to the garbage collection period, the NAND flash-based storage system 200 can perform garbage collection in the garbage collection period (S870).

Next, a NAND flash memory 210 according to an embodiment of the present invention will be described with reference to FIG.

9 is a block diagram of a NAND flash memory 210 according to an embodiment of the present invention.

The NAND flash memory 210 according to an embodiment of the present invention includes one or more blocks 910. [ In addition, one or more blocks 910 each include one or more pages 911.

The NAND flash memory 210 includes a specific block in which parity information for error correction is recorded in an arbitrary page of a plurality of blocks 910 for recording data. At this time, the specific block may be a cold block that is less likely to perform garbage collection because the update is not frequent compared to the hot block.

The hot block has a shorter data storage period than the cold block. And hot blocks are likely to perform garbage collection by frequent updates. Therefore, hot blocks can correct errors without garbage collection and without additional parity information. That is, the NAND flash memory 210 classifies a plurality of blocks 910 included in the NAND flash memory 210 into hot blocks and cold blocks, Information can be recorded.

The NAND flash memory 210 can scrub data recorded in the plurality of blocks 910 at a predetermined timing based on the error correction code and the parity information. At this time, the NAND flash memory 210 calculates a predetermined timing through comparison of a garbage collection period and a safe period that can be calculated for a plurality of blocks 910 included in the NAND flash memory 210. [

If the safing period is longer than the garbage collection period, the predetermined timing may be a garbage collection period. At this time, the NAND flash memory 210 may perform garbage collection in the garbage collection period.

If the safing period is shorter than the garbage collection period, the NAND flash memory 210 may first write the parity information in the safing period to extend the safing period. Then, the NAND flash memory 210 records the parity information, and then reassigns the safing period based on the error correction code and the parity information.

The NAND flash memory 210 may re-calculate the re-calculated safing period and the garbage collection period to reserve a predetermined timing. The NAND flash memory 210 may perform scrubbing or garbage collection according to the re-calculated predetermined timing. At this time, when performing scrubbing, the NAND flash memory 210 may perform scrubbing based on the error correction code and the parity information. The NAND flash-based storage system 200 and the data retention enhancement method according to an embodiment of the present invention perform scrubbing on data in which a plurality of blocks are recorded using an error correction code and parity information at a predetermined timing, It is possible to reduce the data retention error rate that can not be corrected and to extend the life of the NAND flash memory.

The NAND flash-based storage system 200 and the data retention enhancement method can compare the garbage collection period and the safing period to perform garbage collection and scrubbing. Therefore, it is possible to perform a read operation that may affect the performance and the life of the NAND flash memory And write operations. In addition, since the NAND flash-based storage system 200 and the data retention enhancement method use error correction codes and parity information to perform scrubbing, errors of a large amount of data can be corrected have.

One embodiment of the present invention may also be embodied in the form of a recording medium including instructions executable by a computer, such as program modules, being executed by a computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, the computer-readable medium can include both computer storage media and communication media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Communication media typically includes any information delivery media, including computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave, or other transport mechanism.

While the methods and systems of the present invention have been described in connection with specific embodiments, some or all of those elements or operations may be implemented using a computer system having a general purpose hardware architecture.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

200: NAND flash-based storage system
210: NAND flash memory
220: Memory
230: controller

Claims (12)

In a NAND flash-based storage system,
At least one NAND flash memory including a plurality of blocks for recording data; And
And a controller for managing the data by executing data retention enhancement firmware,
The controller writes parity information for error correction to an arbitrary page of a predetermined block among the plurality of blocks by executing the firmware,
Scrubbing is performed on data recorded in the plurality of blocks using an error correction code and the parity information at a predetermined timing,
Wherein the controller compares the calculated safe period with a garbage collection period of the NAND flash memory by modeling a relationship between a use time of the NAND flash memory and an error rate that varies depending on use of the NAND flash memory,
Wherein if the safing period is shorter than the garbage collection period, the arbitrary page is determined in the safing period, and the parity information is recorded in the determined page. The method according to claim 1,
Wherein the controller classifies the plurality of blocks into a hot block and a cold block and records the parity information in an arbitrary page of the classified cold block among the plurality of blocks. 3. The method of claim 2,
The controller calculates an over-provisioning (OP) space size at the time of performing the scrubbing, and calculates a first over-provisioning space for the classified hot block based on the calculated size and a second over- And setting an over provisioning space. The method according to claim 1,
Wherein the controller writes the parity information to one or more pages located at the end of a plurality of pages of the specific block. delete The method according to claim 1,
Wherein the controller performs garbage collection on data recorded in the plurality of blocks in the garbage collection period when the garbage collection period is shorter than or equal to the safe period. The method according to claim 1,
Wherein the controller recalculates the safing period after recording the parity information and compares the safing period with the garbage collection period to calculate the predetermined timing,
Wherein the recalculated safe period is calculated by modeling a relationship between a usage time of the NAND flash memory and an error rate that varies depending on the recorded parity. In a method for enhancing data retention of a NAND flash-based storage system,
Recording parity information for error correction in an arbitrary page of a predetermined block among a plurality of blocks for recording data in a NAND flash memory; And
And performing scrubbing on data recorded in the plurality of blocks using the parity information at a predetermined timing,
Wherein the recording of the parity information comprises:
Calculating a safe period by modeling a relationship between a use time of the NAND flash memory and an error rate changed by using the NAND flash memory;
Comparing the calculated safe period and a garbage collection cycle for the NAND flash memory; And
Determining the arbitrary page in the safing period if the safing period is shorter than the garbage collection period, and recording the parity information on the determined page. 9. The method of claim 8,
The step of recording the parity information
And dividing the plurality of blocks into a hot block and a cold block and recording the parity information on an arbitrary page of the classified cold block. delete 9. The method of claim 8,
Further comprising the step of re-calculating the safing period after the recording of the parity information, and calculating the predetermined timing by comparing with the garbage collection period,
Wherein the recalculated safe period is calculated by modeling a relationship between a use time of the NAND flash memory and an error rate varying according to the recorded parity. In a NAND flash memory,
And a specific block in which parity information for error correction is recorded in an arbitrary page of a plurality of blocks for recording data,
Wherein data recorded in the plurality of blocks is scrubbed using an error correction code and the parity information at a predetermined timing,
Wherein the arbitrary page compares a safing period and a garbage collection period for the NAND flash memory, and if the safing period is shorter than the garbage collection period, the parity information is recorded after the safing period is determined during the safing period,
Wherein the safing period is calculated by modeling a relationship between a use time of the NAND flash memory and an error rate that varies depending on use of the NAND flash memory.
KR1020150046818A 2015-04-02 2015-04-02 Storage system based on nand flash and data retention improving method KR101653999B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150046818A KR101653999B1 (en) 2015-04-02 2015-04-02 Storage system based on nand flash and data retention improving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150046818A KR101653999B1 (en) 2015-04-02 2015-04-02 Storage system based on nand flash and data retention improving method

Publications (1)

Publication Number Publication Date
KR101653999B1 true KR101653999B1 (en) 2016-09-09

Family

ID=56939255

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150046818A KR101653999B1 (en) 2015-04-02 2015-04-02 Storage system based on nand flash and data retention improving method

Country Status (1)

Country Link
KR (1) KR101653999B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11194687B2 (en) 2019-01-02 2021-12-07 SK Hynix Inc. Controller and operation method thereof
KR20220025189A (en) * 2017-12-29 2022-03-03 마이크론 테크놀로지, 인크. Uncorrectable ecc
CN117854569A (en) * 2024-03-05 2024-04-09 合肥康芯威存储技术有限公司 Performance test system and performance test method for memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120107126A (en) * 2009-12-30 2012-09-28 샌디스크 테크놀로지스, 인코포레이티드 Method and controlller for performing a copy-back operation
KR20120136674A (en) * 2011-06-09 2012-12-20 삼성전자주식회사 On-chip data scrubbing method and apparatus with ecc
KR20130143140A (en) * 2011-04-26 2013-12-30 엘에스아이 코포레이션 Variable over-provisioning for non-volatile storage
KR20140131261A (en) * 2013-05-03 2014-11-12 실리콘 모션 인코포레이티드 Method for reading data from block of flash memory and associated memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120107126A (en) * 2009-12-30 2012-09-28 샌디스크 테크놀로지스, 인코포레이티드 Method and controlller for performing a copy-back operation
KR20130143140A (en) * 2011-04-26 2013-12-30 엘에스아이 코포레이션 Variable over-provisioning for non-volatile storage
KR20120136674A (en) * 2011-06-09 2012-12-20 삼성전자주식회사 On-chip data scrubbing method and apparatus with ecc
KR20140131261A (en) * 2013-05-03 2014-11-12 실리콘 모션 인코포레이티드 Method for reading data from block of flash memory and associated memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220025189A (en) * 2017-12-29 2022-03-03 마이크론 테크놀로지, 인크. Uncorrectable ecc
KR102420955B1 (en) 2017-12-29 2022-07-15 마이크론 테크놀로지, 인크. Uncorrectable ecc
US11694760B2 (en) 2017-12-29 2023-07-04 Micron Technology, Inc. Uncorrectable ECC
US11194687B2 (en) 2019-01-02 2021-12-07 SK Hynix Inc. Controller and operation method thereof
CN117854569A (en) * 2024-03-05 2024-04-09 合肥康芯威存储技术有限公司 Performance test system and performance test method for memory
CN117854569B (en) * 2024-03-05 2024-05-24 合肥康芯威存储技术有限公司 Performance test system and performance test method for memory

Similar Documents

Publication Publication Date Title
US11893238B2 (en) Method of controlling nonvolatile semiconductor memory
US11922039B2 (en) Storage device that secures a block for a stream or namespace and system having the storage device
US10732898B2 (en) Method and apparatus for accessing flash memory device
US9026764B2 (en) Memory system performing wear leveling based on deletion request
US9552290B2 (en) Partial R-block recycling
US20160011782A1 (en) Semiconductor storage
KR20130088173A (en) Transaction log recovery
US20150103593A1 (en) Method of Writing Data in Non-Volatile Memory and Non-Volatile Storage Device Using the Same
KR101653999B1 (en) Storage system based on nand flash and data retention improving method
US20230161666A1 (en) Ecc parity biasing for key-value data storage devices
US10095417B1 (en) Method and system for improving flash storage read performance in partially programmed blocks
KR101412830B1 (en) Semiconductor memory and method of controlling thereof
JP2014178867A (en) Storage control device and storage control system

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20190731

Year of fee payment: 4