KR101651573B1 - Semiconductor memory device and programming method thereof - Google Patents

Abstract

Provided are a semiconductor memory device and a programming method thereof that can reduce the programming time while maintaining the reliability of data.
In the NAND flash memory of the present invention, the detection circuit 130 that loads the programming data input from the external input / output terminal into the page buffer / sense circuit 170 and monitors the programming data determines whether or not the programming data is a specific bit string . Programming data held in the page buffer / sense circuit 170 is transmitted to the ECC circuit 120 by the transfer / write circuit 200 when the program data is detected to be not a specific bit string, and the error generated by the ECC operation The correction code is written to the page buffer / sense circuit 170. [ On the other hand, when a specific bit string is detected, the transmission of the programming data stored in the page buffer / sense circuit 170 is inhibited and the existing error correction code corresponding to the specific bit string is written to the page buffer / sense circuit 170 .

Description

[0001] DESCRIPTION [0002] Semiconductor memory devices and programming methods [

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its programming method, and to error detection and correction of input / output data of a semiconductor memory device, and more particularly to error detection and correction of input data of a NAND type flash memory.

In semiconductor memories such as flash memories and DRAMs, the degree of integration increases year by year, making it difficult to manufacture memory elements free from defects or defects. Therefore, on the memory chip, a redundancy scheme is used to apparently remedy the physical defects of the memory elements that occur during the manufacturing process. For example, in some redundancy schemes, a redundant memory is provided so as to save memory elements having physical defects. In the semiconductor memory, an error detection correction circuit (ECC: Error Checking Correction) is used as a soft error countermeasure in addition to the physical remedy by the redundancy memory.

In the NAND type flash memory, programming or erasing of data is repeated, so that the charge holding characteristic deteriorates due to the deterioration of the tunnel insulating film or the threshold value fluctuation occurs due to the charge trapped in the tunnel insulating film, thereby causing a bit error. In Patent Document 1, an error detection and correction circuit is mounted as a countermeasure against bit errors. In particular, in memory cells close to block select transistors, bit error rate tends to increase due to unevenness of pattern due to lithography, irregularity of ion implantation during diffusion layer formation, and an ECC code is stored so that it can be more remedied.

In addition to storing one bit of data in one memory cell, the NAND type flash memory may store multi-bit data in one memory cell. Patent Document 2 discloses an error correction scheme for such multi-bit data. Also, in Patent Document 3, an ECC code is generated by adding ECC parity to input data, a generated ECC code is written to a physical block, and an error is detected by an ECC code when there is an error in page data read from the physical block And registers a physical block having a corrected error number equal to or greater than the threshold value as a warning block in the table to lower the priority of the warning block selection at the time of data writing.

Patent Document 1: JP-A-2010-152989 Patent Document 2: JP-A-2008-165805 Patent Document 3: JP-A-2010-79486

The NAND type flash memory that mounts the ECC circuit on-chip stores the input data in the page buffer, transfers the data stored in the page buffer to the ECC circuit, and generates an error correction code Code) into the page buffer and then programmed the data in the page buffer to the selected page of the memory array. However, ECC operations on all page data to be programmed take a long time to process. In the NAND type flash memory, since programming is performed page by page, the time required for the operation of the ECC circuit increases in proportion to the increase in the number of bits per page due to the high integration. This may be a hindrance to shortening the programming time.

The present invention solves the above-described conventional problems, and provides a semiconductor memory device and a programming method thereof that can reduce the programming time while maintaining the reliability of data.

A semiconductor memory device according to the present invention comprises a memory array, data holding means for holding and holding data read from the memory array or writing data to the memory array, An error detecting and correcting means for correcting error correcting codes generated by the error correcting means, transmitting means for transmitting data to the error detecting and correcting means in the data storing and holding means, writing means for writing the error correcting codes generated by the error detecting correcting means in the data storing and holding means, And a detecting means for detecting whether or not the data input to the data holding and holding means has a specific bit string, wherein when said specific bit string is detected, said transmitting means prohibits transmission of data corresponding to said specific bit string, The writing means may write a predetermined error correction code It is written in the data storage holding means.

The specific bit string is a bit string composed of logic 0 or a bit string composed of logic 1. And the specific bit string is the same number of bits as the number of bits transmitted by the transmitting means at one time. The data holding and holding means is divided into a plurality of sectors, the transmitting means transmits data on a sector-by-sector basis, and the error correction means performs error correction processing on a sector-by-sector basis. And the specific bit string is equal to the number of bits of one page stored and held by the data holding and holding means. The semiconductor memory device further includes a memory means for storing the relationship between the specific bit string and the error correction code, and the writing means writes the error correction code corresponding to the specific bit string on the basis of the detection result of the detection means. The writing means includes a logic circuit for generating an error correction code corresponding to a specific bit string on the basis of the detection result of the detection means, and writes the error correction code generated by the logic circuit concerned. The semiconductor memory device includes a plurality of external input / output terminals, and data input from a plurality of external input / output terminals are loaded in parallel in the data storage / holding means, and the detecting means determines whether each of the data input in parallel includes a specific bit string . The detecting means includes a detecting circuit for detecting the presence or absence of transition of bit data.

A programming method of a NAND type flash memory according to the present invention is a method for programming a NAND type flash memory by loading programming data input from an external input / output terminal into a page buffer to detect whether or not the programming data is a specific bit string, The program data stored in the buffer is transferred to the ECC circuit, the error correction code generated by the ECC operation is written into the page buffer, and when a specific bit string is detected, transmission of the program data stored in the page buffer is performed And writes an existing error correction code corresponding to the specific bit string into the page buffer.

According to the present invention, when the data to be input to the data holding and holding means is a specific bit string, it is prohibited to transfer the data from the data holding and holding means to the error correction means and the error correction code is stored in the data It is possible to reduce the data transfer time from the data storage and holding means to the error correction means and shorten the data programming time to the memory array.

1 is a diagram showing a schematic configuration of an entire NAND flash memory according to an embodiment of the present invention.
2 is a circuit diagram showing a configuration of a NAND string of a memory cell array according to an embodiment of the present invention.
3 is a diagram showing an example of the voltages applied to the respective portions during the programming of the flash memory according to the embodiment of the present invention.
4 is a view for explaining the flow of data input to the flash memory according to the embodiment of the present invention.
5 is a diagram showing an example of the detection circuit of this embodiment.
6 is a table for defining the relationship between a specific bit string and an existing error correction code.
7 is a diagram for explaining a normal ECC process according to an embodiment of the present invention.
8 is a view for explaining an example in which ECC processing according to the embodiment of the present invention is skipped.
Fig. 9 is a flowchart for explaining the ECC process of the conventional flash memory.
10 is a flowchart for explaining the ECC processing of the flash memory according to the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. Here, a NAND type flash memory is exemplified. Also, it should be noted that the drawings are emphasized in order to facilitate understanding and are different from the actual device scale.

<Examples>

A typical configuration of a flash memory according to an embodiment of the present invention is shown in Fig. However, the configuration of the flash memory shown here is merely an example, and the present invention is not necessarily limited to such a configuration. The flash memory 10 of the present embodiment includes a memory array 100 in which a plurality of memory cells are arranged in a matrix form, an input / output buffer 110 connected to the external input / output terminal I / O to store and retain input / output data, An ECC circuit 120 for error detection and correction of data to be programmed in the array 100 or data read out therefrom and data input to the page buffer / sense circuit 170 in the external input / output terminal or the input / A detection circuit 130 for monitoring a specific bit string therefrom, an address register 140 for receiving address data from the input / output buffer 110, command data from the input / output buffer 110, A control unit 150 for receiving signals and controlling the respective units, a control unit 150 for receiving row address information Ax from the address register 140 and decoding and decoding the row address information Ax A word line selection circuit 160 for selecting a block and a word line based on a page selected by the word line selection circuit 160 and a page holding and retaining data read from the page selected by the word line selection circuit 160 Receives the column address information Ay from the buffer / sense circuit 170 and the address register 140 and decodes the column address information Ay and outputs the data in the page buffer / sense circuit 170 (A write voltage Vpgm, a pass voltage Vpass, a read pass voltage Vread, an erase voltage Vers, etc.) necessary for data reading, programming and erasing, And an internal voltage generating circuit 190 for generating an internal voltage.

The memory array 100 includes m memory blocks BLK (0), BLK (1), ..., BLK , And BLK (m-1). A page buffer / sense circuit 170 is arranged near the block BLK (0). In addition to such a configuration, the page buffer / sense circuit 170 may be disposed at the other end or both end portions of the memory array 100.

As shown in Fig. 2, one memory block is provided with a plurality of NAND cell units NU in which a plurality of memory cells are connected in series, and n + 1 cell units NU are arranged in the row direction in one memory block have. The cell unit NU includes a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series and a selection transistor TD connected to the drain side of the memory cell MC31, And a selection transistor TS connected to the source side of the memory cell MC0 at the other end and the drain of the selection transistor TD is connected to a corresponding one bit line GBL, TS are connected to a common source line SL.

The control gates of the memory cells MCi are connected to the word lines WLi and the gates of the select transistors TD and TS are connected to the select gate lines SGD and SGS which are in parallel with the word lines WL do. The word line selection circuit 160 selectively connects the selection transistors TD and TS through the selection gate lines SGD and SGS of the block when the block is selected based on the row address Ax or the converted address . Fig. 2 shows the structure of a typical cell unit. However, the cell unit may include one or a plurality of dummy cells in a NAND string.

The memory cell typically includes a source / drain which is an N-type diffusion region formed in the P-well, a tunnel oxide film formed on the channel between the source / drain, a floating gate (charge storage layer) formed on the tunnel oxide, And a control gate formed with a dielectric film therebetween. When no charge is accumulated in the floating gate, that is, when data &quot; 1 &quot; is written, the threshold value is in the negative state and the memory cell is normally on. When electrons are accumulated in the floating gate, that is, when data &quot; 0 &quot; is written, the threshold value is shifted in positive and the memory cell is normally off. However, the memory cell may be an SLC type storing one bit (binary data) or an MLC type storing a plurality of bits.

3 is a table showing an example of a bias voltage applied in each operation of the flash memory. In the read operation, a certain voltage is applied to the bit line, a certain voltage Vx (for example, 0 V) is applied to the selected word line, a pass voltage Vpass (for example, 4.5 V And a positive voltage (for example, 4.5 V) is applied to the select gate lines SGD and SGS to turn on the bit line select transistor TD and the source line select transistor TS, 0V is applied to the line. In programming (writing) operation, a program voltage Vpgm (15 to 20 V) of a high voltage is applied to a selected word line, an intermediate potential (for example, 10 V) is applied to a non-selected word line, And turns off the source line select transistor TS to supply a potential corresponding to data of "0" or "1" to the bit line GBL. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P-well, and electrons of the floating gate are extracted to the substrate to erase data in block units.

4 shows the flow of data input from the external input / output terminal of the flash memory 10 of the present embodiment. The input data Di provided in the input / output buffer 110 is loaded into the page buffer / sense circuit 170 and also input to the detection circuit 130. The detection circuit 130 detects whether the input data Di is data including a specific bit string. A specific bit string is a bit string for which no error detection correction operation is required, or a bit string whose error correction code is known. In one example, the detection circuit 130 detects a bit string in which all the input data Di is "0" or a bit string in which all the input data is "1".

The detection circuit 130 can detect a specific bit string of the input data Di by a logic circuit. 5 is an example of a detection circuit when all the bit strings of the input data Di detect "0" or "1". The detection circuit 130 includes a two-input OR circuit 132 and an AND circuit 134 for inputting the i-th data of the input data Di and the (i-1) th data (i is an integer of two or more) And a flag circuit 136 for setting flag information based on the output of the circuit. When all of the input data Di is &quot; 0 &quot;, the output of the OR circuit 132 is at the L level and the other is at the H level. When all the input data Di are &quot; 1 &quot;, the output of the AND circuit 134 is at the H level and the other is at the L level. The flag circuit 136 outputs a detection signal S that can discriminate that the input data Di are all "0" and all "1". For example, when the detection signal S is composed of 2-bit data and is "00", the input data Di are all "1" when the input data Di are all "0" and "11". The detection signal S of the detection circuit 130 is provided to the transfer / write circuit 200 and the ECC circuit 120.

The ECC circuit 120 generates an error correction code or a parity bit necessary for error detection and correction of the input data Di by calculating the input data Di. The calculation of the ECC is performed by a known method such as Hamming code or Reed-Solomon, and converts the inputted k bits or k bytes of input data Di into p = k + q. In this specification, &quot; q &quot; is referred to as an error correction code or parity bit necessary for error detection correction of the input data Di.

Between the page buffer / sense circuit 170 and the ECC circuit 120, a transfer / write circuit 200 is provided. The transfer / write circuit 200 transfers the input data Di stored in the page buffer / sense circuit 170 to the ECC circuit 120. The transfer / write circuit 200 also writes the error correction code generated by the ECC circuit 120 in the spare area of the page buffer / sense circuit 170.

The transmission / writing circuit 200 prohibits transmission of the input data Di held and held in the page buffer / sense circuit 170 when the detection circuit 130 detects that the input data Di is a specific bit string do. That is, the ECC circuit 120 does not execute the ECC operation of the input data Di. The ECC circuit 120 generates an existing error correction code of the input data Di (= a specific bit string) and provides it to the transmission / writing circuit 200, and the transmission / And writes the error correction code in the spare area of the page buffer / sense circuit 170. [

In one example, the ECC circuit 120 may include a table defining the relationship between a particular bit string and an existing error correction code. An example of the table is shown in Fig. When the ECC circuit 120 receives the detection signal S from the detection circuit 130, the ECC circuit 120 reads out an existing error correction code corresponding to a specific bit string based on the detection signal S, . For example, when all of the input data Di is "0" (in this example, the detection signal S is "00"), the conventional error correction code EC0 is outputted to the transmission / When the input data Di are all "1" (in this example, the detection signal S is "11"), the conventional error correction code EC1 is output to the transfer / This table does not need to be stored and held by the ECC circuit 120, and the transfer / write circuit 200 may keep and maintain the table. Alternatively, the detection circuit 130 may preserve the table and provide an existing error correction code to the transfer / write circuit 200.

As another example, the ECC circuit 120 may be provided with a logic circuit for generating an existing error correction code based on the detection signal S. [ For example, an error correction code EC0 is generated when the detection signal S is "00", and an error correction code EC1 is generated when the detection signal S is "11" / Write circuit 200 shown in Fig. The ECC circuit 120 is not necessarily provided with a logic circuit for generating such an error correction code, and the transfer / write circuit 200 or the detection circuit 130 may be provided.

When the writing of the error correction code into the page buffer / sense circuit 170 by the transfer / write circuit 200 is completed, the input data Di and the error correction code Is programmed to the selected page of the memory array (100).

The data read from the selected page of the memory array 100 in the read operation is stored in the page buffer / sense circuit 170 and then transferred to the ECC circuit 120 through the transfer / The ECC circuit 120 determines whether or not there is a programming error or a read error based on the error correction code, and if there is an error caused by the error, corrects the data using the error correction code. The ECC processed data is transferred to the page buffer / sense circuit 170 through the transfer / write circuit 200 and then outputted to the outside through the input / output buffer 110.

In the present embodiment, when the detection circuit 130 detects that the input data Di is a specific bit, the input data Di stored in the page buffer / sense circuit 170 is supplied to the ECC circuit 120 The transmission is omitted and the conventional error correction code is written into the page buffer / sense circuit 170 without performing the calculation by the ECC circuit 120. This makes it possible to reduce the transfer time and the ECC calculation time of the input data Di from the page buffer / sense circuit 170 to the ECC circuit 120, thereby greatly shortening the time required for programming the input data Di.

Next, the description will be made using the example shown in FIG. 7 to FIG. The external input / output terminals of the flash memory 10 may be configured as x1, x4, x8, etc. Here, the example in which the flash memory 10 has x8 external input / output terminals is shown. 7, the external input / output terminals P-0 to P-7 are connected to the I / O buffers 110-1 to 110-7, respectively. The external input / output terminals P- To (P-7) are input to the I / O buffers 110-0 to 110-7 in parallel. The page buffer / sense circuit 170 includes a regular area 300 divided into eight sectors of sector 0 to sector 7 and a spare area 310 divided into four sectors of spare 0, spare 1, spare 2 and spare 3 ).

Eight external input / output terminals P-0 to P-7, that is, the input / output buffers 110-0 to 110-7, are provided in one sector of the regular area 300 of the page buffer / sense circuit 170 . The column selecting circuit 180 shown in Fig. 1 decodes the received column address information Ay and, based on the decoding result, the data inputted to the external input / output terminals P-0 to P-7 are loaded Select the sector. 7, the data received from the external input / output terminals P-0 to P-7 is loaded into the sector 0 according to the column address information Ay. In the example shown in FIG. 8, The data received in (P-0) to (P-7) is loaded into sector 1 according to column address information Ay. At the same time, the data loaded into each sector is input to the detection circuit 130, where it is monitored whether or not the input data is a specific bit string.

One sector of the regular area 300 is composed of, for example, 256 bytes, and 256 bits are allocated to one external input / output terminal (256 bits x 8 = 1 sector). In this case, eight sectors can store and maintain approximately 2K bytes of programming data as a whole. One sector of the spare area 310 is composed of, for example, 16 bytes. In this case, four sectors (spare 0 to spare 3) can hold and retain 64 bytes of data as a whole. One sector of the spare area 310 includes an area 311 for storing information for identifying a bad block including a bad memory element, an area 312 for storing information about user data, Areas 313 and 314 for storing error correction codes (parity bits) for each sector and an area 315 for storing error correction codes (parity bits) when the spare area 310 is subjected to ECC operation . Areas 313 and 314 of spare 0 in spare area 310 store sector 0 and error correction code (parity bit) of sector 1 in regular area 300 and spare 1 313 and 314 store the error correction codes (parity bits) of sector 2 and sector 3 of the regular area 300. [ Similarly, the spare 2 of the spare area 310 stores the parity bits of the sector 4 and the sector 5 of the regular area 300 and the spare 3 of the spare area 310 stores the parity of the sector 6 and the sector 7 of the regular area 300 Bit.

The transfer / write circuit 200 transfers data stored in the regular area 300 on a sector-by-sector basis. That is, when one sector is 256 bytes, the transfer / write circuit 200 has a plurality of transfer transistors for transferring 256 bytes of data to the ECC circuit 120 in parallel. A control signal is commonly connected to each gate of the transfer transistor, and the control signal is controlled by the control unit 150. [ The ECC circuit 120 receives data transmitted in units of sectors and performs an ECC operation to generate an error correction code. The transmission / write circuit 200 writes the error correction code received from the ECC circuit 120 in the area 313 or 314 of the corresponding sector of the spare area 310. [

7 shows an example in which the input data Di, that is, programming data is loaded into sector 0 of the regular area 300. In the example shown in Fig. In this case, since the input data Di does not correspond to a specific bit string, the detection signal S by the detection circuit 130 does not inhibit the transmission from the transmission / Therefore, the transfer / write circuit 200 transfers the input data Di to the ECC circuit 120 and the error correction code generated by the ECC circuit 120 is transferred to the area 313 of the spare 0 in the spare area 310 .

8 shows an operation when the input data Di has a specific bit string. When the detection circuit 130 detects that the input data Di loaded in the sector 1 of the regular area 300 corresponds to a specific bit string, the detection signal S is supplied to the transfer / (Not shown). The transfer / write circuit 200 inhibits the transfer of the input data Di of the sector 1 to the ECC circuit 120 in response to the detection signal S. The ECC circuit 120 identifies a specific bit string based on the detection signal S and provides an error correction code corresponding to the specific bit string to the transmission / Then, the transmission / write circuit 200 writes the error correction code of the sector 1 in the area 314 of the spare 0 in the spare area 310.

FIG. 9 shows a conventional ECC processing flow, and FIG. 10 shows an ECC processing flow of this embodiment. First, the conventional ECC processing operation will be described. External control signals and command data, address data, and programming data are supplied to the flash memory 10 from the external controller. The control unit 150 starts the program operation based on the external control signal and the command data.

When the programming data (input data Di) is loaded into the page buffer / sense circuit 170 through the external input / output terminal and the input / output buffer 110 (S100), the programming sequence starts under the control of the control unit 150 ). The data of the sector 0 stored in the page buffer / sense circuit 170 is transferred to the ECC circuit 120 through the transfer / write circuit 200 (S104). Next, an ECC operation is performed in the ECC circuit 120, and the generated parity bit is written into the spare area 310 of the page buffer / sense circuit 170 (S108).

Next, whether or not there is an ECC unprocessed sector is determined by the control unit 150 or the transfer / write circuit 200 (S110). In this manner, data of all the sectors of the page buffer / sense circuit 170 is subjected to ECC processing, and parity bits for each sector are written in the sectors 313 and 314 of the corresponding sector of the spare area 310. In addition, the NAND type flash memory is programmed in units of pages, and the size of input programming data does not necessarily have to be the same as the size of eight sectors in one page, that is, the regular area 300 shown in FIG. For example, the size of the programming data may be one sector size. There is a limitation on the number of times (NOP (Number of Program)) that is allowed to continuously program on the same page from the viewpoint of the normal programming disturb, and one page data can be divided and programmed according to the NOP. When NOP is 4, one page data can be divided into two sectors, for example, two sectors, one sector, three sectors, and two sectors, and input to the flash memory 10.

When the ECC process of the regular area is completed, the ECC process of the spare area is executed next. 7, the data of spare 0 in the spare area 310 is transferred to the ECC circuit 120 by the transfer / write circuit 200 (S112), and the ECC process is executed there (S114) The generated parity bit is written in the area 315 (S116). It is judged whether or not there is an unprocessed sector of the ECC (S118), and if there is such a sector, steps S112 to S116 are repeated. In this manner, ECC processing of all the sectors in the spare area 310 is executed. When the ECC processing of all the data stored in the regular area 300 and the spare area 310 of the page buffer / sense circuit 170 is completed, the data held in the page buffer / sense circuit 170 is selected (S120).

On the other hand, in the flash memory 10 of the present embodiment, as shown in Fig. 10, the programming data is loaded into the page buffer / sense circuit 170 (S200) (S202). When the loading of the programming data into the page buffer / sense circuit 170 is completed, the programming sequence is started (S204).

As soon as the programming data of each sector is input to the page buffer / sense circuit 170, the detection circuit 130 detects whether the programming data of each sector is a specific bit string (S206). If the programming data of the sector does not coincide with the specific bit string, the programming data of the corresponding sector is transferred to the ECC circuit 120 and ECC processing is executed (S208, S210). That is, the ECC process shown in Fig. 7 is executed. On the other hand, when the detection circuit 130 detects that the programming data of the sector coincides with the specific bit string, the transfer / write circuit 200 does not transfer the sector to the ECC circuit 120 of the programming data, Does not execute the ECC operation for the programming data of the corresponding sector. Accordingly, the processing of steps S208 and S210 is skipped. The ECC circuit 120 identifies a specific bit string based on the detection signal S instead of skipping the ECC operation and outputs the existing parity bit corresponding to the identified specific bit string to the transmission / , The transfer / write circuit 200 writes the existing parity bit in the area 313 or 314 of the spare area 310. [ This processing is performed for all the sectors in the regular area 300 of the page buffer / sense circuit 170 (steps S206 to 214). When ECC processing in the regular area 300 ends, ECC processing to the spare area 310 is executed next. The ECC processing of the spare area 310 is the same as the conventional method shown in Fig. 9, and thus the description thereof will be omitted.

As described above, according to the present embodiment, when programming data of a specific bit string having a known error correction code is inputted, the page buffer / sense circuit 170 does not transmit the programming data to the ECC circuit 120, The programming time of the input data can be shortened. In particular, the time required for transferring data from the page buffer / sense circuit 170 to the ECC circuit 120 is relatively large, which contributes greatly to shortening the programming time.

In the above embodiment, the example in which the data stored in the page buffer / sense circuit 170 is transferred to the ECC circuit 120 is shown, but the page buffer / sense circuit 170 has one or a plurality of cache memory devices The present invention can also be applied to a pipeline structure. In this case, the data transfer between the cache memory and the ECC circuit is skipped.

Although the embodiments of the present invention have been described above, the present invention is not limited to the specific embodiments, and various modifications and changes may be made within the scope of the gist of the invention described in the claims.

10: Flash memory
100: memory array
110: I / O buffer
120: ECC circuit
130: Detection circuit
140: address register
150:
160: Word line selection circuit
170: page buffer / sense circuit
180: Thermal select circuit
190: internal voltage generating circuit
200: transfer / write circuit
300: Regular area
310: spare area

Claims (13)

Memory arrays,
Data holding means for holding and holding data read from the memory array or storing data to be written in the memory array,
Error detection correction means for correcting error detection of data,
Transfer means for transferring data from the data storage and holding means to the error detection correction means,
Writing means for writing the error correction code generated by the error detection correction means to the data storage /
And a detecting unit that detects whether or not the data input to the data holding and holding unit has a specific bit string,
When said specific bit string is detected, said transmitting means prohibits transmission of data corresponding to said specific bit string, and said writing means writes a predetermined error correction code in said data storage holding means,
Wherein the specific bit string is a bit string in which it is not necessary to perform an error detection correction operation or a bit string in which an error correction code is known. The semiconductor storage device according to claim 1, wherein the specific bit string is a bit string composed of a logical zero. The semiconductor memory device according to claim 1, wherein the specific bit string is a bit string made up of logic one. The semiconductor memory device according to any one of claims 1 to 3, wherein the specific bit string has the same number of bits as the number of bits transmitted by the transmitting means at one time. The semiconductor memory device according to claim 1, wherein said data storage and holding means is divided into a plurality of sectors, said transmitting means transmits data on a sector-by-sector basis, and said error correction means performs error correction processing on a sector-by-sector basis. The semiconductor storage device according to any one of claims 1 to 3, wherein the specific bit string is equal to the number of bits of one page stored and held by the data storage and holding means. The semiconductor memory device according to any one of claims 1 to 3, further comprising: storage means for storing a relationship between a specific bit string and an error correction code, wherein said writing means writes, on the basis of the detection result of said detection means, And the corresponding error correction code is written. The semiconductor memory device according to any one of claims 1 to 3, wherein the writing means includes a logic circuit for generating an error correction code corresponding to a specific bit string on the basis of the detection result of the detection means, To the semiconductor memory device. The semiconductor memory device according to any one of claims 1 to 3, wherein data inputted from a plurality of external input / output terminals, including a plurality of external input / output terminals, are loaded into the data storage / holding means in parallel, And detects whether or not each of the input data includes a specific bit string. The semiconductor storage device according to claim 1, wherein the memory array is a NAND type memory array, and the data holding means includes a page buffer. As a programming method of the NAND type flash memory,
The programming data input from the external input / output terminal is loaded into the page buffer,
Detects whether the programming data is a specific bit string,
When it is detected that the specific bit string is not a specific bit string, the program data stored in the page buffer is transmitted to the ECC circuit, and the error correcting code generated by the ECC operation is written into the page buffer. On the other hand, Prohibiting transmission of the programming data stored in the buffer and writing the existing error correction code corresponding to the specific bit string into the page buffer,
Wherein the specific bit string is a bit string in which it is not necessary to perform an error detection correction operation or a bit string in which an error correction code is known. 12. The programming method according to claim 11, wherein the programming data are all bit strings of logic &quot; 0 &quot;. 12. The method according to claim 11, wherein the programming data are all bit strings of logic &quot; 1 &quot;.

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