KR101651291B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an organic light emitting diode display device, which comprises a data driver for converting RGB digital video data into RGB data voltages using RGB gamma compensation voltages and supplying the RGB data voltages to data lines; A scan driver for supplying a scan pulse to the scan lines; RGB digital gamma data in which luminance and color coordinates are kept constant at each frame frequency are individually set for each RGB, and a frame change notification signal and a count value of a vertical synchronization signal input from the outside are inputted, A lookup table for selecting RGB digital gamma data set to a frequency; And a gamma compensation voltage generator for adjusting the RGB gamma compensation voltage according to the RGB digital gamma data received from the lookup table.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such a flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) And a light emitting device (Electroluminescence Device).

The electroluminescent device is divided into an inorganic electroluminescent device and an organic light emitting diode (OLED) according to the material of the light emitting layer, and is a self-luminous device which emits itself, has a high response speed and a large luminous efficiency, luminance and viewing angle have.

The organic light emitting diode display device can be driven by driving methods such as voltage driving, voltage compensation, current driving, digital driving, and external compensation, and in recent years, voltage compensation driving methods have been selected the most.

When the frame frequency of an image signal inputted to the organic light emitting diode display device is changed, the threshold voltage sampling of a driving thin film transistor (hereinafter, referred to as "TFT ") in each of the light emitting cells is changed. As a result of the experiment, the color organic light emitting devices in which the TFTs for driving the organic light emitting diode (OLED) in each of the light emitting cells are implemented by a p-type MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) When driving, the luminance and white color coordinates are measured as 200 nits, (x: 0.28, y: 0.29), but when the frame frequency is reduced to 60 Hz, the luminance and white color coordinates change to 120 nit, (x: 0.27, y: 0.28).

It is therefore an object of the present invention to provide an organic light emitting diode display device which prevents variations in luminance and chromaticity coordinates when a frame frequency changes.

According to an embodiment of the present invention, there is provided an organic light emitting diode display device including: an organic light emitting diode; and light emitting cells including a driving circuit of the organic light emitting diode are arranged in a matrix, ≪ / RTI > A data driver for converting the RGB digital video data into an RGB data voltage using the RGB gamma compensation voltage and supplying the converted RGB data voltage to the data lines; A scan driver for supplying a scan pulse to the scan lines; RGB digital gamma data in which luminance and color coordinates are kept constant at each frame frequency are individually set for each RGB, and a frame change notification signal and a count value of a vertical synchronization signal input from the outside are inputted, A lookup table for selecting RGB digital gamma data set to a frequency; And a gamma compensation voltage generator for adjusting the RGB gamma compensation voltage according to the RGB digital gamma data received from the lookup table.

In the organic light emitting diode display device of the present invention, the threshold voltage sampling value of the driving TFT is varied in each of the discharge cells when the frame frequency is changed, but it is possible to prevent the luminance and the color coordinate change by varying the RGB gamma voltage.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6. FIG.

1, an organic light emitting diode display device according to a first embodiment of the present invention includes a display panel 100 in which m × n (m and n are positive integers) light emitting cells are arranged in a matrix, A scan driver 104 for sequentially supplying scan pulses to the scan lines and emission control lines intersecting with the data lines, and a scan driver 104 for applying the RGB gamma compensation voltage A gamma compensation voltage generating section 102 for supplying the gamma compensation voltages V _RG , V _GG and V _BG to the data driving circuit 103 and a control circuit for controlling the driving circuits 103 and 104 and the gamma compensation voltage generating section 102 And a timing controller (101)

The light emitting cells of the display panel 100 are formed in the pixel regions defined by the intersection of the data lines and the scan lines. The light emitting cells of the display panel 100 are commonly supplied with a high potential power supply voltage VDD, a low potential power supply voltage or a ground voltage GND and a reference voltage Vref as shown in FIGS. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the low potential power supply voltage or the ground voltage GND may be lower than the threshold voltage of the organic light emitting diode OLED. Respectively. The reference voltage Vref may be set to a negative voltage so as to apply a reverse bias to the organic light emitting diode OLED at the time of initialization of the driving element connected to the organic light emitting diode OLED. In this case, since the reverse bias is periodically applied to the organic light emitting diode device OLED, deterioration of the organic light emitting diode device OLED can be reduced and the lifetime can be extended. Each of the light emitting cells includes an organic light emitting diode OLED, five TFTs T11 to T14, a driving device DTFT1, a boost capacitor Cbst, and a storage capacitor Cstg as shown in FIGS. 3 and 4 , An organic light emitting diode (OLED), five TFTs (T21 to T25), a driving device (DTFT2), and a storage capacitor (Cstg), as shown in FIGS.

The data driver 103 converts the digital video data RGB input from the timing controller 101 into RGB gamma compensation voltages and supplies the RGB gamma compensation voltages to the data lines. The scan driver 104 sequentially supplies the scan pulses SEL_N-1 and SELN shown in FIG. 4 or the scan pulses SR01 and Scan shown in FIG. 6 to the scan lines in sequence. In addition, the scan driver 104 sequentially supplies the emission control pulses EM shown in FIGS. 4 and 6 to the emission control lines.

The timing controller 101 supplies the digital video data RGB to the data driver 103 and outputs a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a dot clock CLK And generates timing control signals CS and CG for controlling the operation timings of the data driver 103 and the scan driver 104 by using the timing control signals CS and CG. The timing controller 101 changes the RGB gamma compensation voltage output of the gamma compensation voltage generator 102 in real time when the frame frequency of the input video signal is changed to prevent the luminance and the color coordinate change due to the frame frequency variation.

The gamma compensation voltage generating unit 102 includes a programmable gamma correction unit 112 for adjusting the voltages of the RGB gamma compensation voltages V _RG , V _GG , and V _BG individually set for each RGB according to the RGB digital gamma data input from the timing controller 101, And is implemented by a programmable gamma compensation voltage generator.

The first embodiment of the timing controller 101 varies the output of the gamma compensation voltage generator 102 when the frame frequency is changed according to the frame change notification signal FS input from the outside as shown in FIG. The frame change notification signal FS is input from the external system board as a signal having a different logic value according to the frame frequency in synchronization with the vertical synchronization signal Vsync defining the frame period. For example, a logic value of the frame change notification signal FS is generated as '00' when the frame frequency is 60 Hz, and a logic value of the frame change notification signal FS is generated as '01' when the frame frequency is 120 Hz .

The timing controller 101 includes a look-up table 105 for selecting RGB digital gamma data with the frame change notification signal FS as an address. In the lookup table 105, RGB digital gamma data in which the luminance and the color coordinate are kept constant at each frame frequency are set through experiments. RGB digital gamma data is set individually for each RGB. The lookup table 105 selects the RGB digital gamma data set at the frame frequency of the current input image with the frame change notification signal FS as the input address and outputs the RGB gamma compensation voltage outputted from the gamma compensation voltage generation unit 102 as Adjust.

Fig. 2 shows a second embodiment of the timing controller 102. Fig.

Referring to FIG. 2, the timing controller 101 determines the frame frequency of the input image in real time using the frame frequency detection circuit, and varies the output of the gamma compensation voltage generator 102 when the frame frequency is changed. The timing controller 101 shown in FIG. 2 includes a frame frequency sensing circuit for sensing a frame frequency of an input image in real time when a frame change notification signal FS is not generated on an external system board as shown in FIG.

The frame frequency sensing circuit includes an oscillator 21, a D flip-flop 22, a Vsync logic determination section 23, a counter 24, a latch 25, and a lookup table 26.

The oscillator 21 constantly generates a reference clock frequency of, for example, 100 Mhz. A vertical synchronization signal Vsync is input to the input terminal of the D flip-flop 22 and a reference clock frequency is input to the clock terminal. The D flip-flop 22 generates an output every time a reference clock is input to generate a vertical synchronization signal synchronized with the reference clock.

The Vsync logic determination section 23 determines the logical value of the signal input from the D flip-flop 22 and supplies the input terminal of the counter 24 with the logical value of HIGH, while the D flip- - Reset the counter 24 when the output of the flop 22 changes to Low. The counter 24 increases the count value of the high logic signal input from the Vsync logic determination section 23 according to the reference clock and outputs the count value to the Vsync logic determination section 23 under the control of the Vsync logic determination section 23 when the vertical synchronization signal Vsync changes to the low logic Reset the count value. Therefore, the counter 24 outputs a count value indicating the active high section of the vertical synchronization signal Vsync to the latch 25 every frame period.

The latch 25 stores the count value input from the counter 24 and supplies the count value to the lookup table 26 in the low section of the vertical synchronization signal Vsync. In the lookup table 26, RGB digital gamma data in which the luminance and the color coordinate are kept constant at each frame frequency are set through experiments. RGB digital gamma data is set individually for each RGB. The lookup table 26 adjusts the RGB gamma compensation voltage output from the gamma compensation voltage generator 102 by selecting the RGB digital gamma data with the count value input from the latch 25 as the input address.

Figs. 3 and 4 show a first embodiment of a light emitting cell and its driving waveform.

3 and 4, the light emitting cells include first to fourth TFTs T11 to T14, a driving TFT DTFT1, a storage capacitor Cstg, a boost capacitor Cbst, and a light emitting diode OLED do. The first to fourth TFTs T11 to T14 and the driving element DTFT1 are implemented as a p-type MOSFET.

The first TFT T11 responds to the scan pulse from the (N-1) th (N is a positive integer) scan line to the reference voltage Vref during the first and second periods t11 and t12 And supplies it to the first node n1. The drain electrode of the first TFT T11 is connected to the first node n1, and the source electrode thereof is connected to the reference voltage source Vref. The gate electrode of the first TFT T11 is connected to the (N-1) th scan line SEL_N-1.

The second TFT T12 supplies the data voltage Data to the first node n1 during the third period t13 in response to the scan pulse SEL_N from the Nth scan line. The drain electrode of the second TFT T12 is connected to the first node n1, and the source electrode thereof is connected to the data line. And the gate electrode of the second TFT T12 is connected to the Nth scan line SEL_N.

The third TFT T13 may apply the voltage of the second node n2 during the first and second periods t11 and t12 to the fourth TFT (n2) in response to the scan pulse SEL_N-1 from the N- T14 and the drain electrode of the driving TFT DTFT1. The source electrode of the third TFT T13 is connected to the second node n2 and the drain electrode thereof is connected to the source electrode of the fourth TFT T14 and the drain electrode of the driving element DTFT1. The gate electrode of the third TFT T13 is connected to the (N-1) th scan line SEL_N-1.

The fourth TFT T14 is turned on in response to the light emission control pulse from the light emission control line during the second period t11 during the current path between the driving TFT DTFT1 and the third TFT T13 and the organic light emitting diode OLED And is turned on during the other period to form a current path between the driving TFT DTFT1 and the third TFT T13 and the organic light emitting diode OLED. The drain electrode of the fourth TFT T14 is connected to the anode electrode of the organic light emitting diode OLED and the source electrode thereof is connected to the drain electrodes of the driving TFT DTFT1 and the third TFT T13. The gate electrode of the fourth TFT (T14) is connected to the emission control line.

The driving TFT DTFT1 supplies a current from the high potential power source voltage source VDD to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving TFT DTFT1 is connected to the drain electrode of the third TFT T13 and the source electrode of the fourth TFT T14, and the source electrode thereof is connected to the high potential power source voltage source VDD. And the gate electrode of the driving TFT DTFT1 is connected to the second node n2.

The boost capacitor Cbst is connected between the first node n1 and the second node n2 and stores the data voltage DATA applied to the first node n1 during the third period t13, Boost by voltage. The storage capacitor Cstg is connected between the second node n2 and the source electrode of the driving TFT DTFT1 to maintain the gate-source voltage of the driving TFT DTFT1.

The organic light emitting diode (OLED) includes a red organic light emitting diode formed in a red subpixel, a green organic light emitting diode formed in a green subpixel, and a blue organic light emitting diode formed in a blue subpixel. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The organic light emitting diode OLED emits light for the third period t13 according to the current supplied under the control of the driving TFT DTFT1. The anode electrode of the organic light emitting diode (OLED) is connected to the drain electrodes of the third TFT (T13) and the driving TFT (DTFT1), and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source (GND).

The operation of the light emitting cell shown in FIG. 3 will be described step by step with reference to FIG.

During the first period t11, the first and third TFTs T11 and T13 are turned on and the second TFT T12 is turned off. At this time, the gate voltage of the driving TFT DTFT1 is initialized.

During the second period t12, the first and third TFTs T11 and T13 are kept on and the second and fourth TFTs T12 and T14 are turned off. During the second period t12, the boost capacitor Cbst and the storage capacitor Cstg sample the gate voltage of the driving TFT DTFT1 to (VDD-Vth), and the reference voltage Vref is applied to the first node n1 .

During the third period t13, the second and fourth TFTs T12 and T14 are turned on while the first and third TFTs T11 and T13 are turned off. During the third period t13, the voltage of the first node n1 is changed from the reference voltage Vref to the data voltage Vdata (Data N) by the second TFT T12, which is turned on in response to the Nth scan pulse SEL_N. (Vref > Vdata), and the voltage of the second node n2 at this time is lowered by (Vref-Vdata). During the third period, the organic light emitting diode (OLED) emits light with a luminance equal to the gray level of the Nth data.

When the frame frequency of the input image changes in the light emitting cells of FIGS. 3 and 4, t12 is changed and the threshold voltage (Vth) sampling time of the driving TFT is changed. As a result, when the frame frequency is changed to a high level, the sampling time is reduced, so that the luminance of the organic light emitting diode OLED is lowered and the color coordinates can be changed. The present invention adjusts the voltage of the RGB gamma compensation voltage supplied to the data driver when the frame frequency is changed to compensate for the luminance and the chromaticity coordinates, for example, by raising the RGB gamma compensation voltage when the frame frequency becomes high.

5 and 6 show a second embodiment of a light emitting cell and its driving waveform.

5 and 6, the light emitting cells include first to fifth TFTs T21 to T25, a driving TFT DTFT2, a storage capacitor Cstg, and a light emitting diode OLED. The first to fifth TFTs T21 to T25 and the driving TFT DTFT2 are implemented as a p-type MOSFET.

The first TFT T21 is turned on during the second and third periods t22 and t23 in response to the scan pulse from the second scan line SRO1 to turn on the data voltage Vdata: n1. The drain electrode of the first TFT (T21) is connected to the first node (n1), and its source electrode is connected to the data line. The gate electrode of the first TFT T21 is connected to the second scan line SRO1.

The second TFT T22 is turned off during the third period t23 in response to the emission control pulse from the emission control line EM1 to block the current path between the first node n1 and the reference voltage Vref And is turned on to supply the reference voltage Vref to the first node n1 during the other period. A reference voltage Vref is supplied to the source electrode of the second TFT T22, and the drain electrode thereof is connected to the first node n1. The gate electrode of the second TFT (T22) is connected to the emission control line (EM).

The third TFT T23 supplies the voltage of the second node n2 during the second and third periods t22 and t23 to the source of the fourth TFT T24 in response to the scan pulse from the second scan line SRO1. Electrode and the drain electrode of the driving TFT DTFT2. The source electrode of the third TFT T23 is connected to the second node n2 and the drain electrode thereof is connected to the source electrode of the fourth TFT T24 and the drain electrode of the driving element DTFT2. And the gate electrode of the third TFT T23 is connected to the second scan line SR01.

The fourth TFT T24 is turned off in response to the light emission control pulse from the light emission control line EM N to turn on the driving TFT DTFT2 and the third TFT T23 during the second and third periods t22 and t23, And a current path between the driving TFT DTFT2 and the third TFT T23 and the organic light emitting diode OLED is turned off during a period other than the current path between the organic light emitting diode OLED and the organic light emitting diode OLED, . The drain electrode of the fourth TFT T24 is connected to the anode electrode of the organic light emitting diode OLED and the source electrode thereof is connected to the drain electrodes of the driving TFT DTFT2 and the third TFT T23. The gate electrode of the fourth TFT (T24) is connected to the emission control line (EM1).

The fifth TFT T25 is turned on during the first to fourth periods t21 to t24 in response to the scan pulse from the first scan line Scan and is turned on between the third node n3 and the reference voltage source Vref Thereby forming a current path. The scan pulse width from the first scan line (Scan) is wider than the scan pulse width from the second scan line (SRO1). The rising time of the scan pulse from the first scan line SCAN is earlier than the rising time of the scan pulse from the second scan line SRO1 by the first period t21. The polling time of the scan pulse from the first scan line (Scan) is later than the polling time of the scan pulse from the second scan line (SRO1) by a predetermined time. The drain electrode of the fifth TFT (T25) is connected to the third node (n3), and its source electrode is connected to the reference voltage source (Vref). The gate electrode of the fifth TFT (T25) is connected to the first scan line (Scan).

The driving TFT DTFT2 supplies a current from the high potential power source voltage source VDD to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving TFT DTFT2 is connected to the drain electrode of the third TFT T23 and the source electrode of the fourth TFT T24, and the source electrode thereof is connected to the high potential power source voltage source VDD. And the gate electrode of the driving TFT (DTFT) is connected to the second node (n2).

The storage capacitor Cstf is connected between the first node n1 and the second node n2 to maintain the gate voltage of the driver TFT DTFT2.

The organic light emitting diode (OLED) includes a red organic light emitting diode formed in a red subpixel, a green organic light emitting diode formed in a green subpixel, and a blue organic light emitting diode formed in a blue subpixel. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL). The organic light emitting diode OLED emits light for a fourth period t24 during which the emission control line voltage maintains the low logic voltage in accordance with the current supplied under the control of the driving TFT DTFT2. The anode electrode of the organic light emitting diode (OLED) is connected to the third node (n3), and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source (GND).

The operation of the light emitting cell shown in FIG. 5 will be described step by step with reference to FIG.

During the first period t21, the fifth TFT T25 is turned on in response to the scan pulse from the first scan line Scan, and the voltage of the third node n3 is initialized to the reference voltage Vref do. During the first period t21, the voltage of the third node n3 is discharged to the reference voltage source Vref. At this time, since the voltage difference between the reference voltage Vref and the ground voltage GND is equal to or lower than the threshold voltage of the organic light emitting diode OLED or a reverse bias is applied to the organic light emitting diode OLED, Does not flow. During the first period t21, the second and fourth TFTs T22 and T24 are turned on while the first and third TFTs T21 and T23 are turned off.

During the second period t22, the first and third TFTs T21 and T23 are turned on in response to the scan pulse from the second scan line SR01. The gate electrodes of the second and fourth TFTs T22 and T24 are applied with the light emission control pulses which change from the low logic voltage to the high logic voltage during the second period t22. As a result, the second and third nodes n2 and n3 are initialized to the reference voltage Vref. At this time, since the fifth TFT T25 maintains the On state, the third node n3 maintains the reference voltage Vref. The organic light emitting diode OLED maintains the non-emission state during the second period t22 because the anode voltage is low at the reference voltage Vref.

During the third period t23, the threshold voltage of the driving TFT DTFT2 is stored in the storage capacitor Cstg. During the third period t23, the second and fourth TFTs T22 and T24 maintain the off state and the third node n3 maintains the reference voltage Vref.

During the fourth period t24, the second and fourth TFTs T22 and T24 are turned on because the voltage of the emission control line EM1 is inverted to the low logic voltage, while the first, third and fifth TFTs (T21, T23, T25) are turned off. Thus, the organic light emitting diode OLED emits for about one frame period from the fourth period t24.

The light-emitting cell circuit of the present invention can be variously modified. For example, in the embodiments described above, each of the TFTs may be selected as an n-type MOSFET, in which case the driving waveforms of Figs. 4 and 5 are generated in opposite phases. In addition, the number of TFTs can be reduced by combining a n-type MOSFET and a p-type MOSFET in a light emitting cell circuit by using a CMOS (Complementary Metal Oxide Semiconductor) process.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

1 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.

2 is a block diagram showing another embodiment of the timing controller shown in FIG.

3 is a circuit diagram illustrating a light emitting cell driving circuit according to a first embodiment of the present invention.

4 is a waveform diagram showing driving waveforms of the light emitting cell driving circuit shown in FIG.

5 is a circuit diagram showing a light emitting cell driving circuit according to a second embodiment of the present invention.

6 is a waveform diagram showing driving waveforms of the light emitting cell driving circuit shown in FIG.

Description of the Related Art

100: display panel 101: timing controller

102: gamma compensation voltage generator 103:

104:

Claims (6)

A display panel in which light emitting cells including an organic light emitting diode and a driving circuit of the organic light emitting diode are arranged in a matrix and data lines and scan lines cross each other; A data driver for converting the RGB digital video data into an RGB data voltage using the RGB gamma compensation voltage and supplying the converted RGB data voltage to the data lines; A scan driver for supplying a scan pulse to the scan lines; RGB digital gamma data in which luminance and color coordinates are kept constant at each frame frequency are individually set for each RGB, and a frame change notification signal and a count value of a vertical synchronization signal input from the outside are inputted, A lookup table for selecting RGB digital gamma data set to a frequency; And And a gamma compensation voltage generator for adjusting the RGB gamma compensation voltage according to the RGB digital gamma data received from the lookup table. delete The method according to claim 1, An oscillator for generating a reference clock of a predetermined frequency; A D flip-flop for synchronizing the vertical synchronization signal and the reference clock; A counter for counting a high logic interval at the output of the D flip-flop to the reference clock and outputting the count value; A Vsync logic determining section for detecting a high logic section of the output of the D flip-flop and supplying it to the counter and resetting the counter when the output of the D flip-flop changes to a logic low; And Further comprising a latch for storing a counter value input from the counter and outputting a count value stored in a low period of the vertical synchronization signal to the lookup table. delete delete delete

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