KR101646017B1 - Memory device with crossbar array structure and manufacturing method of the same - Google Patents

Abstract

The present invention discloses a memory device having a crossbar array structure and a method for manufacturing the same. The present invention is configured to include diodes which are disposed on the inside of a plurality of resistance variable memory cells. A leakage of electric current is remarkably diminished by setting the diodes, which are disposed in the memory cells sharing an electrode, such that the forward directions of the diodes of the memory cells are alternately opposite to each other, in which the forward direction of the diode of each memory cell is opposite to the forward direction of the diode of an adjacent memory cell sharing the electrode, and identical to the forward direction of the diode of the adjacent memory cell which is arranged in the diagonal direction without sharing the electrode. Also, since the leakage of electric current is remarkably diminished, the read margin of the memory device having the crossbar array structure increases, so the number of memory cells per a unit area may be increased, thereby improving the degree of integration.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device having a crossbar array structure and a manufacturing method thereof,

The present invention relates to a memory device, and more particularly to a crossbar-structured memory device.

Recently, nonvolatile memory has been studied to meet the requirements of high integration, low power consumption, fast operation speed and to overcome the scale limit of devices such as conventional flash memory. In particular, Resistance Random Access Memory (ReRAM) devices have advantages such as simple device structure and excellent scalability, and are becoming popular as next generation nonvolatile memory devices. ReRAM is a memory device that uses a characteristic that a resistance change material changes its resistance value according to a voltage condition. Unlike other next generation nonvolatile memory devices, since a memory structure can be operated by a simple structure of a metal-resistance change layer-metal, The process is simple and the process cost is low.

1A is a cross-sectional view showing the structure of a conventional ReRAM. Referring to FIG. 1A, the conventional ReRAM includes a lower electrode 110, a resistance-variable layer 120, and an upper electrode 130. In general, the lower electrode 110 and the upper electrode 130 are made of a conductive material, and the resistance-variable layer 120 is made of a material exhibiting a resistance change characteristic. As the conductive material, a metal material is mainly used. As the resistance change layer, a metal oxide or perovskite (SrTiO 3) is used. When a voltage of an appropriate condition is applied between the upper electrode 130 and the lower electrode 110, the resistance variable layer 120 has a different resistance value, that is, a low resistance state (LRS) And a high resistance state (HRS) state. The memory device operates as a memory device by distinguishing the two states.

When the ReRAM is implemented as an array, a crossbar-type array structure as shown in FIG. 1B is used to increase the degree of integration. The crossbar array has a structure in which a plurality of resistance-variable layers 120 are inserted between a plurality of upper electrodes 130 orthogonal to each other and a plurality of lower electrodes 110, and the structure is very simple and easy to be stacked in layers It is a very advantageous structure in an integrated circuit, and ReRAM is considered to be the most suitable memory element for such a structure.

In the crossbar array configuration of ReRAM, as shown in Fig. 1B, in order to distinguish a state in which the resistance of data stored in the memory cell to be read is large or a state in which the resistance is small, A read voltage Vread is applied to the upper electrode 130 and the lower electrode 110 to distinguish between when the current flows well and when the current does not flow.

However, in the case of the crossbar array of ReRAM, as shown in FIG. 1B, if the data of the selected cell (selected memory cell) to be read has a high resistance state (HRS), the current should not flow well, A path through which the current flows through the cells is formed to flow a current, thereby causing a problem that the stored data can not be read correctly.

Since the sine-pass current is generated through the unselected memory cells, distorted signals are generated in the memory device as a whole. In order to solve such a problem, However, this method can also reduce the leakage current, but it can not completely remove the diode.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device of a crossbar array structure capable of minimizing a leakage current generated in memory cells other than a memory cell selected in a memory device of a crossbar array structure and a method of manufacturing the same.

A memory device of a crossbar array structure according to a preferred embodiment of the present invention for solving the above problems is provided with a first electrode formed on a substrate and a second electrode crossing the first electrode, A plurality of resistance change memory cells each including a memory portion having a resistance varying in accordance with a voltage applied between two electrodes and a diode arranged between the first electrode and the second electrode and controlling a current flow Wherein the forward direction of the diode is arranged opposite to the forward direction of the diodes of the adjacent resistance change memory cells.

Further, in the memory device of the crossbar array structure, the forward direction of the diodes of the resistance change memory cells sharing the first electrode and the second electrode among the plurality of adjacent resistance change memory cells is preferably opposite to each other.

In the memory device of the crossbar array structure, the forward direction of the diodes of the resistance-change memory cells that do not share the first electrode and the second electrode among the plurality of adjacent resistance-change memory cells is preferably equal to each other .

In the memory device of the crossbar array structure, the diode may include a p-type semiconductor layer having one surface (first contact surface) in contact with the memory portion and an n-type semiconductor layer in contact with the opposite surface of the first contact surface .

In the memory device of the crossbar array structure, a plurality of the first electrodes are formed on the substrate in parallel to each other, a plurality of the resistance-change memory cells are formed on the first electrode so as to be spaced from each other, Type semiconductor layer is formed in contact with the resistance-change memory cell in a direction crossing the first electrode, and the plurality of resistance-change memory cells are arranged in the memory cell region along the first electrode and the second electrode, And the first electrode and the second electrode are alternately formed in contact with the first electrode and the second electrode.

The memory device of the crossbar array structure may further include a drive circuit for applying the program voltage and the read voltage to the first electrode or the second electrode in accordance with the forward direction of the diode included in the selected resistance change memory cell .

According to another aspect of the present invention, there is provided a memory device of a crossbar array structure, including a first electrode formed of a plurality of columns, a second electrode formed of a plurality of columns so as to intersect the first electrode, ; And a memory unit formed between the first electrode and the second electrode and having a resistance varied according to a voltage applied between the first electrode and the second electrode, and a memory unit disposed between the first electrode and the second electrode, And a plurality of resistance change memory cells including a diode for controlling the flow of current, wherein the first electrode and the second electrode are alternately formed on the substrate and the memory cell for each resistance change memory cell .

In the memory device of the crossbar array structure, all of the diodes included in each resistance-change memory cell may be formed in the same manner so that the direction toward the substrate is the forward direction or the reverse direction.

Further, the memory device of the crossbar array structure is characterized in that the forward direction of the diodes of the resistance-change memory cells sharing the first electrode and the second electrode among the plurality of adjacent ones of the resistance-change memory cells is a direction from the first electrode to the second electrode Direction are preferably opposite to each other.

In the memory device of the crossbar array structure, the forward direction of the diodes of the resistance-change memory cells in the diagonal direction, which do not share the first electrode and the second electrode among the plurality of adjacent resistance-change memory cells, It is preferable that they are equal to each other with respect to the direction toward the two electrodes.

The memory device of the crossbar array structure may further include a drive circuit for applying the program voltage and the read voltage to the first electrode or the second electrode in accordance with the forward direction of the diode included in the selected resistance change memory cell .

According to another aspect of the present invention, there is provided a method of forming a memory device of a crossbar array structure, including: (a) forming a first electrode on a substrate in a plurality of parallel rows; (b) forming a resistance change memory cell including a memory unit and a diode on the plurality of first electrode columns, wherein the resistance change memory cell is formed so as to have the same structure as the resistance change memory cells located on the diagonal line; And (c) forming a second electrode in a plurality of parallel rows in a direction crossing the first electrode on the resistance-change memory cells.

In the step (b) of the method for forming a memory device of the crossbar array structure, the forward direction of the diodes included in the resistance-change memory cells located on the diagonal line are the same, and the first electrode and the second electrode are shared And the forward direction of the diodes included in the adjacent resistance change memory cells may be opposite to each other.

The step (b) of the method for forming a memory device of the crossbar array structure may further include the steps of: (b1) forming odd-numbered (or even-numbered) Forming an even-numbered (or odd-numbered) resistance-change memory cell of a cell and an even-numbered (or odd-numbered) column with the same forward direction of the diode; And (b2) an odd-numbered (or even-numbered) resistance of the odd-numbered (or odd-numbered) Forming the change memory cell so that the forward direction of the diode is opposite to the forward direction of the diode included in the resistance change memory cells formed in the step (b1).

According to another aspect of the present invention, there is provided a method of forming a memory device of a crossbar array structure, comprising: (a) etching an insulating substrate to form a first electrode composed of a plurality of rows parallel to each other; Forming an area in the substrate where a second electrode, which is composed of a plurality of rows parallel to each other in a direction intersecting with the first electrode, is to be formed; (b) depositing an electrode forming material on the substrate to form a first electrode and a second electrode in regions formed in the substrate; (c) forming a resistance change memory cell on the first electrode and the second electrode in the same structure; And (d) depositing an electrode forming material on the resistance change memory cell to form a first electrode and a second electrode on the resistance change memory cell, wherein the first electrode and the second electrode are formed on the resistance change memory cell, And connecting a first electrode and connecting a second electrode formed on the resistance-change memory cell and a second electrode formed inside the substrate.

In addition, in the step (c) of the method for forming a memory device of the crossbar array structure, a memory portion and a diode formed of a resistance change material are formed on the first electrode and the second electrode, The forward direction of the diodes may be the same.

In the step (d) of the method for forming a memory device of the crossbar array structure, the first electrode formed on the resistance change memory cell is connected to the first electrode formed on the substrate below the adjacent resistance change memory cell, The electrode forming material may be deposited such that the second electrode formed on the cell is connected to the second electrode formed on the substrate under the adjacent resistance change memory cell.

The present invention is configured such that a diode is included in a plurality of resistance change memory cells included in a crossbar array structure, and the forward direction of diodes included in the memory cells sharing the electrodes are alternately set to be opposite to each other, The leakage current is greatly reduced by forming the forward direction of the diode to be opposite to the forward direction of the diodes of adjacent memory cells sharing the electrode and equal to the forward direction of the diodes of adjacent memory cells in the diagonal direction that do not share the electrode .

In addition, by greatly reducing the leakage current, it is possible to include more memory cells per unit area by increasing the read margin of the memory device of the crossbar array structure, thereby improving the integration degree.

1A is a diagram illustrating a resistance change memory structure according to the prior art.
1B is a view for explaining a structure and a problem of a conventional crossbar array memory device.
FIGS. 2A and 2B are diagrams for explaining a configuration of a crossbar-structured memory device including a resistance-change memory cell according to a first preferred embodiment of the present invention.
Fig. 3 is a diagram showing an overall configuration of a memory device of a crossbar array structure according to a first preferred embodiment of the present invention.
4 is a diagram showing an equivalent circuit of a memory device of a crossbar array structure according to the present invention and a conventional technique.
FIGS. 5A to 5D are diagrams for explaining a leakage of a memory device of a crossbar array structure including a resistance change memory cell according to a first preferred embodiment of the present invention and a memory device of a crossbar array structure according to the related art The current path is represented by an equivalent circuit and compared.
6A to 6D are diagrams showing a process of forming a memory device of a crossbar array structure according to a first preferred embodiment of the present invention.
FIG. 7A is a diagram showing the entire structure of a memory device of a crossbar array structure according to a second preferred embodiment of the present invention, and FIG. 7B is an enlarged view of a partial area shown in FIG. 7A.
8A and 8B are views for explaining a method of manufacturing a memory device of a crossbar array structure according to a second preferred embodiment of the present invention.
FIG. 9 is a plan view showing a manufacturing process of a memory device of a crossbar array structure according to a second preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2A and 2B are diagrams for explaining a configuration of a memory device of a crossbar structure including a resistance change memory cell according to a first preferred embodiment of the present invention, wherein FIG. 2A is a diagram showing the structure of a crossbar array , And Fig. 2B is an enlarged view of a portion shown in Fig. 2A.

2A and 2B, a memory device of a crossbar structure according to a first preferred embodiment of the present invention includes a plurality of first electrodes 210-1 to 210-n formed on a substrate, A plurality of resistance change memory cells 230 formed to be spaced apart from each other at regular intervals on the first electrodes 210-1 to 210-n, a plurality of resistance change memory cells 230-1 to 210- 230 formed on the second electrodes 220-1 to 220-n.

The first electrodes 210-1 to 210-n are formed of a plurality of columns formed on the substrate, which are generally used for forming electrodes, such as Pt, and are arranged parallel to each other at regular intervals.

The second electrodes 220-1 to 220-n may be formed of the same material as that of the first electrodes 210-1 to 210-n or other materials generally used for forming the electrodes, A plurality of columns are arranged in parallel to each other in a direction crossing the resistance change memory cells 230 formed on the first electrodes 210-1 to 210-n, .

In the preferred embodiment of the present invention, the structures of the first electrodes 210-1 to 210-n and the second electrodes 220-1 to 220-n are the same as those of the conventional crossbar array structure, and thus a detailed description thereof will be omitted.

The plurality of resistance-change memory cells 230 formed on the first electrodes 210-1 to 210-n and having the upper portions thereof contacting the second electrodes 220-1 to 220-n are electrically connected to the first electrodes 210- A memory unit 231 and a first electrode 210-1 to 210-n having a resistance varying according to a voltage applied between the first electrodes 210-1 to 210-n and the second electrodes 220-1 to 220- And a diode 232 disposed between the second electrodes 220-1 to 220-n for controlling the flow of current.

At this time, the resistance change memory cells 230 (n) sharing the first electrodes 210-1 to 210-n and the second electrodes 220-1 to 220-n among the plurality of adjacent resistance change memory cells 230 The first electrodes 210-1 and 210-2 to 210-n and the second electrode 220-1 of the plurality of resistance change memory cells 230 adjacent to each other are connected to each other, The forward direction of the diodes 232 of the diagonal direction resistance-change memory cells 230 that do not share the bit lines 220-n are formed to be equal to each other.

For reference, the meaning of "adjacent memory cells" in the present invention means eight memory cells 230 located in four directions and diagonal directions with respect to a specific memory cell 230.

Referring to FIG. 2B, for convenience of description, four memory cells R 1 to R 4 are shown among the plurality of resistance-change memory cells 230.

A plurality of first electrodes 210-1, 210-2 ... 210-n are formed on the substrate in parallel with each other, and a plurality of first electrodes 210-1, 210-2 ... 210- The two electrodes 220-1, 220-2 ... 220-n are formed in parallel with each other. The first electrodes 210-1 to 210-n and the second electrodes 220-1 to 220-n and each resistance change memory cell 230 is composed of a memory unit 231 and a diode 232. The resistance change memory cell 230 includes a memory unit 231 and a diode 232. [

Referring to the resistance change memory cell R4, the resistance change memory cell R4 has a pn junction diode 232 formed on the first electrode 210-1, and a memory unit 231 formed of a resistance change material thereon And the upper surface of the memory unit 231 is in contact with the second electrode 220-1. The pn junction diode 232 is formed of a p-type semiconductor layer 232-1 and an n-type semiconductor layer 232-2. An n-type semiconductor layer 232-2 is formed on the first electrode 210-1. A p-type semiconductor layer 232-1 is formed on the p-type semiconductor layer 232-1, and a memory portion 231 is formed on the p-type semiconductor layer 232-2. Therefore, the forward direction of the diode 232 included in R4 is the direction toward the substrate, that is, the direction from the second electrode 220-1 toward the first electrode 210-1.

Meanwhile, in the resistance change memory cell R 1 sharing the fourth electrode and the second electrode 220 - 1, the memory unit 231 is formed on the first electrode 210 - 1, the pn junction diode 232 Is formed. At this time, a p-type semiconductor layer 232-1 is formed on the memory portion 231, and an n-type semiconductor layer 232-2 is formed on the memory portion 231 to be in contact with the second electrode 220-1. Therefore, the forward direction of the diode 232 of R1 becomes upward from the substrate, that is, from the first electrode 210-2 toward the second electrode 220-1, and the diode 232 included in the adjacent R4 And the forward direction of the diode 232 is set in the opposite direction.

Similarly, in the resistance change memory cell R 3 sharing R 4 and the first electrode 210 - 1, a memory unit 231 is formed on the first electrode 210 - 1, and a pn junction diode 232 Is formed. At this time, the p-type semiconductor layer 232-1 is formed on the memory portion 231, and the n-type semiconductor layer 232-2 is formed thereon to be in contact with the second electrode 220-2. As shown in FIG. Therefore, the forward direction of the diode 232 of R3 becomes upward from the substrate, that is, from the first electrode 210-1 toward the second electrode 220-2, and the diode 232 included in the adjacent R4 And the forward direction of the diode 232 is set in the same direction as that of the diagonally adjacent line R1.

On the other hand, if the resistance change memory cell R2 adjacent to the diagonally opposite R4 not sharing the first electrode 210-1 and the second electrode 220-1 is referred to as R2, the pn junction is formed on the first electrode 210-2. And a memory portion 231 formed of a resistance change material is formed on the diode portion 232. An upper surface of the memory portion 231 is in contact with the second electrode 220-2. The pn junction diode 232 is formed of a p-type semiconductor layer 232-1 and an n-type semiconductor layer 232-2. An n-type semiconductor layer 232-2 is formed on the first electrode 210-2. A p-type semiconductor layer 232-1 is formed on the p-type semiconductor layer 232-1, and a memory portion 231 is formed on the p-type semiconductor layer 232-2. Therefore, R2 has the same structure as R4, and the forward direction of the diode 232 included in R2 has the same direction as the forward direction of the diode included in R4.

In summary, the memory device of the crossbar structure including the resistance change memory cell according to the first preferred embodiment of the present invention has a structure in which the forward direction of the diodes is set opposite to each other between the adjacent resistance change memory cells sharing the first electrode and the second electrode And the forward direction of the diodes is set in the same direction between the diagonally adjacent resistance change memory cells that do not share the first and second electrodes.

In other words, the resistance change memory cells 230 formed on the same first electrodes 210-1 and 210-2 to 210-n are alternately formed such that the forward direction of the diodes 232 is opposite to each other, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-2, 220-1, 220-2, 220-2, and 220-n are also alternately formed. As a result, the forward directions of the diodes 232 of the resistance-change memory cells 230 in the diagonal direction with respect to each other are formed to be equal to each other.

FIG. 3 is a diagram showing the overall configuration of a memory device of a crossbar array structure according to a first preferred embodiment of the present invention.

Referring to FIG. 3, the memory device of the crossbar array structure according to the first preferred embodiment of the present invention includes a crossbar array structure including the resistance change memory cell 230 described above with reference to FIGS. 2A and 2B, And a driver circuit 300 for driving the resistance change memory cell 230 of FIG.

As described above, since the diodes 232 included in the resistance change memory cell 230 of the present invention are not the same in the forward direction, the driver circuit 300 is provided for the diode 232 included in each memory cell 230 A program voltage or a read voltage should be applied to the first electrodes 210-1, 210-2 to 210-n or the second electrodes 220-1, 220-2, ..., 220-n according to the forward direction.

For example, since the forward direction of the diode 232 is from the first electrodes 210-2 and 210-1 to the second electrodes 220-1 and 220-2, the resistance change memory cells R1 and R3 are connected to the driver circuit 300 applies a program voltage or a read voltage through the first electrodes 210-1 and 210-2.

On the other hand, since the resistance change memory cells R2 and R4 have the forward direction of the diode 232 from the second electrodes 220-2 and 220-1 toward the first electrodes 210-2 and 210-1, The controller 300 applies a program voltage or a read voltage through the second electrodes 220-2 and 220-1.

4 is a diagram showing an equivalent circuit of a memory device of a crossbar array structure according to the present invention and a conventional technique.

A memory device of a crossbar array structure according to the related art is formed such that all the diodes 232 included in each resistance-change memory cell 230 have the same forward direction.

Therefore, assuming that a leakage current occurs in a path as shown in FIG. 1B, in the prior art, as shown in FIG. 4A, the leakage current flows through two forward diodes and one reverse diode Flow.

On the other hand, in the memory device of the crossbar array structure according to the first embodiment of the present invention, when a leakage current flows in the same path as in Fig. 1B, as shown in Fig. 4B, And the amount of the leakage current is remarkably reduced as compared with the prior art.

Meanwhile, the memory device of the crossbar array structure according to the preferred embodiment of the present invention can secure a larger read margin as compared with the memory device of the crossbar array structure of the related art, and can increase the integration density per unit area have.

FIGS. 5A to 5D are diagrams for explaining a leakage of a memory device of a crossbar array structure including a resistance change memory cell according to a first preferred embodiment of the present invention and a memory device of a crossbar array structure according to the related art The current path is represented by an equivalent circuit and compared.

(1) A. Flocke and TG Noll, "Fundamental analysis of resistive nanocrossbars for the use in hybrid nano / CMOS-memory," Proc. 33rd ESSCIRC , 2007, pp. 328-331. (2) Zi-Jheng Liu, A crossbar array including a resistance change memory cell through a ZnO-based one diode-one resistor device structure for crossbar memory applications, APPLIED PHYSICS LETTERS 100, 153503 (2012), Jon-Yiew Gan and Tri-Rung Yew It is a well-known fact that the equivalent circuit of the memory device of the structure can be expressed as shown in Figs. 5A and 5B.

In the same manner as shown in Figs. 5A and 5B, an equivalent circuit of a region corresponding to the region shown in Fig. 2B among the prior art crossbar arrays in which the diodes of all the memory cells have the same forward direction is shown in Fig. An equivalent circuit of the memory device of the crossbar array structure according to the first preferred embodiment of the present invention shown in Fig. 2B is shown in Fig. 5D.

In general, the read margin is defined by the following equation (1).

In Equation 1 V _{out (LRS)} and V _{out (HRS)} is the same as the voltage (V _pu) distribution of the series resistance, it may be summarized as shown in Equation 2 below. (R1, R2, R3 are defined as R ^sneak )

5C, the resistance value of R1 and R3 whose direction of the diode 232 is forward is significantly smaller than that of the diode 232 whose direction is opposite to that of the diode 232. Therefore, And can be summarized as Equation (3) below.

5D, since the direction of the diode 232 is opposite to the direction of the diode 232 in the case of R1, R2, and R3 of the present invention, the resistance value is large and can not be ignored. Therefore, 2 < / RTI >

Generally, when calculating the read margin, R _pu is set to an R _LRS value, and the following exemplary numerical values are substituted into Equation 2 and Equation 3 and computed by computer simulation, the read margin (proposed CBA) Is larger than the conventional readout margin (conventional CBA), which can be obtained as a graph as shown in FIG. 5E.

[Example numerical value]

Current _HRS @Vread: 10 ^-7 A

Current _LRS @Vread: 10 ^-5 A

Current @ -Vread: 10 ^-8 A

Read Voltage: 0.1 V

As shown in FIG. 5E, it can be seen that the present invention achieves a much higher degree of integration than the prior art, based on a read margin of 10%.

The memory device of the crossbar array structure according to the first preferred embodiment of the present invention has been described.

6A to 6D are views showing a process of forming a memory device of a crossbar array structure according to a first preferred embodiment of the present invention, wherein FIGS. 6A to 6C are sectional views taken along the line aa in FIG. 2A, (b) is a cross-sectional view of bb.

Referring to FIGS. 6A to 6D, a substrate 600 on which a memory device of a crossbar array structure is to be formed is first prepared (1 in FIG. 6A). At this time, the substrate uses a general insulating substrate such as SiO2.

Next, a photoresist pattern (PR) 610 is formed on the insulating substrate 600 except for the region where the first electrode 210 is to be formed (FIG. 6A, 2), and dry etching is performed to form the first Thereby securing a region for forming the electrode 210 (3 & cir & in Fig. 6A).

Thereafter, a metal is deposited on the substrate to form the first electrode 210 (Fig. 6A), and the PR pattern 610 that has been formed is removed (Fig. 6A). At this time, the first electrode 210 is formed on the substrate in a plurality of rows parallel to each other. The plan view of the substrate after the step < 5 > of Fig. 6A is performed is as shown in Fig. 6D (a).

Next, a photoresist pattern (PR) 620 is formed on the first electrode 210 except the region where the odd-numbered (or even-numbered) resistance-change memory cell 230 is to be formed ) And a diode 232 (including a p-type semiconductor layer 232-1 and an n-type semiconductor layer 232-2) are formed on the PR pattern 620 by vapor deposition, The pattern 620 and the memory cell structures formed on the PR pattern are removed (⑦ in FIG. 6B). Since the memory cells 230 formed at this time have the same configuration, the forward direction of the diodes 232 is formed identically.

If an odd-numbered resistance-change memory cell is formed on a specific first electrode 210, the first electrode 210 of the adjacent column (i.e., the first electrode formed on both sides of the specific first electrode) Note that the cell is formed. That is, the resistance change memory cells adjacent to each other in the diagonal direction are all formed at one time. 6B is a plan view of the substrate after step 7 in FIG. 6B is performed. (The memory cell formed in step 7 in FIG. 6B is denoted by "F").

Referring again to FIG. 6B, after the odd-numbered (or even-numbered) resistance-change memory cells 230 are formed, except for the region for forming the even-numbered (or odd-numbered) resistance-change memory cells 230, (6) (Fig. 6 (8)).

Thereafter, the memory unit 231 and the diode 232 are deposited so that the resistance change memory cell 230 is formed in a structure opposite to the structure of the odd-numbered (or even-numbered) memory cell 230, Odd-numbered) memory cells 230 and the PR pattern 630 is removed (9) of FIG. 6B). Therefore, the forward direction of the diode 232 included in the even-numbered (or odd-numbered) memory cell 230 is formed to be opposite to the forward direction of the diode 232 formed in step 7 of FIG. 6B. At this time, odd-numbered (or even-numbered) resistance change memory cells of adjacent first electrode 210 columns are also formed. The planar view of the substrate after the step (9) of FIG. 6B is performed is as shown in (c) of FIG. 6D (the memory cell formed in step 9 in FIG. 6B is indicated by "R").

Then, a photoresist pattern (PR pattern) 640 is formed in the remaining region except the upper region of the memory cell 230 in which the second electrode 220 is to be formed to form the second electrode 220 6), a metal is deposited thereon to form a second electrode 220, and then the PR pattern 640 is removed to complete a cross bar array structure (11) in FIG. 6C). The top view of the substrate after step (11) of Fig. 6 (b) is performed is as shown in Fig. 6 (d).

The memory device of the crossbar array structure according to the first preferred embodiment of the present invention and the manufacturing method thereof have been described.

Hereinafter, a memory device of a crossbar array structure according to a second preferred embodiment of the present invention and a method of manufacturing the same will be described.

FIG. 7A is a diagram showing the entire structure of a memory device of a crossbar array structure according to a second preferred embodiment of the present invention, and FIG. 7B is an enlarged view of a partial area shown in FIG. 7A.

In the first embodiment, the first electrode 210 is formed on the substrate and the second electrode 220 is formed on the memory cell 230. However, in the first embodiment, In the second embodiment, the first electrodes 710-1 to 710-n and the second electrodes 720-1 to 720-n are alternately arranged to contact the substrate in any one of the memory cells, Is formed on the cell, then on the substrate, and then on the memory cell.

7B, in the case of the resistance change memory cell 730 R4, the first electrode 710-1 is formed on the substrate, and the resistance change memory cell 730-1 is formed on the first electrode 710-1. And a second electrode 720-1 is formed on the memory cell 730. [

In addition, the resistance change memory cells R1 and R3 sharing the first electrode 710-1 and the second electrode 720-1 with the fourth electrode are formed on the substrate with the second electrodes 720-1 and 720-2, The resistance change memory cell 730 is formed on the second electrodes 720-1 and 720-2 and the first electrodes 710-2 and 710-1 are formed on the memory cell 730. [

In the case of the resistance-change memory cell R2 diagonally adjacent to the memory cell R4, the first electrode 710-2 is formed on the substrate, the memory cell 730 is formed on the first electrode 710-2, And a second electrode 720-2 is formed on the memory cell 730.

In the case of the resistance change memory cell 730 shown in FIGS. 7A and 7B, the first electrodes 710-1 and 710-2 to 710-n or the second electrodes 720-1 and 720- 2,..., 720-n, and a diode 732 is formed on the memory portion 731. In this case, the forward direction of the diode 732 may be formed in any direction because all the cells 730 are the same.

As described above, in the case of the second embodiment, the positions of the first electrodes 710-1, 710-2 to 710-n and the second electrodes 720-1, 720-2, And the structure of the memory cell 730, that is, the lamination structure of the memory portion 731 and the diode 732, is the same for all the memory cells 730. [ As a result, if the forward direction of the diode 732 is viewed on the basis of the first electrodes 710-1 and 710-2 to 710-n and the second electrodes 720-1, 720-2, 720-n) sharing the first electrodes 710-1, 710-2 to 710-n and the second electrodes 720-1, 720-2, ..., 720-n in the same manner as in the first embodiment 730 are opposite to each other, and the forward directions of adjacent memory cells 730 in the diagonal direction are equal to each other.

Accordingly, the positions of the first electrodes 710-1 and 710-2 to 710-n and the second electrodes 720-1, 720-2, and 720-n are alternately set for each memory cell 730 3 to 5E are applied to the second embodiment in the same manner, except that they are changed. Accordingly, even in the case of the second embodiment, the first electrodes 710-1, 710-2 to 710-n or the second electrodes 720-1, 720-2, ..., 720-n are arranged along the memory cell 730, And a driver circuit (300) for selectively applying a program voltage and a read voltage.

8A and 8B are views for explaining a method of manufacturing a memory device of a crossbar array structure according to a second preferred embodiment of the present invention.

The second electrodes 720-1, 720-2, ..., 720-n may have a cross-sectional structure cut in a direction parallel to the first electrodes 710-1, 710-2 ~ 710-n, Sectional views of the first electrodes 710-1 and 710-2 to 710-n are cut with reference to FIGS. 8A and 8B. FIG.

First, a substrate 800 on which a memory device of a crossbar array structure is to be formed is prepared (1 & cir & At this time, the substrate uses a general insulating substrate such as SiO2.

Next, a space for forming electrodes is formed by dry etching the insulating substrate 800 after the PR pattern 810 is formed (② in FIG. 8A) except for the space where the electrodes are formed on the substrate 800 8A). In this case, the region (the first electrode region 820 in this example) where the electrode is to be formed on the substrate in the longitudinal direction of the electrode is formed such that the length of the region is long and the electrode is formed on the substrate in the direction crossing the longitudinal direction of the electrode The region to be formed (the second electrode region 830 in this example) forms a space with a short width of the region.

8A). Then, the PR pattern 810 and the metal layer thereon are removed (Fig. 8A). Then, a metal is deposited to form a first electrode 710 and a second electrode 720 formed on the substrate ⑤) of. A plan view of the substrate on which the step (5) of FIG. 8A is completed is as shown in FIG. 9 (a).

Next, a PR pattern 840 is formed in the remaining region except the region where the memory cell 730 is to be formed ((6) in FIG. 8B), and a memory portion 731 is formed thereon with a resistance change material, And a diode 732 are successively laminated, and the resistance change memory cell 730 is formed by removing the PR pattern 840 ((7) in FIG. 8B). At this time, the order of forming the memory portion 731 and the diode 732 may be reversed. The top view of the substrate on which step (7) in FIG. 8 (b) is completed is as shown in FIG. 9 (b).

Then, a PR pattern 850 is formed around the memory cell 730 formed on the first electrode 710 formed in the lengthwise direction among the electrodes formed on the substrate, a metal is deposited on the PR pattern 850, After completing the electrode (the first electrode 710 in this example) and the electrode (the second electrode 720 in this example) formed in the longitudinal direction on top of the memory device of the array structure, the PR pattern 850 (9 in Fig. 8B). A top view of the finally formed crossbar array structure is shown in Fig. 9 (c).

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

210, 210-1, 210-2, 210-n, 710, 710-1, 710-2, 710-
220, 220-1, 220-2, 220-n, 720, 720-1, 720-2, 720-
230, and 730: resistance change memory cell
231, 731:
232, 732: Diode
232-1: p-type semiconductor layer
232-2: n-type semiconductor layer
300: Driver circuit

Claims (17)

A memory device comprising: a memory unit formed between a first electrode formed of a plurality of columns on a substrate and a second electrode formed of a plurality of columns intersecting the first electrode, the resistance of which changes according to a voltage applied between the first electrode and the second electrode; , And
And a plurality of resistance change memory cells disposed between the first electrode and the second electrode and including a diode for controlling the flow of current,
Wherein the forward direction of the diodes included in each of the resistance change memory cells is opposite to the forward direction of some of the diodes included in the adjacent resistance change memory cells and is equal to the forward direction of the other diodes. Structure memory device. The method according to claim 1,
Wherein the forward direction of the resistive memory cells sharing the first electrode and the diodes of the resistance-change memory cells sharing the second electrode among the plurality of adjacent resistance-change memory cells are opposite to each other, Device. The method according to claim 1,
Wherein the forward direction of the diodes of the resistance change memory cells in the diagonal direction which do not share the first electrode and the second electrode among the plurality of adjacent resistance change memory cells are equal to each other. 2. The device of claim 1,
Type semiconductor layer in contact with one surface (first contact surface) of the memory section and an n-type semiconductor layer in contact with the opposite surface of the first contact surface. 5. The method of claim 4,
Wherein a plurality of the first electrodes are formed on the substrate in parallel with each other,
A plurality of resistance change memory cells are formed on the first electrode so as to be spaced apart from each other,
The second electrode is formed in contact with the resistance change memory cell in a direction crossing the first electrode,
Wherein the plurality of resistance change memory cells are formed so that the memory portion and the n-type semiconductor layer alternately contact the first electrode and the second electrode along the first electrode and the second electrode. Memory device in an array structure. 6. The method according to any one of claims 1 to 5,
And a drive circuit for applying a program voltage and a read voltage to the first electrode or the second electrode in accordance with the forward direction of the diode included in the selected resistance change memory cell.
A first electrode formed of a plurality of columns and a second electrode formed of a plurality of columns so as to intersect the first electrode; And
A memory unit formed between the first electrode and the second electrode and having a resistance changed according to a voltage applied between the first electrode and the second electrode,
And a plurality of resistance change memory cells disposed between the first electrode and the second electrode and including a diode for controlling the flow of current,
Wherein the first electrode and the second electrode are alternately formed on the substrate and the memory cell for each resistance-change memory cell. 8. The method of claim 7,
Wherein all of the diodes included in each resistance-change memory cell are formed identically so that a direction toward the substrate is a forward direction or a reverse direction. 8. The method of claim 7,
The forward direction of the resistive memory cells sharing the first electrode and the diodes of the resistance-change memory cells sharing the second electrode among a plurality of adjacent ones of the plurality of resistance- Are opposite to each other in the crossbar array structure. 8. The method of claim 7,
The forward direction of the diodes of the resistance change memory cells in the diagonal direction which do not share the first electrode and the second electrode among the plurality of adjacent resistance change memory cells are the same with respect to the direction from the first electrode to the second electrode A memory device having a crossbar array structure. 11. The method according to any one of claims 7 to 10,
And a drive circuit for applying a program voltage and a read voltage to the first electrode or the second electrode in accordance with a forward direction based on a direction from the first electrode to the second electrode of the diode included in the selected resistance change memory cell The memory device comprising: a crossbar array;
delete A method of forming a memory device of a crossbar array structure,
(a) forming a first electrode in a plurality of parallel rows on a substrate;
(b) forming a resistance change memory cell including a memory unit and a diode on the plurality of first electrode columns, wherein the resistance change memory cell is formed so as to have the same structure as the resistance change memory cells located on the diagonal line; And
(c) forming a second electrode in a plurality of parallel rows in a direction crossing the first electrode on the resistance-change memory cells,
The step (b)
The forward direction of the diodes included in the diagonal resistance-change memory cells are equal to each other. The diodes included in the adjacent resistance-change memory cells sharing the first electrode and the diodes included in the adjacent resistance- And forming the resistance change memory cells such that the forward directions are opposite to each other. 14. The method of claim 13, wherein step (b)
(or odd-numbered) resistance change memory cells of odd-numbered (or even-numbered) resistance-change memory cells and odd-numbered (or odd-numbered) Forming memory cells with the same forward direction of the diodes; And
(or an odd-numbered) resistance change memory cell of odd-numbered (or odd-numbered) resistance change memory cells of odd-numbered (or even-numbered) Forming a memory cell such that the forward direction of the diode is opposite to the forward direction of the diode included in the resistance change memory cells formed in the step (b1).
A method of forming a memory device of a crossbar array structure,
(a) etching an insulating substrate to form a region in which a first electrode composed of a plurality of rows parallel to each other is to be formed and a region in which a second electrode composed of a plurality of rows parallel to each other in a direction intersecting with the first electrode is to be formed Forming a substrate;
(b) depositing an electrode forming material on the substrate to form a first electrode and a second electrode in regions formed in the substrate;
(c) forming a resistance change memory cell on the first electrode and the second electrode in the same structure; And
(d) depositing an electrode forming material on the resistance change memory cell to form a first electrode and a second electrode on the resistance change memory cell, wherein the first electrode and the second electrode are formed on the resistance change memory cell, And connecting a second electrode formed on the resistance change memory cell and a second electrode formed inside the substrate. 16. The method of claim 15, wherein step (c)
Wherein a memory portion and a diode are formed on the first electrode and the second electrode, the diode portion being formed of a resistance change material, and the diode is formed to have the same forward direction with respect to the substrate. 16. The method of claim 15, wherein step (d)
The first electrode formed on the resistance change memory cell is connected to the first electrode formed on the substrate under the adjacent resistance change memory cell,
And depositing the electrode forming material such that the second electrode formed on the resistance change memory cell is connected to the second electrode formed on the substrate below the adjacent resistance change memory cell.

Images