KR101639943B1 - Shared memory control method for facilitating shared memory of general purpose graphic processor as cache and general purpose graphic processor using same - Google Patents

Abstract

A general purpose graphic processor according to embodiments of the present invention is a general purpose graphic processor including a plurality of multi-processors, an L2 cache, and a global GPU memory. Each of the multi-processors may include: a plurality of core units; a configurable memory which is configured by being divided into an L1 cache and a shared memory in a fixed ratio; and a local memory control part which stores a victim memory sacrificed in the L1 cache in the shared memory.

Description

TECHNICAL FIELD [0001] The present invention relates to a shared memory control method for operating a shared memory of a general-purpose graphics processor as a cache, and a general-purpose graphics processor using the shared memory control method. [0002]

The present invention relates to a graphics processor, and more particularly, to a shared memory of a graphics processor.

Recently, a graphics processor has been developed that utilizes the fact that a large portion of known graphics-related operations can be pipelined and can be programmed with repetitive stream operations, Processor (General Purpose Graphic Processor Unit, GPGPU).

It is best suited for graphics applications as well as general purpose graphics processors, but it can also be used for a variety of scientific and engineering applications such as physics effects simulation, computational biology, cryptography, image processing, particle nuclear physics simulation, A tremendous increase in computation speed is expected in the field.

Recently, the general purpose graphics processor stores shared global variables or data used by the stream processor cores to provide shared memory that can be accessed by a plurality of stream processor cores concurrently.

For example, NVIDIA graphics processors physically provide 64 kB of memory, which the programmer can use to store 64 kB of memory at a predetermined rate, for example 48 kB: 16 kB, 32 kB: 32 kB, 16 kB: 48 kB, It can be used as cache or shared memory.

However, there are not many applications that can efficiently utilize shared memory. In fact, among the examples in the software development kit provided by NVIDIA, there are not many examples of utilizing 64 kB memory as shared memory.

This means that it runs at the same speed as the processor core and wastes tens of kB of memory with a short latency comparable to the latency of the main memory.

In other words, there is a need for a method that can be used as a cache at run-time when there is a request from a program, even if the memory capacity is set to hardware shared memory.

SUMMARY OF THE INVENTION The present invention is directed to a shared memory control method for operating a shared memory of a general purpose graphic processor as a cache and a general purpose graphics processor using the same.

A shared memory control method for performing a cache function in a shared memory of a general-purpose graphics processor at a run-time in response to a request from a program, and a general-purpose Graphics processor.

The solution to the problem of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

A general purpose graphics processor according to an aspect of the present invention is a general purpose graphics processor including a plurality of multiprocessors, an L2 cache and a global GPU memory, each of which comprises a plurality of core units, A configurable memory that is divided into shared memory; And a local memory controller for storing a victim block, which is sacrificed in the L1 cache, in the shared memory while the kernel application running on the general-purpose graphics processor does not use the shared memory.

According to one embodiment, the local memory control unit,

And configure the shared memory with the same line size as the mapping scheme of the L1 cache.

According to one embodiment, the local memory control unit

If there is a load / store instruction for data access by one of the core units,

If a cache hit occurs in the L1 cache, data is accessed from the L1 cache and the load / store instruction is terminated.

And to search for the shared memory if a cache miss occurs in the L1 cache.

According to one embodiment, when a cache miss occurs in the L1 cache,

The local memory control unit,

If a line corresponding to a set index of a memory address to be accessed exists in the L1 cache,

If a line corresponding to a set index of a memory address to access is not in the L1 cache, a victim block is selected from the L1 cache according to a predetermined cache replacement policy, and the selected victim block is copied from the L1 cache to the shared memory And may be operable to search for the shared memory.

According to one embodiment, the local memory control unit,

If there is no empty space to copy the victim block to the shared memory, a second sacrifice block is selected from the shared memory according to a predetermined cache replacement policy applied to the shared memory, Copying from the shared memory to the L2 memory or the global GPU memory, and then storing the sacrificial block that is sacrificed from the L1 cache in the space where the secondary sacrificial block was stored.

According to one embodiment, depending on the result of searching the shared memory,

The local memory control unit,

If a cache hit occurs in the shared memory, data is accessed from the shared memory and the load / store instruction is terminated.

If a cache miss occurs in the shared memory, information related to an unprocessed cache miss is stored in a Miss Status Holding Register (MSHR), data is accessed from the L2 cache or the global GPU memory, And to terminate the load / store instruction while updating the unprocessed cache miss information of the MSHR.

In accordance with another aspect of the present invention, a method for controlling a shared memory of a general purpose graphics processor including a plurality of multiprocessors, an L2 cache and a global GPU memory,

Each of the multiprocessors includes a plurality of core units, a configurable memory, and a local memory controller, and when the configurable memory is divided into L1 cache and shared memory at a predetermined ratio,

The local memory control unit,

(a) if there is a load / store instruction for data access by one of the core units, searching the L1 cache;

(b) accessing data in the L1 cache and terminating a load / store instruction when a cache hit occurs in the L1 cache in step (a);

(c) if in step (a) a cache miss occurs in the L1 cache but a line corresponding to a set index of a memory address to access is in the L1 cache, searching for the shared memory;

(d) if in step (a) a cache miss occurs in the L1 cache but there is no line in the L1 cache corresponding to the set index of the memory address to access, in accordance with a predetermined cache replacement policy, Copying the selected victim block from the L1 cache to the shared memory, and searching for the shared memory;

(e) accessing data in the shared memory and terminating a load / store instruction when a cache hit occurs in the shared memory in step (c) or step (d);

(f) if a cache miss occurs in the shared memory in step (c) or step (d), storing information related to an unprocessed cache miss in the MSHR, accessing data in the L2 cache or the global GPU memory, Storing the accessed data in the L1 cache, and terminating the load / store instruction while updating the unprocessed cache miss information.

According to one embodiment, the method for controlling a shared memory of the general-purpose graphics processor is characterized in that prior to step (a)

If the kernel application does not use the shared memory, setting the configurable memory to a maximum configurable size L1 cache and a minimum configurable shared memory size may be included.

According to one embodiment, the step of setting the configurable memory further comprises:

And configuring the shared memory with the same line size as the mapping method of the L1 cache.

According to one embodiment, step (d)

Wherein the local memory control unit selects a second sacrifice block in the shared memory according to a predetermined cache replacement policy applied in the shared memory if there is no empty block to copy the victim block to the shared memory, And copying the secondary victim block from the shared memory to the L2 memory or the global GPU memory and then storing the victim block that is sacrificed from the L1 cache in the space where the secondary victim block was stored have.

According to another aspect of the present invention, a method for controlling a shared memory of a general purpose graphics processor including a plurality of multiprocessors, an L2 cache and a global GPU memory

Each of the multiprocessors includes a plurality of core units, a configurable memory, and a local memory controller, and when the configurable memory is divided into L1 cache and shared memory at a predetermined ratio,

The local memory control unit,

(a ') searching the L1 cache if there is a load / store instruction for data access by one of the core units;

(b ') accessing data in the L1 cache if a cache hit occurs in the L1 cache in step (a');

(c ') if a cache miss occurs in the L1 cache in step (a'), searching for the shared memory; And

(d ') if the cache miss occurs in the shared memory at step (c'), accessing data in the L2 cache or the global GPU memory.

According to the shared memory control method of the present invention and the general-purpose graphics processor using the same, the shared memory of the general-purpose graphics processor can be operated as a cache.

According to the shared memory control method and the general-purpose graphics processor using the shared memory control method of the present invention, it is possible to perform the cache function in the shared memory of the general-purpose graphics processor at runtime even when the program is set as the shared memory, have.

According to the shared memory control method of the present invention and the general-purpose graphics processor using the shared memory, the shared memory of the general-purpose graphics processor is used as an auxiliary cache of the L1 cache at runtime, so that the L1 cache stores a global memory The time for searching can be minimized.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a block diagram illustrating a general purpose graphics processor having a shared memory according to an embodiment of the present invention.
2 is a flowchart illustrating a shared memory control method according to an embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram schematically illustrating a general purpose graphics processor having a shared memory according to an embodiment of the present invention.

1, general purpose graphics processor 10 includes a plurality of multiprocessors 110, an L2 cache 120, a global memory controller 130, a global GPU memory 140, and a thread manager 150 .

The general-purpose graphics processor 10 distributes the received instructions to the respective multiprocessors 110 when the instructions and data are received from the central processor unit (CPU) of the host device (not shown) GPU memory 140, and when the instructions are processed in parallel in the multiprocessors 110 to generate operation results, the generated operation results are merged and sent back to the CPU or the host memory.

To this end, the thread manager 150 distributes the instructions received from the CPU of the host device to the respective multiprocessors 110, and the global memory controller 130 may store the received data in the global GPU memory 140 have. The data stored in global GPU memory 140 may be, for example, texture or polygon data.

Each of the multiprocessors 110 accesses the L2 cache 120 first when it is necessary to load / store data while performing operations according to the distributed instructions, The global GPU memory 140 can access the global GPU memory 140 through the global memory controller 130.

Each of the multiple processors 110 may include a plurality of core units 111, 112 and 113, a configurable memory 114, a texture cache 117 and a local memory controller 118 have.

The core units 111, 112, and 113 process the instructions distributed by the thread management unit 150, respectively.

The local memory control unit 118 loads / stores the data to be processed by the core units 111, 112 and 113 into the configurable memory 114 or the texture cache 117 according to the instructions, For example, in the L2 cache 120 or in the global GPU memory 140, outside the multiprocessor 110, unless it is searched in the texture cache 117 or the texture cache 117.

As described above, the configurable memory 114 can be divided into the L1 cache 115 and the shared memory 116 at a predetermined ratio according to the user setting, the program setting, or the default setting. For example, 64 kB of configurable memory 114 may be set to 16 kB of L1 cache 115 and 48 kB of shared memory 116, or 32 kB of L1 cache 115 and 32 kB of shared memory 116 ) And may be set to a 48 kB L1 cache 115 and a 16 kB shared memory 116. [

If the kernel application to be executed in the general purpose graphics processor 10 does not use the shared memory, the space of the shared memory 116 set to at least 16 kB is wasted.

Accordingly, the local memory control unit 118, when the kernel application does not use the shared memory, sets the configurable memory 114 to the L1 cache 115 of the maximum configurable size and the shared memory 116 of the minimum configurable size ).

Specifically, the local memory control unit 118 analyzes the commands distributed to the multiprocessor 110, or identifies at runtime whether the kernel application uses the shared memory, depending on the state of the variable declared for shared memory usage , The configurable memory 114 can be set at runtime to the L1 cache 115 of the maximum configurable size and the shared memory 116 of the minimum configurable size if the kernel application does not use the shared memory.

In this case, in the shared memory control scheme for the general-purpose graphics processor 10 of the present invention, the local memory control unit 118 is configured to use the set shared memory 116 in the same manner as the L1 cache 115, Is not intended to be used as the L1 cache 115 as a whole.

Also, in the shared memory control scheme for the general-purpose graphics processor 10 of the present invention, the local memory controller 118 does not intend to use the set shared memory 116 as a buffer cache for overcoming the difference in access time.

Rather, in the shared memory control scheme for the general-purpose graphics processor 10 of the present invention, the local memory control unit 118 determines whether the allocated kernel application is to be allocated, even if the executed kernel application often utilizes shared memory, Is intended to utilize the memory space of the shared memory 116 as an auxiliary cache of the L1 cache 115. [

In particular, the local memory control unit 118 stores a victim block that is sacrificed in the L1 cache 115 in the shared memory 116.

To this end, the local memory control unit 118 configures the shared memory 116 in the same mapping scheme as the L1 cache 115. If the L1 cache 115 has a 128-byte line, the L1 cache 115 may be configured as a 4-way 32-bit associative mapping cache when the L1 cache 115 is set to a 16 kB size, Is set to a size of 48 kB, it can be configured as a six-way 64-bit associative mapping cache.

If the kernel application does not utilize the shared memory 116, it is preferable that the L1 cache 115 is set to the maximum size of 48 kB, so that the shared memory 116 has a line size of 128 bytes It can be configured as a four-way 32-bit associative mapping cache.

When there is a load / store instruction for data access by one of the core units 111, 112, and 113, the local memory control unit 118 first searches the L1 cache 115 in the configurable memory 114 . If a cache hit occurs in the L1 cache 115, the data is accessed and the load / store command is terminated.

However, if a cache miss occurs in the L1 cache 115 even though a line corresponding to the set index of the memory address to be accessed is in the L1 cache 115, Lt; / RTI > searches shared memory 116 further.

Specifically, the local memory control unit 118 determines whether the L2 cache 120 is in the LI cache 115 if a line corresponding to the set index of the memory address to be accessed was in the LI cache 115, even if a cache miss occurred in the L1 cache 115. [ The shared memory 116 may be searched.

This is because even if a cache miss occurs in the L1 cache 115 because the local memory controller 118 previously stored in the L1 cache 115 stores only the victimized victim blocks in the shared memory 116, This is because there is a high possibility that other lines (data whose core unit has the same set index as the memory address found in the L1 cache) of the set index are stored in the shared memory 116. [

Here, since the block is a data exchange unit between the L1 cache 115 and the shared memory 116, the size of the block may be equal to the size of the line.

On the other hand, if a cache miss occurs because a line corresponding to a set index of a memory address to be accessed is not in the L1 cache 115, the local memory control unit 118 sets a predetermined cache replacement policy, for example, a Least Recently Used ), Selects a victim block in the L1 cache 115 according to NRU (Not Recently Used) or RRIP (Re-Reference Interval Prediction), and copies the selected victim block from the L1 cache 115 to the shared memory 116 do.

At this time, if there is no empty block in the shared memory 116 to copy the victim block, the local memory controller 118 sets a predetermined cache replacement policy, for example, LRU, NRU, or RRIP applied in the shared memory 116 The secondary victim block is selected from the shared memory 116 and the selected secondary victim block is copied from the shared memory 116 to the L2 memory 120 and then the L1 And may store a victim block that is sacrificed from the cache 115.

The local memory control unit 118 then determines whether or not a cache miss occurs in the L1 cache 115 and also if a line corresponding to the set index of the memory address to access is not in the L1 cache 115 The victimized victim block may still be stored in the shared memory 116, so that the shared memory 116 may be further searched.

The local memory control unit 118 accesses the data and terminates the load / store command if a cache hit occurs in the shared memory 116 as a result of searching the shared memory 116. [

Further, if a cache miss occurs in the shared memory 116, the local memory controller 118 may store information related to an outstanding miss in the miss status holding register (MSHR).

When the unprocessed cache miss information is stored in the MSHR, the local memory control unit 118 stores the unprocessed cache miss information in the lower L2 cache 120 or the global GPU memory 140, which is outside the multiprocessor 110, And accesses the data to correspond to the load / store instruction. The local memory control unit 118 can store the data accessed by the lower memory means in the L1 cache 115 and update the unprocessed cache miss information.

In the conventional cache control technique, when a cache hit occurs in the L1 cache, data access is immediately performed. However, if a cache miss occurs in the L1 cache, the cache miss information is immediately written to the MSHR, It takes time to access the data.

According to the shared memory control technique of the present invention, when a cache hit occurs in the L1 cache, processing the data access accordingly is the same as the conventional technique. However, in the shared memory control technique of the present invention, when a cache miss occurs in the L1 cache 115, when the line corresponding to the set index of the memory address to be accessed is in the L1 cache 115, The time cost of further searching is added and when there is no line in the L1 cache 115 corresponding to the set index, the time cost of further searching the shared memory 116 and the cache change from the L1 cache 115 to the shared memory 116 Time cost is added.

However, if the cache missed data in the L1 cache 115 is cached in the shared memory 116, it is not necessary to access the data in the lower L2 cache or the main memory, so that the time cost Can be greatly reduced.

According to the shared memory control technique of the present invention, since the entire memory capacity of the configurable memory 114 is not set to the L1 cache 115 and the setting of the shared memory 116 is maintained, When the shared memory 116 is to be used as a memory shared by the core units 111, 112 and 113, the shared memory 116 can immediately stop serving as an auxiliary cache of the L1 cache 115 and perform its role as a shared memory have.

Even if the shared memory 116 stops serving as the auxiliary cache of the L1 cache 115 in response to the need of the kernel application, the local memory control unit 118, if a cache miss occurs in the L1 cache 115, ), The unprocessed cache miss information is immediately stored in the MSHR and data is accessed from the external L2 cache 120 or the global GPU memory 140. [

Therefore, according to the shared memory control technique of the present invention, it is possible to perform the cache function in the shared memory of the general-purpose graphics processor at runtime and to search for time from the L1 cache to the global memory connected to the general- Can be minimized.

Table 1 below shows the performance improvement when an application that multiplies a matrix of a predetermined size is performed in a general-purpose graphics processor and a shared memory is used as an auxiliary cache of the L1 cache.

Matrix size Time required for existing techniques
(Unit: cycle) The time required for the technique of the present invention
(Unit: cycle) Reduction rate 96 × 96 34955 32734 6.4% 128 x 128 87495 67837 22.5% 160 x 160 104521 88763 15.1% 256 × 256 635045 545608 14.1% 320 x 320 791043 454586 42.5% 400 x 400 1658483 796374 52% 512 × 512 4198154 4811830 7.4%

Referring to Table 1, when the shared memory is used as the auxiliary cache of the L1 cache according to the shared memory control technique of the present invention, compared to the case of using only the L1 cache without utilizing the shared memory according to the existing cache control technique, The time required could be shortened by as much as 6.4% and as much as 52%.

Because graphical applications or scientific simulation applications are made up of a large number of matrix operations or vector operations, the shared memory control technique of the present invention can result in significant performance improvements overall.

2 is a flowchart illustrating a shared memory control method according to an embodiment of the present invention.

A shared memory control method according to an embodiment of the present invention includes a general graphics processor 10 including a plurality of multiprocessors 110, an L2 cache 120 and a global GPU memory 140, 110 each include a plurality of core units 111, 112, 113, a configurable memory 114 and a local memory control unit 118 and the configurable memory 114 also includes a plurality of core units 111, In step S21, the local memory control unit 118 determines whether or not the kernel application is to use the shared memory in the configurable memory 114 (step < RTI ID = 0.0 > ) To the maximum configurable size of the L1 cache 115 and the minimum configurable size of the shared memory 116. [

At this time, in step S21, the local memory controller 118 may configure the shared memory 116 with the same line size as the mapping method of the L1 cache 115. [

In step S22, when there is a load / store instruction for data access by one of the core units 111, 112, and 113, the local memory control unit 118 sets the L1 cache in the configurable memory 114 (115).

In step S23, if a cache hit occurs in the L1 cache 115 in accordance with the search in step S22, the process proceeds to step S29, where the local memory control unit 118 accesses the data And terminates the load / store command.

If a cache miss occurs in the L1 cache 115 in the search of step S22, the process proceeds to step S24.

In step S24, the local memory control unit 118 proceeds to step S25 if a line corresponding to the set index of the memory address to be accessed is in the L1 cache 115. Otherwise, if the set of memory addresses to be accessed If there is no line corresponding to the index in the L1 cache 115, the process proceeds to step S26.

The local memory control unit 118 searches the shared memory 116 instead of accessing the L2 cache 120 in step S25.

The local memory controller 118 stores the victimized victim blocks in the L1 cache 115 and stores the victimized victim blocks in the shared memory 116. Even if a cache miss occurs in the L1 cache 115, It is highly likely that the lines of the set index are still stored.

Here, since the block is a data exchange unit between the L1 cache 115 and the shared memory 116, the size of the block may be equal to the size of the line.

In step S26, the local memory control unit 118 selects a victim block in the L1 cache 115 according to a predetermined cache replacement policy, for example, LRU, NRU, or RRIP, 115 to the shared memory 116 and proceeds to step S25 to search for the shared memory 116. [

In step S26, if there is no empty block in the shared memory 116 to copy the victim block, then the local memory controller 118 determines whether a cache replacement policy applied in the shared memory 116, The secondary victim block is selected in the shared memory 116 according to the LRU, NRU, or RRIP, the selected secondary victim block is copied from the shared memory 116 to the L2 memory 120, It may store the victim block that is sacrificed from the L1 cache 115 in the space where the victim block was stored.

After searching the shared memory 116 in step S25, the local memory control unit 118, in step S27, searches the shared memory 116 and if a cache hit occurs in the shared memory 116, The flow advances to step S29 to access the data and terminate the load / store instruction.

If a cache miss occurs in step S27, the flow advances to step S28.

In step S28, the local memory control unit 118 stores information related to an outstanding miss in the MSHR, accesses the data in the lower L2 cache 120 or the global GPU memory 140, It is possible to terminate the load / store instruction while storing the data in the L1 cache 115 and updating the unprocessed cache miss information.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. It will be understood that variations and specific embodiments which may occur to those skilled in the art are included within the scope of the present invention.

Further, the apparatus according to the present invention can be implemented as a computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the recording medium include ROM, RAM, optical disk, magnetic tape, floppy disk, hard disk, nonvolatile memory and the like. The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

10 Universal graphics processor
110 multiprocessor
111, 112, and 113 core units
114 Configurable Memory
115 L1 cache
116 shared memory
117 Texture cache
118 Local Memory Control
120 L2 cache
130 global memory controller
140 Global GPU Memory
150 thread management unit

Claims (11)

A general purpose graphics processor comprising a plurality of multiprocessors, an L2 cache, and a global GPU memory,
A plurality of core units;
A configurable memory configured to be divided into an L1 cache and a shared memory at a predetermined capacity ratio; And
And a local memory controller for storing a victim block that is sacrificed in the L1 cache in the shared memory while the kernel application running on the general purpose graphics processor does not use the shared memory. Processor. The memory control apparatus according to claim 1,
And to configure the shared memory with the same line size as the mapping of the L1 cache. The apparatus of claim 1, wherein the local memory control unit
If there is a load / store instruction for data access by one of the core units,
If a cache hit occurs in the L1 cache, data is accessed from the L1 cache and the load / store instruction is terminated.
And to search for the shared memory if a cache miss occurs in the L1 cache. 4. The method of claim 3, further comprising: when a cache miss occurs in the L1 cache,
The local memory control unit,
If a line corresponding to a set index of a memory address to be accessed exists in the L1 cache,
If a corresponding index of the memory address to access is not in the L1 cache, a victim block is selected from the L1 cache and the selected victim block is copied from the L1 cache to the shared memory And to search for the shared memory. 5. The apparatus according to claim 4,
If there is no empty space to copy the victim block to the shared memory, a second sacrifice block is selected from the shared memory according to a predetermined cache replacement policy applied to the shared memory, To the L2 memory or the global GPU memory from the shared memory and then to store the victim block that is sacrificed from the L1 cache in the space where the secondary victim block was stored. 5. The method according to claim 4, further comprising:
The local memory control unit,
If a cache hit occurs in the shared memory, data is accessed from the shared memory and the load / store instruction is terminated.
If a cache miss occurs in the shared memory, information related to an unprocessed cache miss is stored in a Miss Status Holding Register (MSHR), data is accessed from the L2 cache or the global GPU memory, And to terminate the load / store instruction while updating the unprocessed cache miss information of the MSHR. 1. A shared memory control method for a general purpose graphics processor comprising a plurality of multiprocessors, an L2 cache and a global GPU memory,
Each of the multiprocessors includes a plurality of core units, a configurable memory, and a local memory controller, and when the configurable memory is divided into L1 cache and shared memory at a predetermined ratio,
The local memory control unit,
(a) if there is a load / store instruction for data access by one of the core units, searching the L1 cache;
(b) accessing data in the L1 cache and terminating a load / store instruction when a cache hit occurs in the L1 cache in step (a);
(c) if in step (a) a cache miss occurs in the L1 cache and a line corresponding to a set index of a memory address to access is in the L1 cache, searching for the shared memory;
(d) if in step (a) a cache miss occurs in the L1 cache and a line corresponding to a set index of a memory address to be accessed is not in the L1 cache, in accordance with a predetermined cache replacement policy, Copying the selected victim block from the L1 cache to the shared memory, and searching for the shared memory;
(e) accessing data in the shared memory and terminating a load / store instruction when a cache hit occurs in the shared memory in step (c) or step (d);
(f) if a cache miss occurs in the shared memory in step (c) or step (d), storing information related to an unprocessed cache miss in the MSHR, accessing data in the L2 cache or the global GPU memory, Storing the accessed data in the L1 cache, and terminating a load / store instruction while updating the unprocessed cache miss information. 8. The method of claim 7, wherein prior to step (a)
If the kernel application does not use the shared memory, setting the configurable memory to a maximum configurable size L1 cache and a minimum configurable shared memory size, Shared memory control method. 9. The method of claim 8, wherein setting the configurable memory further comprises:
And configuring the shared memory with the same line size as the mapping method of the L1 cache, by the local memory control unit. The method of claim 7, wherein step (d)
Wherein the local memory control unit selects a second sacrifice block in the shared memory according to a predetermined cache replacement policy applied in the shared memory if there is no empty block to copy the victim block to the shared memory, And copying the secondary victim block from the shared memory to the L2 memory or the global GPU memory and then storing the victim block that is sacrificed from the L1 cache in the space where the secondary victim block was stored A shared memory control method for a general purpose graphics processor. 1. A shared memory control method for a general purpose graphics processor comprising a plurality of multiprocessors, an L2 cache and a global GPU memory,
Each of the multiprocessors includes a plurality of core units, a configurable memory, and a local memory controller, and when the configurable memory is divided into L1 cache and shared memory at a predetermined ratio,
The local memory control unit,
(a ') searching the L1 cache if there is a load / store instruction for data access by one of the core units;
(b ') accessing data in the L1 cache if a cache hit occurs in the L1 cache in step (a');
(c ') if a cache miss occurs in the L1 cache in step (a'), searching for the shared memory; And
(d ') accessing data in the L2 cache or in the global GPU memory if a cache miss occurs in the shared memory in step (c').

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