KR101616091B1 - A monolithic three dimensional NAND string - Google Patents

Abstract

A monolithic three-dimensional NAND string is disclosed. A monolithic three-dimensional NAND string includes a semiconductor channel in which at least one end extends perpendicular to a major surface of the substrate, a plurality of strips extending in parallel to the major surface of the substrate, Wherein the plurality of control gate electrodes comprise a first control gate electrode located at a first device level and a second control gate electrode located at a second device level, 1 device level and above the main surface of the substrate, a blocking dielectric comprising a plurality of blocking dielectric segments, each of the blocking dielectric segments contacting each of the plurality of control gate electrodes , And wherein each of the plurality of blocking dielectric segments A plurality of discrete charge storage segments, each of the plurality of discrete charge storage segments being partially located within each of the blocking dielectric segments in the shell-like form, Wherein the charge storage segments include a first separate charge storage segment located at the first device level and a second separate degraded storage segment located at the second device level, and each of the plurality of separate charge storage A tunnel dielectric disposed between the segments and the semiconductor channel, the tunnel dielectric being located entirely outside the blocking dielectric segments in the shell-like form.

Description

A monolithic three dimensional NAND string < RTI ID = 0.0 >

The present invention relates to a three-dimensional nonvolatile memory device having a floating gate and a method of manufacturing the same.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of a memory semiconductor device, the degree of integration is an important factor in determining the price of the product, and thus an increased degree of integration is required. In the case of a conventional two-dimensional or planar memory semiconductor device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional memory semiconductor device is increasing, but is still limited, because of the need for expensive equipment to miniaturize the pattern.

In order to overcome such a limitation, three-dimensional memory semiconductor devices having memory cells arranged three-dimensionally have been proposed. However, in order to mass-produce a three-dimensional memory semiconductor device, a process technology capable of reducing the manufacturing cost per bit compared to that of the two-dimensional memory semiconductor device and realizing a reliable product characteristic is required.

A technical problem of the present invention relates to a monolithic three-dimensional NAND string having excellent reliability even by a simple process.

According to one embodiment, a monolithic three-dimensional NAND string comprises a semiconductor channel in which at least one end extends perpendicularly to a major surface of the substrate, a strip extending parallel to the main surface of the substrate wherein the plurality of control gate electrodes comprise a first control gate electrode located at a first device level and a second control gate electrode located at a second device level, 2 device level is located below the first device level and above the major surface of the substrate, a blocking dielectric comprising a plurality of blocking dielectric segments, each of the blocking dielectric segments comprising a plurality of Gate electrodes, the plurality of blocking dielectric < RTI ID = 0.0 > A portion of each of the segments having a clam shape; a plurality of discrete charge storage segments, each of the plurality of discrete charge storage segments being partially located within the respective blocking dielectric segment of the shell- Wherein the plurality of discrete charge storage segments comprise a first separate charge storage segment located at the first device level and a second separate degraded storage segment located at the second device level, A tunnel dielectric disposed between the separated charge storage segments and the semiconductor channel, the tunnel dielectric being located entirely outside the blocking dielectric segments in the shell-like form.

According to another embodiment, a monolithic three-dimensional NAND string comprises a semiconductor channel in which at least one end extends perpendicularly to a major surface of the substrate; A plurality of control gate electrodes having a strip shape extending parallel to the main surface of the substrate, wherein the plurality of control gate electrodes comprises a first control gate electrode located at a first device level and a second control gate electrode located at a second device level Wherein the second device level is located below the first device level and above the major surface of the substrate; A blocking dielectric comprising a plurality of blocking dielectric segments, each of the plurality of blocking dielectric segments being positioned in contact with each of the plurality of control gate electrodes; Wherein at least one of the plurality of discrete charge storage segments comprises at least one of a plurality of discrete charge storage segments defined by a sidewall of the first control gate electrode, a sidewall of the first insulating layer, and a sidewall of the second insulating layer. Wherein the first insulating layer is disposed over the first control gate electrode and the second insulating layer is disposed under the first control gate electrode, and the plurality of discrete charge storage segments A first separated charge storage segment located at a first device level and a second separated charge storage segment located at a second device level; And a tunnel dielectric disposed between each of the plurality of discrete charge storage segments and the semiconductor channel.

According to an embodiment of the present invention, a three-dimensional nonvolatile memory element having a floating gate can be provided. According to an embodiment of the present invention, since the floating gates separated from each other are formed so as to be stacked, a problem that the charge is stored in the floating gate and the charge is diffused to other neighboring cells after the floating gate is programmed can be prevented .

Therefore, the reliability of the semiconductor device can be improved, and malfunction of the memory device can be prevented.

In addition, the floating gate is formed using etching selectivity between different layers, so that the floating gate can be formed easily in the process.

1 is a circuit diagram of a nonvolatile memory device according to embodiments of the present invention.
Figures 2, 4, 6, and 8 are cross-sectional views of non-volatile memory devices in accordance with embodiments of the present invention.
Figures 3, 5, 7, and 9 are perspective views of Figures 2, 4, 6, and 8 illustrating non-volatile memory devices in accordance with embodiments of the present invention.
10 to 16 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.
17 and 18 are cross-sectional views illustrating a method of manufacturing nonvolatile memory devices according to another embodiment of the present invention.
19 to 28 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.
29 is a cross-sectional view illustrating a method of fabricating nonvolatile memory devices according to another embodiment of the present invention.
30 is a block diagram schematically illustrating an electronic device including a nonvolatile memory device according to embodiments of the present invention.
31 is a block diagram illustrating a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The object (s), feature (s), and advantages (s) of the present invention will be readily appreciated by the following embodiments in connection with the accompanying drawings. The present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the same reference numerals are used for elements having the same function.

In the present specification, when a material film such as a conductive film, a semiconductor film, or an insulating film is referred to as being on another material film or substrate, any material film may be formed directly on the other material film or substrate, Which means that another material film may be interposed. Also, in various embodiments of the present specification, the terms first, second, third, etc. are used to describe various parts, materials, etc., but these parts should not be limited by the same terms. These terms are also only used to distinguish certain parts from other parts. Thus, what is referred to as the first portion in any one embodiment may be referred to as the second portion in other embodiments.

It should be understood that the term 'and / or' in this specification refers to any or all of the arrangements listed before and after the term.

1 is a circuit diagram showing a nonvolatile memory device of a three-dimensional structure according to embodiments of the present invention.

Referring to FIG. 1, a non-volatile memory device according to an embodiment of the present invention may include a cell array having a plurality of STRs. The cell array includes a plurality of bit lines BL1 to BL4, word lines WL1 to WL3, upper select lines USL1 to USL3, lower select lines LSL and a common source line CSL can do. The non-volatile memory device may include a plurality of strings STR between the bit lines BL1 to BL4 and the common source line CSL.

Each string STR may include a plurality of memory cell transistors MC connected in series between upper and lower selection transistors UST and LST and upper and lower selection transistors UST and LST . The drains of the upper select transistors UST are connected to the bit lines BL1 to BL4 and the sources of the lower select transistors LST are connected to the common source line CSL. The common source line CSL is a line to which the sources of the lower selection transistors LST are connected in common.

The upper select transistors UST are connected to the upper select lines USL1 to USL3 and the lower select transistors LST are connected to the lower select line LSL. Further, each of the memory cells MC is connected to the word lines WL1 to WL3.

Such a cell array is arranged in a three-dimensional structure, and the string STR has a structure in which the memory cells MC are connected in series in a z-axis direction perpendicular to the xy plane parallel to the upper surface of the substrate. Thus, the channels of the selection transistors UST and LST and the memory cell transistor MC can be formed perpendicular to the xy plane.

In a nonvolatile memory device having a three-dimensional structure, m memory cells may be formed in each xy plane, and an xy plane having m memory cells may be stacked in n layers. (Where m and n are natural numbers).

Hereinafter, referring to Figs. 2 to 9, nonvolatile memory devices according to embodiments of the present invention will be described.

A nonvolatile memory device according to a first embodiment of the present invention is described.

Referring to FIGS. 2 and 3, interlayer insulating films (110 in FIG. 2) and conductive films (LSL, WL, USL) may alternately and repeatedly be laminated on a substrate 100. The substrate 100 may be a semiconductor substrate and may include an impurity region (or well) 105 provided in a common source line (CSL in FIG. 1). The conductive film of the uppermost layer among the conductive films LSL, WL and USL is used as an upper select line USL, the lowermost conductive film is used as a lower select line LSL, . ≪ / RTI > The conductive films may be formed of conductive polysilicon or a metal material.

The lower selection lines LSL may be formed in a plate form or in a line form separated from each other. The upper select line USL may be formed in a line form separated from each other. The word lines WL located between the lower select line LSL and the upper select line USL may each be in the form of a flat plate. The word lines of each layer are formed in a plate shape so that the same voltage can be applied to the word lines of the memory cells formed in the same layer.

In addition, the word lines WL may have a relatively reduced area formed above the word lines WL. That is, the stacked structure of the interlayer insulating films (110 in FIG. 2) and the conductive films (LSL, WL, USL) may have a stepwise edge.

A plurality of semiconductor pillars PL passing through the interlayer insulating films 110 and the conductive films LSL, WL, and USL may be disposed on the substrate 100. The semiconductor pillars PL may be electrically connected to the impurity region 105 in the substrate 100. The semiconductor pillars PL are spaced apart from each other and may be arranged in a matrix on a plane. The semiconductor pillars PL are formed of a semiconductor material and can correspond to the respective strings of the non-volatile memory device. Through the semiconductor pillars PL, the channels of the selection transistors and the memory cell transistors of each string can be electrically connected. The semiconductor pillars PL may be cylindrical, but are not limited thereto. The semiconductor pillars may have overall the same conductivity type. At least, the semiconductor pillars may have the same conductivity type on their surface. The channels of the non-volatile memory device of embodiments of the present invention may be formed in the semiconductor pillars.

Floating gates FG may be interposed between the side of the semiconductor pillars PL and the word lines WL. In addition, the floating gates FG may be interposed between adjacent interlayer insulating films (110 in FIG. 2). That is, the floating gates FG may be spaced apart from each other by the interlayer insulating films 110 (FIG. 2). For example, the floating gates FG may surround the semiconductor pillars PL in a donut shape between the interlayer insulating films 110 (FIG. 2). At this time, a gate insulating layer 143 may be interposed between the side surfaces of the semiconductor pillars PL and the floating gates FG. All the surfaces of the floating gate FG except the surface in contact with the gate insulating film 143 may be surrounded by an intergate dielectric (IGD). That is, the gate interlayer insulating film IGD may be interposed between the floating gate FG and the word line WL, and between the floating gate FG and the interlayer insulating film 110 (FIG. 2).

The gate insulating layer 143 may be interposed between the semiconductor pillars PL and the select line pattern SLP. The select line pattern SLP may be surrounded by a gate middle interlayer insulating film (MGD) such that the floating gate FG is surrounded by the inter-gate insulating film IGD. The selection line pattern SLP may be formed of the same material as the floating gates FG.

Accordingly, the gate insulating layer 143 is surrounded by the semiconductor pillars PL and can be spaced apart from each other like the floating gates FG.

Bit lines (BL) electrically connected to the semiconductor pillars (PL) may be formed on the upper surfaces of the semiconductor pillars (PL). The bit lines BL may be disposed so as to intersect the upper selection lines USL with each other. At this time, the semiconductor pillars PL may be respectively disposed at the intersections of the bit lines BL and the upper selection lines USL.

The vertical distance between the floating gates FG can be adjusted according to the thickness of the interlayer insulating film. Further, since the thickness of the interlayer insulating film is determined by the thin film forming process, not the patterning process, it may be thinner than the limit of the patterning resolution. Therefore, a non-volatile memory device including a floating gate according to an embodiment of the present invention can be operated using a fringe field. As described above, semiconductor pillars according to embodiments of the present invention may all have the same impurity type. In addition, the impurity type of the semiconductor column according to an embodiment of the present invention may be a conductive type opposite to that of the floating gate.

Referring to Figs. 4 and 5, a nonvolatile memory device according to a second embodiment of the present invention is described. Hereinafter, the same or similar components as those of the nonvolatile memory device according to the first embodiment of the present invention will be omitted or briefly described, and elements having different characteristics from those of the first embodiment (e.g., a gate insulating film and a gate interlayer insulating film ) Is explained.

4 and 5, the gate insulating film 143 according to an embodiment is formed between the side surfaces of the semiconductor pillars PL and the floating gates FG, and between the side surfaces of the semiconductor pillars PL and the interlayer insulating film (110) of the substrate. That is, the gate insulating layer 143 may extend along the side surfaces of the semiconductor pillars PL and surround the entire side surfaces of the semiconductor pillars PL.

All the surfaces of the floating gate FG except the surface in contact with the gate insulating film 143 may be surrounded by an intergate dielectric (IGD). The inter-gate insulating film IGD may be composed of a plurality of layers IGD1, IGD2 ₁ , and GID2 ₂ . According to another embodiment, the inter-gate insulating film IGD may be formed in a multilayer structure only between the floating gate FG and the word lines WL.

The select line pattern SLP may be surrounded by a gate intermediate insulating film MGD formed of a plurality of layers MGD1 and MGD2 in the same manner as the floating gate FG.

Referring to Figs. 6 and 7, a three-dimensional nonvolatile memory element according to a third embodiment of the present invention is described. Hereinafter, the same or similar contents as those of the nonvolatile memory devices according to the first and second embodiments of the present invention will be omitted or briefly described, and components having different characteristics from those of the first and second embodiments e.g., a selection line layer) is described.

6 and 7, the floating gates FG can be selectively interposed only between the side surfaces of the semiconductor pillars PL and the word lines WL. In addition, the floating gates FG may be interposed between adjacent interlayer insulating films 110 (FIG. 6), and may be vertically spaced from each other along the semiconductor pillars PL. At this time, the gate insulating layer 143 may be locally interposed between the side surfaces of the semiconductor pillars PL and the floating gates FG. Alternatively, the gate insulating layer 143 may extend along the side surfaces of the semiconductor pillars PL. All the surfaces of the floating gate FG except the surface in contact with the gate insulating film 143 may be surrounded by an intergate dielectric (IGD). The inter-gate insulating film IGD may have a stacked structure of oxide / nitride / oxide (IGD1 / IGD2 / IGD3).

Only the gate insulating film 143 may be interposed between the select lines USL and LSL and the semiconductor column PL. In other words, the memory device of FIG. 6 may not include another conductive pattern such as a floating gate between the selection line USL, LSL and the semiconductor column PL, unlike FIG. 2 or FIG.

Referring to Figs. 8 and 9, a three-dimensional nonvolatile memory element according to a fourth embodiment of the present invention is described. Hereinafter, the same or similar contents as those of the non-volatile memory devices according to the first to third embodiments of the present invention will be omitted or briefly described, and the constituent elements of the first to third embodiments, Elements (e.g., conductive films and interlayer insulating films) are described.

Referring to FIGS. 8 and 9, interlayer insulating patterns 115 and conductive line patterns LSL, WL, and USL may be alternately and repeatedly stacked on a substrate 100. The uppermost layer among the conductive line patterns LSL, WL and USL is used as an upper select line USL, the lowest layer is used as a lower select line LSL and the remaining conductive line patterns are used as word lines WL .

The conductive line patterns LSL, WL, USL may be in the form of a line extending in the same direction. One stack of the conductive line patterns LSL, WL, USL may be separated from the neighboring stack. At this time, in the same layer, the conductive line patterns constituting the word lines WL may be connected to each other so that the same voltage is applied.

A line-shaped isolated insulation pattern 180 may be disposed between the adjacent conductive line patterns LSL, WL, and USL.

A plurality of semiconductor pillars PL passing through the interlayer insulating patterns 115 and the conductive line patterns LSL, WL and USL stacked on the substrate 100 may be disposed. The semiconductor pillars PL may be arranged in a line spaced apart from each other between the adjacent separation insulating patterns 180. [ The semiconductor pillars PL may be arranged in a matrix on a plane.

A silicide layer 121b may be interposed between the isolation insulating patterns 180 and the conductive line patterns LSL, WL, and USL. The silicide layer 121b may be locally disposed on the surfaces of the conductive line patterns LSL, WL, and USL that contact the isolation insulating patterns 180. [

Hereinafter, a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to embodiments of the present invention will be described.

10 to 16, a method of manufacturing a three-dimensional non-volatile memory device according to the first embodiment of the present invention is described.

Referring to FIG. 10, interlayer insulating films 110 and conductive films 120 may be alternately and repeatedly stacked on a substrate 100. The substrate 100 may be a substrate, and may include an impurity region (for example, a well region) 105. The uppermost film of the stacked films 110 and 120 may be an interlayer insulating film. The number of stacked conductive films may vary depending on the capacity of the nonvolatile memory device. The distance between the conductive layers 120 may be determined by adjusting the thickness of the interlayer insulating layers 110.

The interlayer insulating layers 110 and the conductive layers 120 may be stacked on the memory cell region of the substrate 100 in the form of a flat plate. At this time, the interlayer insulating layers 110 and the conductive layers 120 may have a gradually reduced area as they are stacked on the substrate 100. For example, the edge portions of the interlayer insulating films 110 and the conductive films 120 may have a stepped shape. The interlayer insulating layers 110 and the conductive layers 120 may be formed by repeating a deposition step and a patterning step. Alternatively, after the interlayer insulating layers 110 and the conductive layers 120 are all stacked, the respective layers may be selectively patterned in layers.

The interlayer insulating films 110 may be formed of a silicon oxide film or a silicon nitride film. The conductive films 120 may be formed of a polysilicon film or a metal film. The conductive layers 120 may include a lower conductive layer 122 and an upper conductive layer 126 sequentially stacked from the substrate 100. Intermediate conductive films 124 may be stacked between the lower conductive film 122 and the upper conductive film 126. The lower conductive layer 122, the upper conductive layer 126, and the intermediate conductive layers 124 may have the same etch selectivity. For example, the lower conductive layer 122, the upper conductive layer 126, and the intermediate conductive layers 124 may be formed of the same material. The conductive films may comprise conductive polysilicon or a metallic material.

The upper conductive film 126 may be patterned in a line shape.

Referring to FIG. 11, a plurality of first openings 131 penetrating the films 110 and 120 may be formed by etching the stacked interlayer insulating films 110 and the conductive films 120 have. For example, a mask pattern (not shown) is formed on the uppermost film of the interlayer insulating films 110, and the interlayer insulating films 110 and the conductive films 120 exposed by the mask pattern are selectively As shown in FIG. The impurity region 105 of the substrate 100 can be exposed on the bottom surface of the first openings 131 and the interlayer insulating films 110 and the conductive The films 120 may be exposed. In this case, the first openings 131 may be circular, and the diameter of the first openings 131 may be smaller than the horizontal distance between the first openings 131 adjacent to each other. In addition, the first openings 131 may be formed in a planar matrix.

Referring to FIGS. 11 and 12, the conductive layers 120 exposed on the inner walls of the first openings 131 may be selectively recessed to form the conductive patterns 121. For example, an isotropic etching process may be performed on the result of FIG. The isotropic etching process may be performed to selectively etch the conductive layers 120 from other layers. The conductive patterns 121 may include a lower conductive pattern 123 and an upper conductive pattern 127 which are sequentially stacked from the substrate 100. Intermediate conductive patterns 125 may be stacked between the lower conductive pattern 123 and the upper conductive pattern 127. The intermediate conductive patterns 125 may be used as a control gate (or word line). The conductive patterns 121 are formed and the inner walls of the first openings 131 made of the conductive films 120 are selectively expanded to form the second openings 132. [

The second openings 132 may have the same bottom surface as the first openings 131. Meanwhile, the inner walls of the second openings 132 may be formed of the interlayer insulating layers 110 and the conductive patterns 121. The second openings 132 may include extension portions 133 surrounded by the conductive patterns 121 between the adjacent interlayer insulating films 110 and the adjacent interlayer insulating films 110. The diameter of the extension portions 133 may be larger than the diameter of the opening surrounded by the interlayer insulating films 110.

Referring to FIG. 13, a first insulating layer 141 may be formed on the resultant structure of FIG. The first insulating layer 141 may be conformally formed on the resultant structure of FIG. That is, the first insulating layer 141 may be formed along the inner wall and the bottom surface of the second openings 132. The first insulating layer 141 may be formed on the surfaces of the interlayer insulating layers 110 and the conductive patterns 121 exposed on the inner surfaces of the extended portions 133. The first insulating layer 141 may be a single layer or a plurality of layers. The first insulating layer 141 may be a composite oxide / nitride / oxide layer. According to another embodiment, the first insulating layer 141 may be made of a material having a high dielectric constant.

A deposition process may be performed to form the first insulating layer 141. For example, an atomic layer deposition process (or a modification process of an atomic layer deposition process) and / or a chemical vapor deposition process (including a modification process such as a low pressure chemical vapor deposition process and a plasma enhanced chemical vapor deposition process) may be performed.

Referring to FIG. 14, a buried conductive film 151 may be formed to fill the inside of the second openings 132. The embedded conductive film 151 may fill the extensions 133. The buried conductive film 151 may be formed to cover the uppermost layer of the interlayer insulating film. The buried conductive film 151 may be made of conductive polysilicon.

Referring to FIG. 15, the third openings 134 may be formed by performing an anisotropic etching process on the buried conductive film 151. The anisotropic etching process may be performed using the interlayer insulating films 110 as an etching mask. The anisotropic etching process may be performed to expose the upper surface of the substrate 100. As a result, a portion of the buried conductive film 151 may remain in the extension portions 133, so that the buried conductive patterns 152 may be formed. In addition, the first insulating layer 141 on the inner walls of the second openings 132, except for the extension portions 133, is selectively removed by the anisotropic etching process, so that the first insulation patterns 141, (142) may be locally formed. Accordingly, the interlayer insulating layers 110 and the buried conductive patterns 152 may be exposed to the inner walls of the third openings 134. At this time, the first insulating patterns 142 may surround all the surfaces of the buried conductive patterns 152 except the side exposed to the inner walls of the third openings 134.

Alternatively, the planarization process may be performed on the buried conductive film 151 so that the upper surface of the uppermost layer of the interlayer insulating films 110 is exposed. A mask pattern (not shown) exposing the buried conductive film 151 in the second openings 132 may be formed on the uppermost layer of the interlayer insulating films 110. The anisotropic etching process may be selectively performed on the buried conductive film 151 using the mask pattern as an etching mask. After the buried conductive film 151 is etched, the first insulating layer 141 on the bottom surface of the exposed second openings 132 may be removed to form the third openings 134. At this time, the first insulating layer 141 may remain on the sidewalls of the third openings 134. That is, the first insulating patterns 142 surrounding the buried conductive patterns of different layers may be connected to each other along the inner wall of the third openings 134.

Referring to FIG. 16, an oxidation process may be performed on the result of FIG. The oxidation process may be a thermal oxidation process. An oxide film may be formed on the surface of the buried conductive patterns 152 exposed on the inner walls of the third openings 134 by the oxidation process. At this time, the upper surface of the substrate 100 exposed at the bottom of the third openings 134 may also be oxidized. The oxide film formed on the bottom surface of the third openings 134 may be removed by an anisotropic etching process. As a result, the gate insulating layer 143 may be selectively formed on the surface of the buried conductive patterns 152 exposed on the inner walls of the third openings 134. The gate insulating layer 143 may be formed by a radical oxidation process or the like.

The third openings 134 may be filled with a semiconductor material. At this time, the uppermost layer of the interlayer insulating layers 110 may be covered with the semiconductor material. A planarization process may be performed to expose the uppermost layer of the interlayer insulating films 110 so that the semiconductor pillars PL may be formed in the third openings 134. At this time, the semiconductor material may be a polycrystalline or single crystal semiconductor.

And bit lines BL may be formed on the semiconductor pillars PL. After the conductive layer is formed on the uppermost layer of the semiconductor pillars PL and the interlayer insulating layers 110, the conductive layer may be patterned to form the bit lines BL. Thus, the semiconductor pillars PL can be electrically connected to the bit lines BL.

17 to 18, a three-dimensional nonvolatile memory device according to a second embodiment of the present invention and a manufacturing method thereof will be described. Here, the same or similar contents as those described above may be omitted or briefly described.

Referring to FIG. 17, a first insulating layer 141 may be formed on the resultant structure of FIG. The first insulating layer 141 may have a multi-layer structure. The first insulating layer 141 may include a first sub-insulating layer 144 and a second sub-insulating layer 145. The first sub-insulating layer 144 may be formed by an oxidation process. Therefore, the first sub-insulating layer 144 may be selectively formed on the exposed surfaces of the conductive patterns 121. In addition, the upper surface of the substrate 100 may be oxidized by the oxidation process.

A second sub-insulating layer 145 may be conformally formed on the resultant structure. That is, the second sub-insulating layer 145 may be formed along the inner wall, the extended portions 133, and the bottom surface of the second openings 132. And the second sub-insulating layer 145 may have a high dielectric constant. The second sub-insulating layer 145 may be formed by a deposition process. Thus, the first sub-insulating layer 144 and the second sub-insulating layer 145 may be selectively stacked on the exposed surfaces of the conductive patterns 121.

Referring to FIG. 18, as described above, the embedded conductive patterns 152 including conductive polysilicon are formed in the extension portions 133, and the third openings 134 are formed as side surfaces thereof . In addition, the second sub-insulating layer 145 on the inner wall of the third openings 134, except for the extension portions 133, is selectively removed by the anisotropic etching process to form the second sub- (146) may be formed. Accordingly, the interlayer insulating layers 110 and the buried conductive patterns 152 may be exposed to the inner walls of the third openings 134. At this time, the second sub-insulating patterns 146 may surround all the surfaces of the buried conductive patterns 152 except the side exposed to the inner wall of the third openings 134.

Alternatively, the second sub-insulating patterns 146 surrounding the buried conductive patterns of the different layers may be connected to each other along the inner wall of the third openings 134.

A gate insulating layer 143 may be selectively formed on the inner walls of the third openings 134. A deposition process and an anisotropic etching process may be performed to form the gate insulating film 143. [ For example, an atomic layer deposition process (or a modification process of an atomic layer deposition process) and / or a chemical vapor deposition process (including a modification process such as a low pressure chemical vapor deposition process and a plasma enhanced chemical vapor deposition process) may be performed. An insulating film may be conformally formed on the resultant in the above-described deposition process. Thereafter, the insulating film formed on the bottom surface of the third openings 134 and on the uppermost layer of the interlayer insulating films 110 may be removed by an anisotropic etching process.

Referring again to FIG. 4, the semiconductor pillars PL may be formed in the third openings 134. The semiconductor pillars PL may have substantially the same upper surface as the uppermost layer of the interlayer insulating layers 110. [ At this time, the semiconductor material may be a polycrystalline or single crystal semiconductor. And bit lines BL may be formed on the semiconductor pillars PL.

Referring to Figs. 19 to 29, a three-dimensional nonvolatile memory device and a manufacturing method thereof according to a third embodiment of the present invention are described.

Referring to FIG. 19, a lower interlayer insulating layer 110a and a lower conductive layer 122 may be sequentially stacked on a substrate 100. FIG. The substrate 100 may be a substrate, and may include an impurity region (for example, a well region) 105.

Referring to FIG. 20, a mask pattern (not shown) may be formed on the lower conductive layer 122. The lower conductive layer 122 may be selectively anisotropically etched using the mask pattern as an etching mask. Accordingly, lower openings 130a penetrating the lower conductive layer 122 can be formed. At this time, the lower openings 130a may expose the lower interlayer insulating layer 110a or expose the substrate 110. [ The mask pattern can be removed.

Referring to FIG. 21, an intermediate buried insulating film 110b may be formed on the substrate 100 to fill the lower openings 130a. The intermediate conductive films 124 and the intermediate interlayer insulating films 110c may be alternately stacked on the intermediate buried insulating film 110b. The intermediate buried insulating film 110b may be planarized before the intermediate conductive films 124 are formed and the thickness of the intermediate buried insulating film 110b on the lower conductive film 122 may be equal to or greater than the thickness of the intermediate conductive film 124 The thickness of the intermediate interlayer insulating film 110c on the interlayer insulating film 110c.

Referring to FIG. 22, a mask pattern (not shown) may be formed on the uppermost layer of the intermediate interlayer conductive films 110c. The mask pattern may be formed using the same mask as the photomask used to form the lower openings 130a. The intermediate conductive films 124 and the intermediate interlayer insulating films 110c may be selectively anisotropically etched using the mask pattern. Thus, the first intermediate openings 130b penetrating the intermediate conductive films 124 and the intermediate interlayer insulating films 110c may be formed. At this time, the anisotropic etching process may be performed using the intermediate buried insulating film 110b as an etch stop layer. The upper surface of the intermediate buried insulating film 110b may be exposed on the bottom surface of the first intermediate openings 130b and the intermediate conductive films 124 and the intermediate interlayer insulating films 110c may be exposed on the inner walls .

Referring to FIG. 23, the intermediate conductive films 124 exposed to the inner walls of the first intermediate openings 130b may be selectively recessed. Thereby, the intermediate conductive patterns 125 can be formed. The intermediate conductive patterns 125 may be used as a control gate (or word line). At the same time, the inner walls of the first intermediate openings 130b made of the intermediate conductive films 124 can be selectively expanded. Thereby, the second intermediate openings 130c can be formed. For example, an isotropic etching process may be performed on the result of FIG. The isotropic etching process may be performed to selectively etch the intermediate conductive films 124 from other films.

The second intermediate openings 130c may have the same bottom surface as the first intermediate openings 130b. On the other hand, the inner walls of the second intermediate openings 130c may be formed of the intermediate interlayer insulating films 110c and the intermediate conductive patterns 125. The second intermediate openings 130b may include extensions 133 surrounded by the intermediate conductive patterns 125 between the adjacent interlayer insulating films 110 and the adjacent interlayer insulating films 110 . The diameter of the extension portions 133 may be larger than the diameter of the opening surrounded by the intermediate interlayer insulating films 110c.

Referring to FIG. 24, a sacrificial pattern 110d may be formed to fill the second intermediate openings 130c. At this time, the sacrificial pattern 110d may be formed to fill the extensions 133. The sacrificial pattern 110d may be formed by a deposition process and a planarization process. The sacrificial pattern 110d may have a top surface substantially the same height as the uppermost layer of the intermediate interlayer insulating films 110c. The sacrificial pattern 110d may be formed of a material having etch selectivity with respect to the interlayer insulating layers 110 and the conductive layers 120. [ For example, the interlayer insulating layers 110 may include silicon nitride, the conductive layers 120 may include conductive polysilicon or a metal material, and the sacrificial pattern 110d may include silicon oxide .

An upper conductive layer 126 and an upper interlayer insulating layer 110e may be sequentially stacked on the uppermost layer of the sacrificial pattern 110d and the intermediate interlayer insulating layers 110c. The upper conductive film 126 may be a film patterned in a line shape.

Referring to FIG. 25, a mask pattern (not shown) may be formed on the upper interlayer insulating film 110e. The mask pattern may be formed using the same mask (e.g., a reticle) as the photomask used to form the lower openings 130a and / or the first intermediate openings 130b. The upper interlayer insulating film 110e and the upper conductive film 126 may be selectively anisotropically etched using the mask pattern. Thereby, the upper surface of the sacrificial pattern 110d can be exposed.

The sacrificial pattern 110d may be selectively removed. The sacrificial pattern 110d may be formed of a material having different etch selectivity from the conductive layers 122 and 126, the conductive patterns 125, and the interlayer dielectric layers 110. [ Accordingly, the conductive films 122 and 126, the conductive patterns 125, and the interlayer insulating films 110 are not etched or minimally etched by the isotropic etching process, and the sacrificial pattern 110d is selectively etched Lt; / RTI > The sacrificial pattern 110d may be removed so that the second intermediate openings 130c may be formed again.

The intermediate buried insulating film 110b may be exposed on the bottom surface of the second intermediate openings 130c. The intermediate buried insulating film 110b exposed using the interlayer insulating films 110 as an etch mask may be selectively anisotropically etched. Thereby, first openings 135 penetrating the upper conductive film 126, the intermediate conductive patterns 125, and the lower conductive film 122 and exposing the upper surface of the substrate 100 are formed .

The substrate 100 is exposed on the bottom surface of the first openings 135 and the interlayer insulating films 110, the conductive films 122 and 126, The conductive patterns 125 may be exposed. At this time, the first openings 135 may be circular. Also, the first openings 135 may be formed in a planar matrix. The first openings 135 may have different diameters in different regions. For example, in the first openings 135, the diameter of the region penetrating the interlayer insulating layers 110, the upper conductive layer 126, May be smaller than the diameter of the region passing through the openings (125). That is, the first openings 135 may include the extensions 133 having a partially wide diameter.

The interlayer insulating layers 110, the conductive layers 122 and 126 and the conductive patterns 125 may be stacked on the memory cell region of the substrate 100 in the form of a flat plate. At this time, the interlayer insulating layers 110 and the conductive layers 120 may have a gradually reduced area as they are stacked on the substrate 100. For example, the edge portions of the interlayer insulating films 110, the conductive films 122 and 126, and the conductive patterns 125 may have a stepped shape.

The interlayer insulating films 110 may be formed of a silicon oxide film or a silicon nitride film. At this time, at least the sacrificial pattern 110d may be made of a material that can be selectively etched in the etching process than the upper interlayer insulating film 110e and the intermediate buried insulating film 110b.

The conductive films 122 and 126 and the conductive patterns 125 may be formed of a polysilicon film or a metal film and both the conductive films 122 and 126 and the conductive patterns 125 may be formed of the same material, And may be formed of different materials. At this time, at least the intermediate conductive patterns 125 may be formed of the same material.

Referring to FIG. 26, the first insulating layer 141 may be conformally formed on the resultant structure of FIG. That is, the first insulating layer 141 may be formed along the inner wall and the bottom surface of the first openings 135. The first insulating layer 141 may be formed on the surfaces of the interlayer insulating layers 110 and the intermediate conductive patterns 125 exposed on the inner surfaces of the extension portions 133. The first insulating layer 141 may be a single layer or a plurality of layers. The first insulating layer 141 may have a high dielectric constant.

A deposition process may be performed to form the first insulating layer 141. For example, an atomic layer deposition process (or a modification process of an atomic layer deposition process) and / or a chemical vapor deposition process (including a modification process such as a low pressure chemical vapor deposition process and a plasma enhanced chemical vapor deposition process) may be performed. The first insulating layer 141 may further include an oxide layer formed on the surface of the intermediate conductive patterns 125 selectively exposed to the inner walls of the first openings 135 by a thermal oxidation process.

Referring to FIGS. 27 and 28, a buried conductive film 151 may be formed to fill the inside of the first openings 135. The embedded conductive film 151 may fill the extensions 133. The buried conductive film 151 may be made of conductive polysilicon.

The second openings 136 may be formed by performing an anisotropic etching process on the buried conductive film 151. The anisotropic etching process may be performed using the upper interlayer insulating film 110e as an etching mask. The anisotropic etching process may be performed to expose the upper surface of the substrate 100. Thereby, a part of the buried conductive film 151 remains in the extensions 133, and the mummy conductive patterns 152 used as a floating gate can be formed. The first insulating layer 141 on the inner walls of the first openings 135 except for the extension portions 133 is selectively removed by the anisotropic etching process to be used as a gate interlayer insulating film in the extension portions 133 The first insulating pattern 142 may be formed. Therefore, the interlayer insulating layers 110, the embedded conductive patterns 152 used as the floating gate, the upper conductive layer 126, and the lower conductive layer 122 (not shown) are formed on the inner walls of the second openings 136. [ ) Can be exposed. At this time, the first insulation pattern 142 may cover all the surfaces of the embedded conductive patterns 152 except the side exposed to the inner walls of the second openings 136.

Alternatively, the first insulating patterns 142 surrounding the different floating gates may be connected to each other along the inner wall of the second openings 136.

Referring to FIG. 6 again, the oxidation process and the anisotropic etching process are performed on the resultant structure of FIG. 28, so that the upper conductive film 126 exposed on the inner wall of the second openings 136, And a gate insulating layer 143 may be selectively formed on the lower conductive layer 122 and the surface of the lower conductive layer 122. Alternatively, the gate insulating film 143 may extend along the inner wall of the second openings 136 by a deposition process and an anisotropic etching process.

The second openings 136 may be filled with a semiconductor material to form the semiconductor pillars PL in the second openings 136. At this time, the semiconductor material may be a polycrystalline or single crystal semiconductor.

And bit lines BL may be formed on the semiconductor pillars PL.

Referring to Fig. 29, a nonvolatile memory device having a three-dimensional structure according to a fourth embodiment of the present invention and a manufacturing method thereof will be described. Hereinafter, the same or similar contents as those described above may be omitted or briefly described.

Referring to FIG. 29, an anisotropic etching process may be performed so that the stacked conductive patterns 121 between the semiconductor pillars PL of the resultant structure of FIG. 16 are separated. The line openings 137 passing through the interlayer insulating layers 110 and the conductive patterns 121 may be formed by the anisotropic etching process so that the separated conductive patterns 121a may be formed . In addition, the interlayer insulating layers 110 are patterned to form the interlayer insulating patterns 115.

Thereafter, the silicide layer 121b may be formed on the surfaces of the separated conductive patterns 121a exposed on the inner walls of the line openings 137 by performing a silicidation process. At this time, the upper surface of the semiconductor pillars PL may be protected by an insulating film (not shown). The silicidation process may include metal film deposition, heat treatment, and an unreacted metal removal process.

The line openings 137 may be filled with an insulating material and bit lines BL may be formed on the semiconductor pillars PL electrically connected to the semiconductor pillars PL .

The above processes can be applied to the manufacturing method of the memory device according to the other embodiments described above.

Referring to Fig. 30, an electronic device 200 including a non-volatile memory device according to embodiments of the present invention is described. The electronic device 200 may be a wireless communication device such as a PDA, a laptop computer, a portable computer, a web tablet, a cordless telephone, a cellular phone, a digital music player, Lt; RTI ID = 0.0 > and / or < / RTI >

The electronic device 200 may include an input and output device 220 such as a keypad, a keyboard, a display, a memory 230, and a wireless interface 240 coupled to each other via a bus 250. Controller 210 may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory 230 may be used to store instructions executed by controller 210, for example. The memory 230 may also be used to store user data. The memory 230 includes a non-volatile memory device according to embodiments of the present invention.

The electronic device 200 may use the wireless interface 240 to transmit data to or receive data from a wireless communication network that communicates with an RF signal. For example, the wireless interface 240 may include an antenna, a wireless transceiver, and the like.

The electronic device 200 according to an embodiment of the present invention may be used in communication interface protocols such as third generation communication systems such as CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000.

31, a memory system including a non-volatile memory device according to embodiments of the present invention is described.

The memory system 300 may include a memory device 310 and a memory controller 320 for storing a large amount of data. The memory controller 320 controls the memory device 310 to read or write data stored in the memory device 310 in response to a read / write request of the host 330. [ The memory controller 320 may configure an address mapping table for mapping an address provided from the host 330 (a mobile device or a computer system) to a physical address of the memory device 310 have.

The foregoing description is intended to illustrate and describe the present invention. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. In addition, the appended claims should be construed to include other embodiments.

Claims (12)

A semiconductor channel in which at least one end extends perpendicularly to a major surface of the substrate;
A plurality of control gate electrodes having a strip shape extending parallel to the main surface of the substrate, the plurality of control gate electrodes comprising a first control gate electrode positioned at a first device level and a second control gate electrode positioned at a second device level Wherein the second device level is located below the first device level and above the major surface of the substrate;
Wherein each of the blocking dielectric segments is located in contact with each of the plurality of control gate electrodes and wherein a portion of each of the plurality of blocking dielectric segments is in a ' Having a shape;
Wherein each of the plurality of discrete charge storage segments is partially located within each of the blocking dielectric segments of the 'D' shape, and the plurality of discrete charge storage segments are located in the first device A first separate charge storage segment located at a second device level and a second separated degraded storage segment located at a second device level; And
A tunnel dielectric disposed between each of the plurality of discrete charge storage segments and the semiconductor channel, the tunnel dielectric comprising a monolithic three-dimensional NAND string located outside the blocking dielectric segments of the ' . The method according to claim 1,
Wherein the plurality of discrete charge storage segments comprise a plurality of floating gates. The method according to claim 1,
The semiconductor channel having a columnar shape,
Wherein the entirety of the semiconductor channel in the columnar form extends perpendicular to the major surface of the substrate. The method of claim 3,
One source or drain electrode contacting at the top of the columnar semiconductor channel, and
Further comprising another source or drain electrode in contact with a lower portion of the columnar semiconductor channel. The method according to claim 1,
Wherein the tunnel dielectric does not extend into an opening in the blocking dielectric segments of the 'C' shape. A semiconductor channel in which at least one end extends perpendicularly to a major surface of the substrate;
A plurality of control gate electrodes having a strip shape extending parallel to the main surface of the substrate, wherein the plurality of control gate electrodes comprises a first control gate electrode located at a first device level and a second control gate electrode located at a second device level Wherein the second device level is located below the first device level and above the major surface of the substrate;
A blocking dielectric comprising a plurality of blocking dielectric segments, each of the plurality of blocking dielectric segments being positioned in contact with each of the plurality of control gate electrodes;
Wherein at least one of the plurality of discrete charge storage segments comprises at least one of a plurality of discrete charge storage segments defined by a sidewall of the first control gate electrode, a sidewall of the first insulating layer, and a sidewall of the second insulating layer. Wherein the first insulating layer is disposed over the first control gate electrode and the second insulating layer is disposed under the first control gate electrode, and the plurality of discrete charge storage segments A first separated charge storage segment located at a first device level and a second separated charge storage segment located at a second device level; And
And a tunnel dielectric disposed between each of the plurality of discrete charge storage segments and the semiconductor channel. The method according to claim 6,
Wherein the blocking dielectric is disposed between the first control gate electrode and at least one of the separated charge storage segments. The method according to claim 6,
At least a portion of each of the plurality of blocking dielectric segments having a " C " shape. The method according to claim 6,
Wherein the plurality of discrete charge storage segments comprise a plurality of floating gates. The method according to claim 6,
The semiconductor channel having a columnar shape,
Wherein the entirety of the columnar semiconductor channel extends perpendicular to the major surface of the substrate. 11. The method of claim 10,
One source or drain electrode contacting at the top of the columnar semiconductor channel, and
Further comprising another source or drain electrode in contact with a lower portion of the columnar semiconductor channel. 9. The method of claim 8,
Wherein the tunnel dielectric does not extend into the " C " shaped blocking dielectric segments.

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