KR101615769B1 - Liquid Crystal Display And Driving Method Thereof - Google Patents

Abstract

The present invention relates to a horizontal electric field type liquid crystal display device capable of improving contrast characteristics of an input image.

The horizontal electric field type liquid crystal display device includes a liquid crystal display panel in which a plurality of data lines and a plurality of gate lines cross each other and liquid crystal cells are formed in a matrix form in each of the intersection regions; A data driving circuit for supplying a data voltage to the data lines; A gate driving circuit for supplying a scan pulse to the gate lines to select a horizontal line to which the data voltage is supplied; An input image analysis unit for controlling a logic level of a switch control signal differently based on an analysis result of an input image; A first gate high voltage, a gate low voltage, and a second gate high voltage between the first gate high voltage and the gate low voltage; And a VGH adjusting circuit for selectively supplying the first gate high voltage and the second gate high voltage to the gate driving circuit in accordance with the logic level of the switch control signal to adjust a turn-on level of the scan pulse.

Description

TECHNICAL FIELD [0001] The present invention relates to a horizontal electric field type liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a horizontal electric field type liquid crystal display capable of improving contrast characteristics of an input image and a driving method thereof.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. The liquid crystal display panel includes a liquid crystal cell Clc at the intersection of the gate line GL and the data line DL and the gate line GL and the data line GL as shown in FIG. A thin film transistor (hereinafter referred to as "TFT") is formed. A storage capacitor Cst for holding the voltage of the liquid crystal cell Clc is formed in the liquid crystal display panel. The liquid crystal cell Clc includes a pixel electrode, a common electrode, and a liquid crystal layer. An electric field is applied to the liquid crystal layer of the liquid crystal cells Clc by the data voltage applied to the pixel electrode and the common voltage Vcom applied to the common electrode. And the amount of light passing through the liquid crystal layer is controlled by this electric field, thereby realizing an image.

Such a liquid crystal display device is divided into a vertical electric field type and a horizontal electric field type in accordance with the direction of the electric field for driving the liquid crystal. In a vertical electric field type liquid crystal display device, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are disposed opposite to each other, and a liquid crystal of a TN (Twisted Nematic) mode is driven by a vertical electric field formed therebetween. The liquid crystal of the TN mode operates in a normally white mode in which transmittance or gradation becomes higher as the data voltage becomes smaller. In a horizontal electric field type liquid crystal display device, a liquid crystal of an IPS (In Plane Switch) mode is driven by a horizontal electric field between a pixel electrode arranged in parallel with a lower substrate and a common electrode. The liquid crystal of the IPS mode operates in a normally black mode in which the transmittance or the gray level is increased as the data voltage is increased. Such a horizontal electric field type liquid crystal display device has a wide viewing angle as compared with a vertical electric field type liquid crystal display device.

However, the horizontal electric field type liquid crystal display device has a problem that the contrast value of the input image is deteriorated due to a higher luminance value in the low gradation period including the black gradation compared with the vertical electric field in which the liquid crystal is twisted.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a horizontal electric field type liquid crystal display device and a driving method thereof that can improve contrast characteristics of an input image.

In order to achieve the above object, a horizontal electric field type liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel in which a plurality of data lines and a plurality of gate lines cross each other and liquid crystal cells are formed in a matrix form for each of the intersection regions; A data driving circuit for supplying a data voltage to the data lines; A gate driving circuit for supplying a scan pulse to the gate lines to select a horizontal line to which the data voltage is supplied; An input image analysis unit for controlling a logic level of a switch control signal differently based on an analysis result of an input image; A first gate high voltage, a gate low voltage, and a second gate high voltage between the first gate high voltage and the gate low voltage; And a VGH adjusting circuit for selectively supplying the first gate high voltage and the second gate high voltage to the gate driving circuit in accordance with the logic level of the switch control signal to adjust a turn-on level of the scan pulse.

Wherein the input image analyzing unit analyzes the data of the input image to calculate a frame representative value and compares the frame representative value with a predetermined reference value to determine a gradation of the input image; If the frame representative value is greater than or equal to a reference value, determining the input image as a normal gradation image and generating the switch control signal at a first logic level; If the frame representative value is smaller than the reference value, the input image is determined as a low gray level image, and the switch control signal is generated at a second logic level different from the first logic level.

Wherein the VGH adjusting circuit comprises: a first power supply terminal to which the first gate high voltage is input; A first switch element connected between the first power supply terminal and the output node and switched in response to the switch control signal; A second power supply terminal to which the second gate high voltage is input; An inverter for inverting the switch control signal; And a second switch element connected between the second power supply terminal and the output node and switched in response to the inverted switch control signal.

The first and second switch elements are implemented as N-type MOSFETs.

Wherein the VGH adjusting circuit comprises: a first power supply terminal to which the first gate high voltage is input; An inverter for inverting the switch control signal; A first switch element connected between the first power supply terminal and the output node and switched in response to the inverted switch control signal; A second power supply terminal to which the second gate high voltage is input; And a second switch element connected between the second power supply terminal and the output node and switched in response to the switch control signal.

The first and second switch elements are implemented as P-type MOSFETs.

The reference value is set to a gradation value capable of exhibiting a luminance of 1% with respect to the luminance at the time of implementing the peak white gradation.

According to an embodiment of the present invention, a plurality of data lines to which a data voltage is supplied and a plurality of gate lines to which a scan pulse is supplied to select a horizontal line to which the data voltage is supplied are crossed, A method of driving a horizontal electric field type liquid crystal display in which cells are formed in a matrix form includes: (A) controlling a logic level of a switch control signal differently based on an analysis result of an input image; (B) generating a first gate high voltage, a gate low voltage, and a second gate high voltage between the first gate high voltage and the gate low voltage; And a step (C) of selectively outputting the first gate high voltage and the second gate high voltage according to a logic level of the switch control signal to adjust a turn-on level of the scan pulse.

A horizontal electric field type liquid crystal display device and a driving method thereof according to the present invention analyze a gray level of an input image to lower a turn-on level of a scan pulse in a low gray level image compared to a normal gray level image, The charge amount of the data voltage to be applied is reduced in the low-gradation image as compared with the normal gradation image. Accordingly, the horizontal electric field type liquid crystal display device and the driving method thereof according to the present invention can lower the luminance in the low-gray-scale image, thereby greatly improving the contrast characteristic of the input image.

Further, the horizontal electric field type liquid crystal display and the driving method thereof according to the present invention can reduce the power consumption of the gate driving circuit by lowering the turn-on level of the scan pulse in the low gray level image.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 7. FIG.

2 shows a horizontal electric field type liquid crystal display device according to an embodiment of the present invention.

2, the horizontal electric field type liquid crystal display according to the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, a power supply circuit 14, a VGH An adjustment circuit 15, and a backlight unit 16.

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. In the liquid crystal display panel, a plurality of liquid crystal cells Clc are formed in a matrix form by an intersection structure of a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn.

In the lower glass substrate of the liquid crystal display panel 10, the data lines D1 to Dm, the gate lines G1 to Gn, the TFTs, the pixel electrodes 1 connected to the TFTs, Common electrodes 2 that are horizontally opposed to each other, and storage capacitors Cst are formed. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and the like are formed. A horizontal electric field is applied to the liquid crystal layer by the data voltage applied to the pixel electrode 1 and the common voltage Vcom applied to the common electrode 2. [ By this horizontal electric field, the liquid crystal molecules of the liquid crystal layer can be changed in arrangement, and the light amount of the transmitted light can be controlled. The liquid crystal molecules are operated in a normally black mode in which the transmittance or the gray level is increased as the data voltage is increased. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10 and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The timing controller 11 arranges data RGB of an input image supplied from an external system board to the data driving circuit 12 according to the resolution of the liquid crystal display panel 10. The timing controller 11 is connected to the data driving circuit 12 (not shown) based on a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock CLK, A source control signal SDC for controlling the operation timing of the gate driving circuit 13 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13. [ The timing controller 11 inserts an interpolation frame between the frames of the input image input at a frame frequency of 60 Hz and multiplies the source control signal SDC and the gate control signal GDC to obtain 60 × N The operation of the data driving circuit 12 and the gate driving circuit 13 can be controlled with a frame frequency of Hz.

The timing controller 11 includes an input image analysis unit 11a for analyzing the gradation of an input image. The input image analyzing unit 11a analyzes the input image data (RGB) on a frame-by-frame basis, calculates a histogram of the frame, i.e., a cumulative distribution function, and calculates a frame representative value such as an average value and a mode value of the cumulative distribution function . The input image analyzing unit 11a determines the gray level of the input image by comparing the frame representative value with a predetermined reference value, and changes the logic level of the switch control signal SWC according to the determination result. For example, if the frame representative value is equal to or greater than the reference value, the input image analyzing unit 11a determines that the input image is a normal gradation image and generates the switch control signal SWC at the first logic level. On the other hand, if the frame representative value is smaller than the reference value, the input image analyzing unit 11a determines that the input image is a low gray level image, and generates the switch control signal SWC at a second logic level different from the first logic level. Here, the reference value can be set to a tone value that can exhibit a luminance of 1% with respect to the luminance at the time of implementation of peak white gradation. Preferably, the reference value can be set to a tone value which can exhibit a luminance of 0.3% to 0.4% of the luminance in the peak white gradation implementation.

The data driving circuit 12 includes a plurality of source drive ICs. Each of the source drive ICs samples and latches data (RGB) of an input image supplied from the timing controller 11 in response to a source control signal SDC from the timing controller 11, and converts the sampled data into parallel system data. Each of the source drive ICs converts the data converted into the parallel system into an analog gamma compensation voltage using the positive / negative polarity gamma reference voltages VGMA1 to VGMA10 from the power supply circuit 14 to charge the liquid crystal cells Positive / negative analog video data voltages are generated. Each of the source drive ICs inverts the polarity of the positive / negative analog video data voltage under the control of the timing controller 11 and supplies the data voltage to the data lines D1 to Dm.

The gate drive circuit 13 includes a plurality of gate drive ICs. Each of the gate drive ICs includes a shift register that sequentially shifts the first gate high voltage VGH or the second gate high voltage VGH 'in response to the gate control signal GDC from the timing controller 11 And sequentially supplies scan pulses to the gate lines. The scan pulse is swung between the first gate high voltage VGH and the gate low voltage VGL or swung between the second gate high voltage VGH 'and the gate low voltage VGL to supply the data voltage Select the horizontal line.

The power supply circuit 14 generates voltages necessary for driving the liquid crystal display panel 10 by adjusting a voltage Vin input from the system board. The power supply circuit 14 includes a high power supply voltage Vdd of 8 V or less, a logic power supply voltage VCC of about 3.3 V, a first gate high voltage VGH of 15 V or higher, a gate low voltage VGL of -3 V or lower, The second gate high voltage VGH 'between the first gate high voltage VGH and the gate low voltage VGL, the common voltage Vcom between 7V and 8V, the positive / negative polarity gamma reference voltages VGMA1- VGMA10) and the like.

The VGH adjustment circuit 15 outputs the first gate high voltage VGH and the second gate high voltage VGH 'inputted from the power supply circuit 14 in response to the switch control signal SWC from the input image analysis unit 11a, ) To the gate drive circuit (13).

The backlight unit 16 includes a plurality of light sources to irradiate the liquid crystal display panel 10 with light. The backlight unit 16 may be implemented as either a direct type or an edge type. The direct-type backlight unit 16 has a structure in which a plurality of optical sheets and a diffusion plate are stacked under the liquid crystal display panel 10, and a plurality of light sources are disposed under the diffusion plate. The edge type backlight unit 16 has a structure in which a plurality of optical sheets and a light guide plate are stacked below a liquid crystal display panel 10 and a plurality of light sources are disposed on a side surface of the light guide plate. The light sources may be implemented as light sources such as a cold cathode fluorescent lamp (CCFL) or an external electrode fluorescent lamp (EEFL), and may be implemented as a light emitting diode (LED) Light sources. The light sources may be driven block by block or individually based on the PWM signal.

Fig. 3 shows an example of the VGH adjusting circuit 15. Fig.

3, the VGH regulating circuit 15 includes a first power supply terminal 151 to which a first gate high voltage VGH is input, a second power supply terminal 151 to which a first power supply terminal 151 and an output node No are connected A first switch element SW1 switched in response to a switch control signal SWC, a second power supply terminal 152 receiving a second gate high voltage VGH ', and a switch control signal SWC And an inverter INV and a second switch element SW2 connected between the second power supply terminal 152 and the output node No and switched in response to the inverted switch control signal SWC. The first and second switch elements SW1 and SW2 may be implemented as N-type MOSFETs.

The operation of the VGH adjusting circuit 15 will now be described with reference to FIGS. 4A and 4B.

When the switch control signal SWC is input at the first logic level H corresponding to the normal gradation image, the first switch element SW1 is turned on and the second switch element SW2 is turned off. As a result, the VGH regulating circuit 15 supplies the first gate high voltage VGH to the gate driving circuit through the output node No as shown in Fig. 4A. The scan pulse is generated at the first gate high voltage VGH during the turn-on period, thereby maintaining the charged level of the data voltage applied to the pixel electrode 1 through the TFT of the liquid crystal cell at the first level, as shown in FIG.

When the switch control signal SWC is input to the second logic level L in response to the low gray level image, the first switch element SW1 is turned off and the second switch element SW2 is turned on. As a result, the VGH regulating circuit 15 supplies the second gate high voltage VGH 'to the gate driving circuit through the output node No as shown in FIG. 4B. The scan pulse is generated at the second gate high voltage VGH 'during the turn-on period, so that the charge amount of the data voltage applied to the pixel electrode 1 through the TFT of the liquid crystal cell, as shown in FIG. 5, Level.

5, the horizontal axis represents the gate voltage (Vg) applied to the gate electrode of the TFT, and the vertical axis represents the current (Id) flowing between the drain electrode and the source electrode of the TFT. The TFT current Id that is directly connected to the charging capability is proportional to the gate voltage Vg applied to the gate electrode. Therefore, when the gate voltage Vg is lowered, the TFT current Id is decreased correspondingly, It is easy to see that the charged amount of the data voltage applied to the memory cell is reduced.

Fig. 6 shows another example of the VGH adjusting circuit 15. Fig.

6, the VGH regulating circuit 15 includes a first power supply terminal 151 to which a first gate high voltage VGH is input, an inverter INV that inverts the switch control signal SWC, A first switch element SW1 connected between the supply terminal 151 and the output node No and switched in response to the inverted switch control signal SWC and a second switch element SW2 connected between the supply terminal 151 and the output node No in response to the second gate high voltage VGH ' A power supply terminal 152 and a second switch element SW2 connected between the second power supply terminal 152 and the output node No and being switched in response to the switch control signal SWC. The first and second switch elements SW1 and SW2 may be implemented as a P-type MOSFET.

The operation of the VGH regulating circuit 15 is substantially the same as in Figs. 4A and 4B.

FIG. 7 shows a method of driving a horizontal electric field type liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 7, the driving method includes analyzing data (RGB) of an input image frame by frame and calculating a histogram of the frame, that is, a cumulative distribution function, and calculating a frame representative value such as an average value and a mode value of the cumulative distribution function (S10, S20)

If the frame representative value is greater than or equal to the reference value ("NO" in FIG. 7), the driving method determines the gradation of the input image by comparing the representative value of the frame with a predetermined reference value. (S40) and generates the switch control signal at the first logic level to output the first gate high voltage (VGH). (S50) If the frame representative value is smaller than the reference value (S60), the switch control signal is generated at the second logic level and the second gate high voltage VGH (VGH) lower than the first gate high voltage VGH is generated ') (S70)

This driving method generates a scan pulse whose turn-on level is the first gate high voltage (VGH) corresponding to the normal gradation image, thereby maintaining the charged amount of the data voltage applied to the pixel electrode through the TFT of the liquid crystal cell at the first level (S80) This driving method generates a scan pulse whose turn-on level is the second gate high voltage (VGH ') corresponding to the low gray level image, so that the charge amount of the data voltage applied to the pixel electrode through the TFT of the liquid crystal cell To a second level lower than the first level. (S80)

As described above, the horizontal electric field type liquid crystal display device and the driving method thereof according to the present invention analyze the gradation of the input image and lower the turn-on level of the scan pulse in the low gradation image compared to the normal gradation image, The charge amount of the data voltage applied to the pixel electrode is reduced in the low gray level image as compared with the normal gray level image. Accordingly, the horizontal electric field type liquid crystal display device and the driving method thereof according to the present invention can lower the luminance in the low-gray-scale image, thereby greatly improving the contrast characteristic of the input image.

Further, the horizontal electric field type liquid crystal display and the driving method thereof according to the present invention can reduce the power consumption of the gate driving circuit by lowering the turn-on level of the scan pulse in the low gray level image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a circuit diagram showing a pixel equivalently in a liquid crystal display device;

2 is a block diagram showing a horizontal electric field type liquid crystal display device according to an embodiment of the present invention.

3 is a circuit diagram showing an example of a VGH adjustment circuit;

4A and 4B are circuit diagrams showing the operation of the VGH regulating circuit.

5 is a graph showing current characteristics of a TFT according to a gate voltage.

6 is a circuit diagram showing another example of the VGH adjustment circuit;

7 is a flowchart illustrating a method of driving a horizontal electric field type liquid crystal display device according to an embodiment of the present invention.

Description of the Related Art

10: liquid crystal display panel 11: timing controller

12: data driving circuit 13: gate driving circuit

14: power supply circuit 15: VGH adjustment circuit

16: backlight unit 11a: input image analyzing unit

Claims (10)

A liquid crystal display panel in which a plurality of data lines and a plurality of gate lines cross each other and liquid crystal cells are formed in a matrix form for each of the intersection regions; A data driving circuit for supplying a data voltage to the data lines; A gate driving circuit for supplying a scan pulse to the gate lines to select a horizontal line to which the data voltage is supplied; An input image analysis unit for controlling a logic level of a switch control signal differently based on an analysis result of an input image; A first gate high voltage, a gate low voltage, and a second gate high voltage between the first gate high voltage and the gate low voltage; And And a VGH adjustment circuit for selectively supplying the first gate high voltage and the second gate high voltage to the gate driving circuit in accordance with the logic level of the switch control signal to adjust the turn-on level of the scan pulse Wherein the liquid crystal display device is a liquid crystal display device. The method according to claim 1, Wherein the input image analyzing unit comprises: Calculating a representative value of a frame by analyzing data of the input image and comparing the representative value of the frame with a predetermined reference value to determine a gradation of the input image; If the frame representative value is greater than or equal to a reference value, determining the input image as a normal gradation image and generating the switch control signal at a first logic level; And generates the switch control signal at a second logic level different from the first logic level when the frame representative value is smaller than the reference value. 3. The method of claim 2, Wherein the VGH adjusting circuit comprises: A first power supply terminal to which the first gate high voltage is input; A first switch element connected between the first power supply terminal and the output node and switched in response to the switch control signal; A second power supply terminal to which the second gate high voltage is input; An inverter for inverting the switch control signal; And And a second switch element connected between the second power supply terminal and the output node and switched in response to the inverted switch control signal, Wherein the first and second switch elements are implemented as N-type MOSFETs. delete 3. The method of claim 2, Wherein the VGH adjusting circuit comprises: A first power supply terminal to which the first gate high voltage is input; An inverter for inverting the switch control signal; A first switch element connected between the first power supply terminal and the output node and switched in response to the inverted switch control signal; A second power supply terminal to which the second gate high voltage is input; And And a second switch element connected between the second power supply terminal and the output node and being switched in response to the switch control signal, Wherein the first and second switch elements are implemented as P-type MOSFETs. delete 3. The method of claim 2, Wherein the reference value is set to a grayscale value capable of exhibiting a luminance of 1% with respect to a luminance at the time of implementation of a peak white grayscale. A plurality of data lines to which a data voltage is supplied and a plurality of gate lines to which a scan pulse is supplied to select a horizontal line to which the data voltage is supplied are crossed and a horizontal electric field A driving method of a liquid crystal display device, comprising: (A) controlling the logic level of the switch control signal differently based on the analysis result of the input image; (B) generating a first gate high voltage, a gate low voltage, and a second gate high voltage between the first gate high voltage and the gate low voltage; And (C) selectively outputting the first gate high voltage and the second gate high voltage according to a logic level of the switch control signal to adjust a turn-on level of the scan pulse. A method of driving a liquid crystal display device. 9. The method of claim 8, In the step (A), the frame representative value is calculated by analyzing the input image data, and the frame representative value is compared with a predetermined reference value. If the frame representative value is equal to or greater than the reference value, the input image is determined as a normal gradation image Generating the switch control signal at a first logic level and determining that the input image is a low gray level image if the frame representative value is smaller than a reference value to generate the switch control signal at a second logic level different from the first logic level ; Wherein the step (C) comprises: outputting the first gate high voltage in response to the switch control signal of the first logic level and outputting the second gate high voltage in response to the switch control signal of the second logic level And a driving method of the horizontal electric field type liquid crystal display device. 10. The method of claim 9, Wherein the reference value is set to a gray level value capable of exhibiting a luminance of 1% with respect to a luminance at the time of implementing peak white gradation.

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