KR101612220B1 - Method for fabricating semiconductor package and semiconductor package using the same - Google Patents

Method for fabricating semiconductor package and semiconductor package using the same Download PDF

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Publication number
KR101612220B1
KR101612220B1 KR1020150024957A KR20150024957A KR101612220B1 KR 101612220 B1 KR101612220 B1 KR 101612220B1 KR 1020150024957 A KR1020150024957 A KR 1020150024957A KR 20150024957 A KR20150024957 A KR 20150024957A KR 101612220 B1 KR101612220 B1 KR 101612220B1
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KR
South Korea
Prior art keywords
interposer
cover layer
semiconductor die
post
chemical vapor
Prior art date
Application number
KR1020150024957A
Other languages
Korean (ko)
Inventor
김도형
박대준
박정수
김시원
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020150024957A priority Critical patent/KR101612220B1/en
Priority to TW112137633A priority patent/TW202407917A/en
Priority to US15/049,872 priority patent/US9633939B2/en
Priority to TW105105242A priority patent/TWI726867B/en
Application granted granted Critical
Publication of KR101612220B1 publication Critical patent/KR101612220B1/en

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

One embodiment of the present invention provides a method for fabricating a semiconductor package capable of forming a thin semiconductor package, and a semiconductor package using the same. To this end, one embodiment of the present invention discloses the method including the following steps of: (A) forming an interposer on a wafer; (B) forming at least one conductive pad and at least one post on the interposer; (C) placing at least one semiconductor die on the interposer to be electrically connected with the conductive pad; (D) forming a cover layer on the exterior surface of the semiconductor die and the post; (E) encapsulating the post and the semiconductor die together on the interposer with an encapsulant; and (F) exposing the post to the exterior of the cover layer.

Description

반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지{Method for fabricating semiconductor package and semiconductor package using the same}TECHNICAL FIELD [0001] The present invention relates to a semiconductor package manufacturing method and a semiconductor package using the same,

본 발명은 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package manufacturing method and a semiconductor package using the same.

전기전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 패키지를 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 패키지를 제공하기 위한 방법으로서는 메모리 칩의 용량 증대, 다시 말해, 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 다이의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다.2. Description of the Related Art [0002] Various miniaturization of electrical and electronic products and high performance are required, and various technologies for providing a high-capacity semiconductor package have been researched and developed. One way to provide a high-capacity semiconductor package is to increase the capacity of the memory chip, that is, the high integration of the memory chip, and such a high integration can be realized by integrating a larger number of cells in the space of the limited semiconductor die .

그러나 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선 폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 반도체 다이를 적층(stack)하는 기술이 제안되었으며, 차세대 패키지로 다수의 반도체 다이가 형성된 웨이퍼 레벨에서 패키지를 제작하는 기술이 제안되었다.However, such a high integration of the memory chip requires high technology and a lot of development time, such as requiring a precise line width. Therefore, as another method for providing a high-capacity semiconductor module, a technique for stacking semiconductor dies has been proposed, and a technique for fabricating a package at a wafer level in which a plurality of semiconductor dies are formed in a next generation package has been proposed.

본 발명의 일 실시예는 반도체 패키지를 박형화할 수 있는 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 제공한다.One embodiment of the present invention provides a semiconductor package manufacturing method capable of thinning a semiconductor package and a semiconductor package using the same.

또한, 본 발명의 일 실시예는 포스트의 도전성 이온이 반도체 다이로 확산되는 것을 방지할 수 있는 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 제공한다.Also, an embodiment of the present invention provides a semiconductor package manufacturing method and a semiconductor package using the same, which can prevent diffusion of conductive ions of a post into a semiconductor die.

또한, 본 발명의 일 실시예는 반도체 제조 공정 중 발생하는 뒤틀림이나 휨 현상(warpage)을 방지할 수 있는 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 제공한다.Also, an embodiment of the present invention provides a semiconductor package manufacturing method and a semiconductor package using the same, which can prevent warpage and warpage that occur during a semiconductor manufacturing process.

본 발명의 일 실시예에 따른 반도체 패키지 제조 방법은 웨이퍼 상에 인터포저를 형성하는 단계(A), 인터포저 상에 적어도 하나의 도전성 패드 및 적어도 하나의 포스트를 형성하는 단계(B), 상기 도전성 패드에 전기적으로 연결되도록 상기 인터포저 상에 적어도 하나의 반도체 다이를 배치하는 단계(C), 상기 반도체 다이 및 포스트의 외면에 커버층을 형성하는 단계(D), 상기 인터포저 상에서 상기 포스트 및 상기 반도체 다이를 함께 인캡슐란트로 인캡슐레이션하는 단계(E) 및 상기 포스트를 상기 커버층 외부로 노출하는 단계(F)를 포함한다.A method of fabricating a semiconductor package according to an embodiment of the present invention includes the steps of (A) forming an interposer on a wafer, (B) forming at least one conductive pad and at least one post on the interposer, (C) placing at least one semiconductor die on the interposer so as to be electrically connected to the pad, (D) forming a cover layer on the outer surface of the semiconductor die and the post, Encapsulating the semiconductor die together with encapsulant (E) and exposing the post to the outside of the cover layer (F).

상기 (F)단계는 상기 포스트가 노출되도록 상기 인캡슐란트를 그라인딩할 수 있다.The step (F) may grind the encapsulant to expose the post.

상기 (B)단계 내지 (F)단계에서, 상기 포스트의 높이는 상기 반도체 다이의 높이 보다 크게 형성되어, 상기 인캡슐란트를 그라인딩 시 상기 포스트 상면의 커버층은 제거 되고, 상기 반도체 다이의 상면의 커버층은 존재할 수 있다.Wherein the height of the posts is greater than the height of the semiconductor die so that when the encapsulant is ground, the cover layer on the upper surface of the posts is removed, Layers can exist.

상기 (F)단계는 상기 포스트가 노출되도록 상기 포스트의 상부 영역만 선택적으로 식각할 수 있다.In the step (F), only the upper region of the post may be selectively etched so that the posts are exposed.

상기 (D)단계에서, 상기 커버층은 화학기상증착법(CVD; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD; Metal Organic Chemical Vapor Deposition), 원자층 증착법(ALD; Atomic Layer Deposition), 저기압 화학기상증착법(LPCVD; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD; Plasma Enhanced Chemical Vapor Deposition) 중에서 선택된 1종의 방법으로 형성될 수 있다.In step (D), the cover layer may be formed by a chemical vapor deposition (CVD) method, a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, May be formed by one method selected from LPCVD (Low Pressure Chemical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition).

상기 (D)단계에서, 상기 커버층은 절연체일 수 있다.In the step (D), the cover layer may be an insulator.

상기 커버층은 SiN, SiO2 또는 폴리머 중에서 하나 이상이 선택되어 형성될 수 있다.The cover layer may be formed of at least one selected from SiN, SiO 2, or a polymer.

상기 (D)단계에서, 상기 커버층은 하나 이상으로 적층된 레이어로 형성될 수 있다.In the step (D), the cover layer may be formed of one or more laminated layers.

상기 (F)단계 이후, 상기 웨이퍼를 제거하고, 상기 인터포저에 전기적으로 연결되도록 하부에 적어도 하나의 솔더볼을 부착하는 단계(G)를 더 포함할 수 있다.After the step (F), the step (G) may further include removing the wafer and attaching at least one solder ball to the lower part so as to be electrically connected to the interposer.

상기 (G)단계 이후, 상기 다수의 반도체 다이가 낱개로 분리되도록, 상기 인터포저를 소잉하는 단계(H)를 더 포함할 수 있다.The method may further include, after the step (G), sowing the interposer (H) so that the plurality of semiconductor dies are separated one by one.

상기 (C)단계에서, 상기 반도체 다이와 인터포저 사이에는 언더필이 충진 후 경화될 수 있다.
In the step (C), an underfill may be filled between the semiconductor die and the interposer and then cured.

본 발명의 일 실시예에 따른 반도체 패키지는 인터포저, 상기 인터포저 상에 형성된 적어도 하나의 도전성 패드 및 적어도 하나의 포스트, 상기 도전성 패드에 전기적으로 연결되도록 상기 인터포저 상에 형성된 적어도 하나의 반도체 다이, 상기 반도체 다이 및 포스트의 외면을 덮는 커버층 및 상기 인터포저 상에서, 상기 포스트 및 상기 반도체 다이를 인캡슐레이션하는 인캡슐란트를 포함하고, 상기 포스트의 일측은 상기 커버층 및 인캡슐란트의 외부로 노출된다.A semiconductor package according to an embodiment of the present invention includes an interposer, at least one conductive pad formed on the interposer and at least one post, at least one semiconductor die formed on the interposer to be electrically connected to the conductive pad, A cover layer covering the outer surface of the semiconductor die and the post, and an encapsulant encapsulating the post and the semiconductor die on the interposer, wherein one side of the post is exposed to the outside of the cover layer and the encapsulant Lt; / RTI >

상기 포스트의 높이는 상기 반도체 다이의 높이 보다 크게 형성될 수 있다The height of the posts may be greater than the height of the semiconductor die

상기 포스트의 상부 영역만 선택적으로 식각될 수 있다.Only the upper region of the post can be selectively etched.

상기 커버층은 화학기상증착법(CVD; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD; Metal Organic Chemical Vapor Deposition), 원자층 증착법(ALD; Atomic Layer Deposition), 저기압 화학기상증착법(LPCVD; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD; Plasma Enhanced Chemical Vapor Deposition) 중에서 선택된 1종의 방법으로 형성될 수 있다.The cover layer may be formed by a chemical vapor deposition (CVD) method, a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, a low pressure chemical vapor deposition (LPCVD) Chemical Vapor Deposition (PECVD), and Plasma Enhanced Chemical Vapor Deposition (PECVD).

상기 커버층은 절연체일 수 있다.The cover layer may be an insulator.

상기 커버층은 SiN, SiO2 또는 폴리머 중에서 하나 이상이 선택되어 형성될 수 있다.The cover layer may be formed of at least one selected from SiN, SiO 2, or a polymer.

상기 커버층은 하나 이상으로 적층된 레이어로 형성될 수 있다.The cover layer may be formed of one or more laminated layers.

상기 인터포저에 전기적으로 연결되도록 하부에 부착된 적어도 하나의 솔더볼을 더 포함할 수 있다.And at least one solder ball attached at the bottom to be electrically connected to the interposer.

상기 반도체 다이와 인터포저 사이에는 언더필이 충진 후 경화될 수 있다.Between the semiconductor die and the interposer, underfill can be filled and then cured.

본 발명의 일 실시예에 따른 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지는 박형화될 수 있다.The method of manufacturing a semiconductor package and the semiconductor package using the same according to an embodiment of the present invention can be made thin.

또한, 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지는 포스트의 도전성 이온이 반도체 다이로 확산되는 것을 방지할 수 있다.In addition, the method of fabricating a semiconductor package and the semiconductor package using the same according to an embodiment of the present invention can prevent the conductive ions of the post from diffusing into the semiconductor die.

또한, 본 발명의 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지는 반도체 제조 공정 중 발생하는 뒤틀림이나 휨 현상(warpage)을 방지할 수 있다.Also, the method of manufacturing a semiconductor package and the semiconductor package using the same according to an embodiment of the present invention can prevent warpage or warpage during a semiconductor manufacturing process.

도 1 내지 도 9는 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법을 순차적으로 도시한 부분 단면도이다.
도 10 내지 도 17은 본 발명의 다른 실시예에 따른 반도체 패키지 제조 방법을 순차적으로 도시한 부분 단면도이다.1 to 9 are partial cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.
10 to 17 are partial cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to another embodiment of the present invention.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

본 명세서에서 사용된 바와 같이, 용어 "및/또는"은 해당 열거된 항목 중 어느 하나 및 하나 이상의 모든 조합을 포함한다. 또한, 본 명세서에서 사용된 용어는 특정 실시예를 설명하기 위하여 사용되며, 본 발명을 제한하기 위한 것이 아니다. 더불어, 본 명세서에서 사용된 바와 같이, 단수 형태는 문맥상 다른 경우를 분명히 지적하는 것이 아니라면, 복수의 형태를 포함할 수 있다. 더욱이, 본 명세서에서 사용되는 경우 "포함한다(comprise)" 및/또는 "포함하는(comprising)"은 언급한 단계, 동작, 부재, 요소, 수치 및/또는 이들 그룹의 존재를 특정하는 것이며, 하나 이상의 다른 단계, 동작, 부재, 요소, 수치 및 /또는 그룹들의 존재 또는 부가를 배제하는 것이 아니다.As used herein, the term "and / or" includes any and all combinations of one or more of the listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. In addition, as used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Furthermore, " comprise "and / or" comprising "as used herein specify the presence of stated steps, operations, elements, elements, numerical values and / But does not preclude the presence or addition of other steps, operations, elements, elements, numerical values and / or groups.

다음은 도 1 내지 도 9를 참조하여, 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 설명한다.1 to 9, a semiconductor package manufacturing method and a semiconductor package using the same according to an embodiment of the present invention will be described.

도 1 내지 도 9는 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법을 순차적으로 도시한 부분 단면도이다.1 to 9 are partial cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

우선, 도 1에 도시된 바와 같이, 웨이퍼(10) 상에 인터포저(100)를 형성한다. 여기서, 인터포저(100)는 웨이퍼(10) 상에 접착부재(미도시) 등을 통해 부착될 수 있다.First, as shown in FIG. 1, an interposer 100 is formed on a wafer 10. Here, the interposer 100 may be attached to the wafer 10 through an adhesive member (not shown) or the like.

상기 인터포저(100)는 웨이퍼를 이용한 반도체 제조 공정(FAB)에서 제조되어, 웨이퍼를 통해 미세선폭(100um 미만) 및 파인 피치의 배선이 가능하므로, 고밀도 배선이 가능하게 된다.The interposer 100 is fabricated in a semiconductor fabrication process (FAB) using a wafer, and can be wired with a fine line width (less than 100 um) and a fine pitch through a wafer, thereby enabling high-density wiring.

여기서, 실리콘 몸체(110)의 상면 및 하면에는 각각 보호층(111)이 형성된다. 또한, 상기 실리콘 몸체(110)에는 다수의 관통전극(120)이 형성되어 있다. 더불어, 상기 실리콘 몸체(110)의 상면에는 상기 관통전극(120)과 전기적으로 연결되며, 보호층(111) 외부로 노출된 상부 회로패턴(131)이 형성되고, 상기 실리콘 몸체(110)의 하면에는 상기 관통전극(120)과 전기적으로 연결되며, 보호층(111) 외부로 노출된 하부 회로패턴(132)이 형성된다.Here, the protective layer 111 is formed on the top and bottom surfaces of the silicon body 110, respectively. In addition, a plurality of penetrating electrodes 120 are formed in the silicon body 110. An upper circuit pattern 131 is formed on an upper surface of the silicon body 110 and is electrically connected to the penetrating electrode 120. The upper circuit pattern 131 is exposed to the outside of the protective layer 111. The lower surface of the silicon body 110 A bottom circuit pattern 132 electrically connected to the penetrating electrode 120 and exposed to the outside of the passivation layer 111 is formed.

또한, 도 2를 참조하면, 상기 실리콘 몸체(110)의 상면에는 상부 회로패턴(131)에 각각 전기적으로 연결된 도전성 패드(210) 및 포스트(220)가 형성된다.2, a conductive pad 210 and a post 220 electrically connected to the upper circuit pattern 131 are formed on the upper surface of the silicon body 110.

여기서, 상기 도전성 패드(210)는 후술할 반도체 다이와 전기적으로 연결되고, 상기 포스트(220)는 마더 보드 또는 다른 반도체 패키지에 연결될 수 있다.Here, the conductive pad 210 is electrically connected to a semiconductor die to be described later, and the post 220 may be connected to a mother board or other semiconductor package.

상기 도전성 패드(210)는 구리 및 그 등가물 중 선택된 어느 하나로 형성할 수 있으나, 본 발명에서 그 재질을 한정하는 것은 아니다. 또한, 상기 도전성 패드(210)는 스퍼터링, 진공 증착, 또는 포토 리소그래피(Photo Lithography) 공법 등으로 형성될 수 있으나, 본 발명에서 이를 한정하는 것은 아니다.The conductive pad 210 may be formed of any one selected from copper and its equivalents, but the material of the conductive pad 210 is not limited in the present invention. The conductive pad 210 may be formed by sputtering, vacuum deposition, photolithography, or the like, but the present invention is not limited thereto.

상기 포스트(220)는 상기 실리콘 몸체(110)의 상면과 대략 수직한 방향으로 세워진 기둥형으로 형성되며, 전기 및 열 전도성이 우수한 구리(Cu) 및 그 등가물 중 선택된 어느 하나로 형성되는 것이 바람직하다. 하지만, 본 발명에서 포스트(220)의 형상 및 재질을 한정하지 않음은 물론이다.The posts 220 are formed in a column shape extending in a direction substantially perpendicular to the upper surface of the silicon body 110, and are formed of any one selected from copper (Cu) having excellent electrical and thermal conductivity and equivalents thereof. However, it is needless to say that the shape and the material of the post 220 are not limited in the present invention.

이후, 도 3을 참조하면, 반도체 모듈(300)이 인터포저(100) 상에 배치된다. 3, a semiconductor module 300 is disposed on the interposer 100.

상기 반도체 모듈(300)은 반도체 다이(310), 본드 패드(320), 솔더 범프(330) 및 언더필(340)로 구성된다.The semiconductor module 300 includes a semiconductor die 310, a bond pad 320, a solder bump 330, and an underfill 340.

상기 반도체 다이(310)는 액티브층(미도시)에 전기적으로 연결된 본드 패드(320)가 노출된 하면을 가진다. 여기서, 상기 본드 패드(320)는 구리 및 그 등가물 중 선택된 어느 하나로 형성할 수 있으나, 본 발명에서 그 재질을 한정하는 것은 아니다.The semiconductor die 310 has a bottom surface on which a bond pad 320 electrically connected to an active layer (not shown) is exposed. Here, the bond pad 320 may be formed of any one selected from copper and its equivalents, but the present invention is not limited thereto.

상기 솔더 범프(330)는 리플로우 공정을 통해 본드 패드(320)와 도전성 패드(210)를 전기적 및 물리적으로 연결하며, 납/주석(Pb/Sn), 납없는 주석(Leadless Sn)등의 금속재료 및 그 등가물 중 선택된 어느 하나를 이용하여 형성할 수 있으나, 본 발명에서 그 재질을 한정하는 것은 아니다.The solder bumps 330 electrically and physically connect the bond pads 320 and the conductive pads 210 through a reflow process and may be formed of a metal such as lead / tin (Pb / Sn), leadless tin A material, and an equivalent thereof. However, the material is not limited to the material of the present invention.

상기 인터포저(100)의 상면과 반도체 다이(310)의 하면 사이에는 언더필(340)이 충진 후 경화된다.The underfill 340 is filled between the upper surface of the interposer 100 and the lower surface of the semiconductor die 310, and then cured.

상기 언더필(340)은 반도체 패키지 제조 공정 상에서 발생되는 기계적 충격 및 부식과 같은 외부의 영향으로부터 범프 접합부를 보호한다. 여기서, 상기 언더필(340)은 에폭시, 열가소성 재료, 열경화성 재료, 폴리이미드, 폴리우레탄, 폴리머릭 재료, 필링된 에폭시, 필링된 열가소성 재료, 필링된 열경화성 재료, 필링된 폴리이미드, 필링된 폴리우레탄, 필링된 폴리머릭 재료, 플럭싱 언더필 및 그 등가물 중 선택된 어느 하나로 형성할 수 있으나, 본 발명에서, 그 재질을 한정하는 것은 아니다.The underfill 340 protects the bump joint from external influences such as mechanical impact and corrosion that occur on the semiconductor package manufacturing process. Here, the underfill 340 may be formed of a material selected from the group consisting of epoxy, a thermoplastic material, a thermoset material, a polyimide, a polyurethane, a polymeric material, a filled epoxy, a filled thermoplastic material, a filled thermoset material, a filled polyimide, A filled polymeric material, a filled polymeric material, a fluxing underfill, and equivalents thereof, but the material is not limited in the present invention.

여기서, 상기 포스트(220)의 높이(H1)는 반도체 다이(310)의 높이(H2)에 비해 크게 형성되는 것이 바람직하다. 이는 후술할 그라인딩 공정에서, 반도체 다이(310)에 형성된 커버층이 제거되지 않도록 하기 위함이다.It is preferable that the height H1 of the post 220 is larger than the height H2 of the semiconductor die 310. [ This is to prevent the cover layer formed on the semiconductor die 310 from being removed in the grinding process described below.

이후, 도 4를 참조하면, 인터포저(100), 포스트(220) 및 반도체 모듈(300)을 균일하게 덮도록 커버층(400)이 형성된다.4, a cover layer 400 is formed to cover the interposer 100, the posts 220, and the semiconductor module 300 uniformly.

여기서, 상기 커버층(400)은 절연성의 SiN, SiO2 또는 폴리머 그 등가물 중 선택된 어느 하나 이상으로 형성될 수 있으며, 챔버 내에서 화학기상증착법(CVD; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD; Metal Organic Chemical Vapor Deposition), 원자층 증착법(ALD; Atomic Layer Deposition), 저기압 화학기상증착법(LPCVD; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD; Plasma Enhanced Chemical Vapor Deposition) 중에서 선택된 1종의 방법으로 형성될 수 있다. 또한, 단일 레이어가 아니라 상술한 재질로 적층된 복수의 레이어(미도시)일 수 도 있다. 다만, 본 발명에서, 상술한 재질 및 제조 방법으로 커버층(400)을 한정하는 것은 아니다.Here, the cover layer 400 may be formed of at least one selected from insulating SiN, SiO 2, and polymer equivalents thereof. The cover layer 400 may be formed by a chemical vapor deposition (CVD) method, an organometallic chemical vapor deposition A metal organic chemical vapor deposition (MOCVD), an atomic layer deposition (ALD), a low pressure chemical vapor deposition (LPCVD), and a plasma enhanced chemical vapor deposition (PECVD) Can be formed by the method of the species. Further, it may be a plurality of layers (not shown) laminated with the above-described material instead of a single layer. However, in the present invention, the cover layer 400 is not limited to the material and the manufacturing method described above.

즉, 일정 이상의 경도를 갖는 커버층(400)이 웨이퍼(10) 상부에서 인터포저(100), 포스트(220) 및 반도체 모듈(300)을 균일하게 덮고 있으므로 반도체 제조 공정 중 발생하는 뒤틀림이나 휨 현상(warpage)을 방지할 수 있다.That is, since the cover layer 400 having a hardness equal to or higher than a certain level uniformly covers the interposer 100, the post 220, and the semiconductor module 300 on the wafer 10, the warpage and warping phenomena it is possible to prevent warpage.

이후, 도 5를 참조하면, 인터포저(100)의 상부, 즉, 포스트(220), 반도체 모듈(300) 및 커버층(400)의 외주면을 인캡슐란트(20)로 인캡슐레이션한다.5, the encapsulation 20 encapsulates the upper surface of the interposer 100, that is, the outer surface of the post 220, the semiconductor module 300, and the cover layer 400.

상기 인캡슐란트(20)는 상기 포스트(220), 반도체 모듈(300) 및 커버층(400)을 완전히 봉지하여 이들이 외부의 충격 및 산화로부터 손상되지 않도록 보호한다. 여기서, 상기 인캡슐란트(20)는 몰드를 통하여 인캡슐레이션을 수행하는 에폭시 컴파운드, 디스펜서를 통하여 인캡슐레이션을 수행하는 액상 봉지재 및 그 등가물 중 선택된 어느 하나일 수 있으나, 본 발명에서 인캡슐란트(20)의 재질을 한정하는 것은 아니다.The encapsulant 20 completely encapsulates the posts 220, the semiconductor module 300 and the cover layer 400 to protect them from damage from external impact and oxidation. Here, the encapsulant 20 may be any one selected from an epoxy compound that performs encapsulation through a mold, a liquid encapsulant that performs encapsulation through a dispenser, and equivalents thereof. In the present invention, The material of the tread 20 is not limited.

이후, 도 6을 참조하면, 상기 포스트(220)가 커버층(400) 및 인캡슐란트(20)의 외면으로 노출되도록 인캡슐란트(20)의 일면을 일정 두께만큼 그라인딩하여 불필요한 부분을 제거한다. 여기서, 그라인딩 공정은 예를 들면 다이아몬드 그라인더 및 그 등가물을 이용하여 수행할 수 있으며, 본 발명에서 상기 그라인딩 방법을 한정하는 것은 아니다.Referring to FIG. 6, one side of the encapsulant 20 is ground to a certain thickness so that the posts 220 are exposed to the outer surface of the cover layer 400 and the encapsulant 20 to remove unnecessary portions . Here, the grinding process can be performed using, for example, a diamond grinder and its equivalent, and the grinding method is not limited in the present invention.

여기서, 도 3을 함께 참조하면, 상술한 바와 같이 포스트(220)의 높이(H1)가 반도체 다이(310)의 높이(H2)에 비해 크게 형성되므로, 포스트(220)를 덮는 커버층(400)이 제거되는 동안, 반도체 다이(310)를 덮는 커버층(400)은 제거되지 않을 수 있다. 3, since the height H1 of the posts 220 is greater than the height H2 of the semiconductor die 310 as described above, the cover layer 400 covering the posts 220 is formed to have a height The cover layer 400 covering the semiconductor die 310 may not be removed.

역으로 설명하면, 그라인딩 및/또는 폴리싱 공정을 통해, 인캡슐란트(20)의 일면부터 제거하는 중에 반도체 다이(310)를 덮는 커버층(400)이 노출되면, 이를 기준으로 그라인딩 및/또는 폴리싱 공정을 중지할 수 있다.Conversely, if the cover layer 400 covering the semiconductor die 310 is exposed during removal from one side of the encapsulant 20 through a grinding and / or polishing process, the grinding and / The process can be stopped.

이를 통해, 정확한 그라인딩 및 폴리싱 공정을 수행할 수 있으며, 그라인딩 및 폴리싱 공정 중 포스트(220)의 도전성 이온이 반도체 다이(310)로 확산되는 것을 방지할 수 있다.This allows precise grinding and polishing processes to be performed and preventing the conductive ions of the post 220 from diffusing into the semiconductor die 310 during the grinding and polishing process.

이후, 도 7 내지 도 8을 참조하면, 인터포저(100) 하부의 웨이퍼(10)는 제거되고, 인터포저(100)의 하부 회로패턴(132)에 전기적으로 연결되도록 솔더볼(30)이 부착된다. 여기서, 상기 솔더볼(30)은 납/주석(Pb/Sn), 납없는 주석(Leadless Sn)등의 금속재료 및 그 등가물 중 선택된 어느 하나를 이용하여 형성할 수 있으나, 본 발명에서 그 재질을 한정하는 것은 아니다.7 to 8, the wafer 10 under the interposer 100 is removed and the solder ball 30 is attached so as to be electrically connected to the lower circuit pattern 132 of the interposer 100 . Here, the solder ball 30 may be formed using any one selected from a metal material such as lead / tin (Pb / Sn), leadless tin, and the like, and equivalents thereof. However, It does not.

이후, 도 9를 참조하면, 하나의 반도체 모듈(300)과 이에 대응되는 포스트(220)를 포함하는 하나의 단일 유닛으로 구성되도록 소잉 공정을 수행하여, 본 발명의 일 실시예에 따른 반도체 패키지(1000)를 제조한다. 여기서 상기 소잉 공정은 소잉 장비(예를 들면, 블레이드 혹은 레이저 드릴링)를 통해 이루어질 수 있다.
9, a soaking process is performed to form one single unit including one semiconductor module 300 and a corresponding post 220 to form a semiconductor package 300 according to an embodiment of the present invention. 1000). Here, the sawing process may be performed through sawing equipment (for example, blade or laser drilling).

다음은 도 10 내지 도 17을 참조하여, 본 발명의 다른 실시예에 따른 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 설명한다.Next, a semiconductor package manufacturing method and a semiconductor package using the same according to another embodiment of the present invention will be described with reference to FIGS. 10 to 17. FIG.

도 10 내지 도 17은 본 발명의 다른 실시예에 따른 반도체 패키지 제조 방법을 순차적으로 도시한 부분 단면도이다.10 to 17 are partial cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to another embodiment of the present invention.

도 10을 참조하면, 웨이퍼(10) 상에 인터포저(100)를 형성한다. 여기서, 인터포저(100)는 웨이퍼(10) 상에 접착부재(미도시) 등을 통해 부착될 수 있다. 여기서, 상기 인터포저(100)는 도 1의 인터포저(100)와 동일 구성이므로, 상세한 설명은 생략한다.Referring to FIG. 10, an interposer 100 is formed on a wafer 10. Here, the interposer 100 may be attached to the wafer 10 through an adhesive member (not shown) or the like. Here, since the interposer 100 has the same configuration as the interposer 100 of FIG. 1, detailed description thereof will be omitted.

이후, 도 11을 참조하면, 상기 실리콘 몸체(110)의 상면에는 상부 회로패턴(131)에 각각 전기적으로 연결된 도전성 패드(210) 및 포스트(220)가 형성된다.Referring to FIG. 11, a conductive pad 210 and a post 220 electrically connected to the upper circuit pattern 131 are formed on the upper surface of the silicon body 110.

이후, 도 12를 참조하면, 반도체 모듈(300)이 인터포저(100) 상에 배치된다. Thereafter, referring to FIG. 12, a semiconductor module 300 is disposed on the interposer 100.

상기 반도체 모듈(300)은 반도체 다이(310), 본드 패드(320), 솔더 범프(330) 및 언더필(340)로 구성되고, 도 3의 반도체 모듈(300)과 동일 구성이므로, 상세한 설명은 생략한다. 다만, 도 3의 반도체 모듈(300)과는 달리, 포스트(220)의 높이(H1)가 반도체 다이(310)의 높이(H2)에 비해 크게 형성되지 않아도 무관하다. 이는 후술할 식각 공정에서, 포스트(220)의 상부 영역에서만 선택적으로 식각 공정을 수행하므로, 반도체 다이(310)의 높이와 무관하게, 반도체 다이(310)에 형성된 커버층이 제거되지 않을 수 있다.The semiconductor module 300 is composed of a semiconductor die 310, a bond pad 320, a solder bump 330 and an underfill 340 and has the same configuration as the semiconductor module 300 of FIG. 3, do. 3, the height H1 of the post 220 may not be formed larger than the height H2 of the semiconductor die 310. FIG. The cover layer formed on the semiconductor die 310 may not be removed regardless of the height of the semiconductor die 310 because the etch process is selectively performed only in the upper region of the post 220 in a later-described etching process.

이후, 도 13을 참조하면, 인터포저(100), 포스트(220) 및 반도체 모듈(300)을 균일하게 덮도록 커버층(400)이 형성된다. 여기서, 상기 커버층(400)은 도 4의 커버층(400)과 동일 구성이므로, 상세한 설명은 생략한다.13, a cover layer 400 is formed to cover the interposer 100, the posts 220, and the semiconductor module 300 uniformly. Here, the cover layer 400 has the same configuration as that of the cover layer 400 of FIG. 4, and a detailed description thereof will be omitted.

이후, 도 14를 참조하면, 인터포저(100)의 상부, 즉, 포스트(220), 반도체 모듈(300) 및 커버층(400)의 외주면을 인캡슐란트(20)로 인캡슐레이션한다. 상기 인캡슐란트(20)는 상기 포스트(220), 반도체 모듈(300) 및 커버층(400)을 완전히 봉지하여 이들이 외부의 충격 및 산화로부터 손상되지 않도록 보호한다. 여기서, 상기 인캡슐란트(20)는 몰드를 통하여 인캡슐레이션을 수행하는 에폭시 컴파운드, 디스펜서를 통하여 인캡슐레이션을 수행하는 액상 봉지재 및 그 등가물 중 선택된 어느 하나일 수 있으나, 본 발명에서 인캡슐란트(20)의 재질을 한정하는 것은 아니다.14, the encapsulation 20 encapsulates the upper surface of the interposer 100, that is, the outer surface of the post 220, the semiconductor module 300, and the cover layer 400. The encapsulant 20 completely encapsulates the posts 220, the semiconductor module 300 and the cover layer 400 to protect them from damage from external impact and oxidation. Here, the encapsulant 20 may be any one selected from an epoxy compound that performs encapsulation through a mold, a liquid encapsulant that performs encapsulation through a dispenser, and equivalents thereof. In the present invention, The material of the tread 20 is not limited.

이후, 도 15를 참조하면, 상기 포스트(220)의 상부 영역(21)만 선택적으로 식각하여, 포스트(220)가 커버층(400) 및 인캡슐란트(20)의 외면으로 노출되도록 한다.15, only the upper region 21 of the post 220 is selectively etched to expose the posts 220 to the outer surface of the cover layer 400 and the encapsulant 20.

여기서 상기 식각 공정은 물리적 식각 또는 화학적 식각으로 상기 포스트(220)의 상부 영역(21)을 제거할 수 있으나, 본 발명에서 상기 식각 공정을 한정하는 것은 아니다.Here, the etching process may remove the upper region 21 of the post 220 by physical etching or chemical etching, but the present invention does not limit the etching process.

이후, 도 16을 참조하면, 인터포저(100) 하부의 웨이퍼(10)는 제거되고, 인터포저(100)의 하부 회로패턴(132)에 전기적으로 연결되도록 솔더볼(30)이 부착된다. 여기서, 상기 솔더볼(30)은 납/주석(Pb/Sn), 납없는 주석(Leadless Sn)등의 금속재료 및 그 등가물 중 선택된 어느 하나를 이용하여 형성할 수 있으나, 본 발명에서 그 재질을 한정하는 것은 아니다.16, the wafer 10 under the interposer 100 is removed and the solder ball 30 is attached so as to be electrically connected to the lower circuit pattern 132 of the interposer 100. Here, the solder ball 30 may be formed using any one selected from a metal material such as lead / tin (Pb / Sn), leadless tin, and the like, and equivalents thereof. However, It does not.

이후, 도 17을 참조하면, 하나의 반도체 모듈(300)과 이에 대응되는 포스트(220)를 포함하는 하나의 단일 유닛으로 구성되도록 소잉 공정을 수행하여, 본 발명의 다른 실시예에 따른 반도체 패키지(2000)를 제조한다. 여기서 상기 소잉 공정은 소잉 장비(예를 들면, 블레이드 혹은 레이저 드릴링)를 통해 이루어질 수 있다.
17, a soaking process is performed to form one single unit including one semiconductor module 300 and a corresponding post 220 to form a semiconductor package 300 according to another embodiment of the present invention 2000). Here, the sawing process may be performed through sawing equipment (for example, blade or laser drilling).

본 발명은 상기 실시예들에 한정되지 않고 본 발명의 기술적 요지를 벗어나지 아니하는 범위 내에서 다양하게 수정, 변형되어 실시될 수 있음은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 있어서 자명한 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. It is.

10; 웨이퍼 20; 인캡슐란트
30; 솔더볼
100; 인터포저 210; 도전성 패드
220; 포스트 300; 반도체 모듈
400; 커버층10; Wafer 20; Encapsulation
30; Solder ball
100; Interposer 210; Conductive pad
220; Post 300; Semiconductor module
400; Cover layer

Claims (20)

웨이퍼 상에 인터포저를 형성하는 단계(A);
인터포저 상에 적어도 하나의 도전성 패드 및 적어도 하나의 포스트를 형성하는 단계(B);
상기 도전성 패드에 전기적으로 연결되도록 상기 인터포저 상에 적어도 하나의 반도체 다이를 배치하는 단계(C);
상기 반도체 다이 및 포스트의 외면에 커버층을 형성하는 단계(D);
상기 인터포저 상에서 상기 포스트 및 상기 반도체 다이를 함께 인캡슐란트로 인캡슐레이션하는 단계(E); 및
상기 포스트를 상기 커버층 외부로 노출하는 단계(F)를 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.(A) forming an interposer on a wafer;
(B) forming at least one conductive pad and at least one post on the interposer;
(C) placing at least one semiconductor die on the interposer to be electrically connected to the conductive pad;
(D) forming a cover layer on an outer surface of the semiconductor die and the post;
Encapsulating the post and the semiconductor die together on an encapsulant (E) on the interposer; And
And exposing the post to the outside of the cover layer (F). 제 1항에 있어서,
상기 (F)단계는
상기 포스트가 노출되도록 상기 인캡슐란트를 그라인딩하는 것을 특징으로 하는 반도체 패키지 제조 방법.The method according to claim 1,
The step (F)
And grinding the encapsulant so that the posts are exposed. 제 2항에 있어서,
상기 (B)단계 내지 (F)단계에서,
상기 포스트의 높이는 상기 반도체 다이의 높이 보다 크게 형성되어, 상기 인캡슐란트를 그라인딩 시 상기 포스트 상면의 커버층은 제거 되고, 상기 반도체 다이의 상면의 커버층은 존재하는 것을 특징으로 하는 반도체 패키지 제조 방법.3. The method of claim 2,
In the steps (B) to (F)
Wherein the height of the posts is greater than the height of the semiconductor die such that when the encapsulant is ground the cover layer on the upper surface of the posts is removed and a cover layer on the top surface of the semiconductor die is present. . 제 1항에 있어서,
상기 (F)단계는
상기 포스트가 노출되도록 상기 포스트의 상부 영역만 선택적으로 식각하는 것을 특징으로 하는 반도체 패키지 제조 방법.The method according to claim 1,
The step (F)
Wherein only the upper region of the post is selectively etched to expose the posts. 제 1항에 있어서,
상기 (D)단계에서,
상기 커버층은 화학기상증착법(CVD; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD; Metal Organic Chemical Vapor Deposition), 원자층 증착법(ALD; Atomic Layer Deposition), 저기압 화학기상증착법(LPCVD; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD; Plasma Enhanced Chemical Vapor Deposition) 중에서 선택된 1종의 방법으로 형성되는 것을 특징으로 하는 반도체 패키지 제조 방법.The method according to claim 1,
In the step (D)
The cover layer may be formed by a chemical vapor deposition (CVD) method, a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, a low pressure chemical vapor deposition (LPCVD) Wherein the first conductive layer is formed by one of a chemical vapor deposition (CVD) method and a plasma enhanced chemical vapor deposition (PECVD) method. 제 5항에 있어서,
상기 (D)단계에서,
상기 커버층은 절연체인 것을 특징으로 하는 반도체 패키지 제조 방법.6. The method of claim 5,
In the step (D)
Wherein the cover layer is an insulator. 제 6항에 있어서,
상기 커버층은 SiN, SiO2 또는 폴리머 중에서 하나 이상이 선택되어 형성되는 것을 특징으로 하는 반도체 패키지 제조 방법.The method according to claim 6,
Wherein the cover layer is formed of at least one selected from the group consisting of SiN, SiO 2, and a polymer. 제 7항에 있어서,
상기 (D)단계에서,
상기 커버층은 하나 이상으로 적층된 레이어로 형성되는 것을 특징으로 하는 반도체 패키지 제조 방법.8. The method of claim 7,
In the step (D)
Wherein the cover layer is formed of one or more stacked layers. 제 1항에 있어서,
상기 (F)단계 이후,
상기 웨이퍼를 제거하고, 상기 인터포저에 전기적으로 연결되도록 하부에 적어도 하나의 솔더볼을 부착하는 단계(G)를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.The method according to claim 1,
After the step (F)
Further comprising: (G) removing the wafer and attaching at least one solder ball to the bottom to be electrically connected to the interposer. 제 9항에 있어서,
상기 (G)단계 이후,
상기 다수의 반도체 다이가 낱개로 분리되도록, 상기 인터포저를 소잉하는 단계(H)를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.10. The method of claim 9,
After the step (G)
Further comprising the step of sawing the interposer (H) so that the plurality of semiconductor dies are separated one by one. 제 1항에 있어서,
상기 (C)단계에서,
상기 반도체 다이와 인터포저 사이에는 언더필이 충진 후 경화되는 것을 특징으로 하는 반도체 패키지 제조 방법.The method according to claim 1,
In the step (C)
Wherein the underfill is filled between the semiconductor die and the interposer and then cured. 인터포저;
상기 인터포저 상에 형성된 적어도 하나의 도전성 패드 및 적어도 하나의 포스트;
상기 도전성 패드에 전기적으로 연결되도록 상기 인터포저 상에 형성된 적어도 하나의 반도체 다이;
상기 반도체 다이 및 포스트의 외면을 덮는 커버층; 및
상기 인터포저 상에서, 상기 포스트 및 상기 반도체 다이를 인캡슐레이션하는 인캡슐란트를 포함하고,
상기 포스트의 일측은 상기 커버층 및 인캡슐란트의 외부로 노출된 것을 특징으로 하는 반도체 패키지.Interposer;
At least one conductive pad and at least one post formed on the interposer;
At least one semiconductor die formed on the interposer to be electrically connected to the conductive pad;
A cover layer covering an outer surface of the semiconductor die and the post; And
And an encapsulant encapsulating the posts and the semiconductor die on the interposer,
And one side of the post is exposed to the outside of the cover layer and the encapsulant. 제 12항에 있어서,
상기 포스트의 높이는 상기 반도체 다이의 높이 보다 크게 형성된 것을 특징으로 하는 반도체 패키지.13. The method of claim 12,
Wherein the height of the posts is greater than the height of the semiconductor die. 제 12항에 있어서,
상기 포스트의 상부 영역만 선택적으로 식각된 것을 특징으로 하는 반도체 패키지.13. The method of claim 12,
Wherein only the upper region of the posts is selectively etched. 제 12항에 있어서,
상기 커버층은 화학기상증착법(CVD; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD; Metal Organic Chemical Vapor Deposition), 원자층 증착법(ALD; Atomic Layer Deposition), 저기압 화학기상증착법(LPCVD; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD; Plasma Enhanced Chemical Vapor Deposition) 중에서 선택된 1종의 방법으로 형성되는 것을 특징으로 하는 반도체 패키지.13. The method of claim 12,
The cover layer may be formed by a chemical vapor deposition (CVD) method, a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, a low pressure chemical vapor deposition (LPCVD) Wherein the semiconductor package is formed by one method selected from the group consisting of chemical vapor deposition (PECVD) and plasma enhanced chemical vapor deposition (PECVD). 제 15항에 있어서,
상기 커버층은 절연체인 것을 특징으로 하는 반도체 패키지.16. The method of claim 15,
Wherein the cover layer is an insulator. 제 16항에 있어서,
상기 커버층은 SiN, SiO2 또는 폴리머 중에서 하나 이상이 선택되어 형성되는 것을 특징으로 하는 반도체 패키지.17. The method of claim 16,
Wherein the cover layer is formed of at least one selected from SiN, SiO 2, or a polymer. 제 17항에 있어서,
상기 커버층은 하나 이상으로 적층된 레이어로 형성되는 것을 특징으로 하는 반도체 패키지.18. The method of claim 17,
Wherein the cover layer is formed of one or more stacked layers. 제 12항에 있어서,
상기 인터포저에 전기적으로 연결되도록 하부에 부착된 적어도 하나의 솔더볼을 더 포함하는 것을 특징으로 하는 반도체 패키지.13. The method of claim 12,
Further comprising: at least one solder ball attached to the bottom to be electrically connected to the interposer. 제 12항에 있어서,
상기 반도체 다이와 인터포저 사이에는 언더필이 충진 후 경화된 것을 특징으로 하는 반도체 패키지.13. The method of claim 12,
Wherein an underfill is filled between the semiconductor die and the interposer and then cured.
KR1020150024957A 2013-11-19 2015-02-23 Method for fabricating semiconductor package and semiconductor package using the same KR101612220B1 (en)

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