KR101601023B1 - Spread spectrum clock generator with digital compensator and method for generating clock using the same - Google Patents

Abstract

A spread spectrum clock generator is disclosed. A spread spectrum clock generator according to an embodiment of the present invention includes a frequency divider for dividing and feeding an output frequency and fixing a phase of a frequency source by performing low frequency filtering according to a preset loop bandwidth; A sigma-delta modulator for dynamically varying a frequency division value of the frequency divider and outputting the divided value; A profile generator for outputting a low-pass filtered profile by the phase locked loop; A digital compensator for compensating the low-pass filtering applied to the profile input from the profile generator and outputting the compensation to the sigma-delta modulator; And a zero point adjuster for automatically setting the frequency closest to the loop bandwidth of the phase locked loop to a zero point by selecting an amplification degree of each of the taps constituting the digital compensator.

Description

TECHNICAL FIELD [0001] The present invention relates to a spread spectrum clock generator having a digital compensator and a clock generating method using the same.

The present invention relates to a clock generator and a clock generation method, and more particularly, to a clock generator and a clock generation method using a sigma-delta modulator (SDM) capable of reducing Electro Magnetic Interference (EMI) And a clock generation method using the spread spectrum clock generator.

The problem of electromagnetic interference (hereinafter referred to as " EMI ") between components of a portable device is increasing due to use of various portable devices and increase of demand. Problems caused by electromagnetic interference (EMI) may be simply a temporary distortion of video or audio data, but in the worst case it will cause components to malfunction. As handheld devices become smaller and more integrated, discussions on how to deal with electromagnetic interference (EMI) are becoming more active. Future products will be expected to operate at higher speeds with integration and miniaturization, so that the demand for technologies to prevent electromagnetic interference is expected to increase more and more.

In order to reduce the EMI, it is possible to shield a semiconductor or a part which is a problem, but in this case, it is not realistic because it occupies a very large area and is expensive.

Particularly, it is known that EMI increases as the bandwidth of the transmission data increases and the peak power of the output signal increases, and it is inevitable that the bandwidth increases as the data transmission amount increases in recent years. Therefore, a spread spectrum clock generator (SSCG) capable of lowering the power peak of an output signal is considered as the most effective and cost-effective solution for reducing EMI.

Spread spectrum technology is a technology that modulates the period or frequency of a regulated clock to distribute the energy concentrated at a specific frequency over a wider band. It is compatible with the conventional clock driving method, The possible frequencies can be extended to several hundred MHz to several GHz. For example, using a spread spectrum technique, power can be prevented from concentrating on one frequency by distributing and outputting an output frequency of 2.7 GHz by 13.5 MHz, which is 0.005% thereof.

This spread spectrum clock generator (SSCG) is preferred because the printed circuit board (PCB) does not require additional cost during the addition or assembly process. Also, the method varies depending on which part of the phase locked loop (PLL) inputs a profile capable of modulating the output frequency of the clock generator.

The present invention relates to a method of changing a division ratio by connecting a triangular profile generator, a sigma-delta modulator (SDM) and a frequency divider, An example configuration of SSCG is illustrated in FIG. 1, a conventional SSCG 10 includes a general PLL (phase locked loop) including a phase frequency comparator 11, a charge pump 12, a loop filter 13, a voltage controlled oscillator 14, And a triangular profile generator 15 and a sigma-delta modulator (SDM) 16 are connected to the structure. Such a structure is most widely used because it can be finely and accurately changed.

However, this conventional SSCG 10 includes another EMI increase element.

That is, when the loop bandwidth of the PLL is set to a low frequency in order to remove the quantization noise, the SDM 16 generates a triangular profile There is a problem that the degree of distortion becomes larger and EMI is greatly increased. In other words, the triangular profile generated by the triangular profile generator 15 generates a high-frequency harmonic component at its highest and lowest frequencies, and the triangular profile itself is distorted due to low-pass filtering of the high-frequency harmonic component by the loop bandwidth of the PLL, As a result, the output power peak of the output frequency is increased and the EMI generation is increased. When the loop bandwidth of the PLL is lowered, the degree of distortion of the triangular profile is increased, and as a result, EMI is increased.

On the other hand, when the loop bandwidth of the PLL is set to a high frequency in order to reduce the distortion of the triangular profile, the jitter due to the quantization noise of the SDM 16 becomes large, which deteriorates its performance as a clock.

Therefore, in the conventional SSCG (10) design, it has been difficult to set the loop bandwidth that minimizes the distortion of the triangular profile while maximizing the quantization noise canceling characteristic.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a spread spectrum clock generator that maximizes quantization noise canceling characteristics and minimizes distortion of a profile while improving EMI characteristics, and a clock generating method using the spread spectrum clock generator.

In addition, the present invention compensates for the low-frequency filtering by the loop bandwidth of the phase locked loop, so that even if the loop bandwidth of the phase locked loop is set to a frequency for minimizing the quantization noise, the spread spectrum A clock generator and a clock generation method using the clock generator.

Also, the present invention provides a spread spectrum clock generator for analyzing real-time low-pass filtering based on a loop bandwidth of a phase-locked loop, which is difficult to predict, and automatically determining a compensation width thereof, and a clock generating method using the same.

In order to achieve the above object, a spread spectrum clock generator provided in the present invention includes a frequency divider for dividing and feeding an output frequency, and performs low-pass filtering based on a preset loop bandwidth to fix a phase of a frequency source Phase locked loop; A sigma-delta modulator for dynamically varying a frequency division value of the frequency divider and outputting the divided value; A profile generator for outputting a low-pass filtered profile by the phase locked loop; And a digital compensator that compensates the low-pass filtering applied to the profile input from the profile generator and outputs the compensation to the sigma-delta modulator.

At this time, the digital compensator has a finite impulse response filter structure having a plurality of taps (for example, five taps), and the sum of amplitudes of the taps is preferably '0'.

The spread spectrum clock generator may further include a zero point adjuster that selects an amplification degree of each of the taps constituting the digital compensator and automatically sets a frequency closest to a loop bandwidth of the phase locked loop as a zero point, A frequency setting unit for temporarily setting a target frequency of the phase locked loop by temporarily fixing a frequency division ratio value for zero point adjustment; A fixed detector for determining whether the phase locked loop is fixed at the target frequency based on a phase difference between a reference clock signal applied to the phase locked loop and an output signal of the frequency divider; A counter for counting a time taken for the phase locked loop to be fixed at the target frequency; And an amplification degree determination unit that determines the amplification degree of the digital compensator based on the count value.

According to another aspect of the present invention, there is provided a spread spectrum clock generation method, comprising: generating a spread spectrum clock using a spread spectrum clock generator including a phase locked loop, a sigma-delta modulator, and a profile generator; Performing low-pass filtering by the loop bandwidth of the phase locked loop; Outputting a low-pass filtered profile in the profile generator; Compensating the low pass filtering process in the profile; Applying the compensated profile to the sigma-delta modulator to determine a frequency division value; And outputting a clock divided by the frequency division value.

The low-pass filtering process compensating step comprises: detecting a loop bandwidth applied at the low-pass filtering; And applying the zero point to the profile after setting the loop bandwidth to a zero point, wherein the loop bandwidth detecting step sets the frequency division ratio value to a first value and the phase locked Fixing a target frequency of the loop; Setting the frequency dividing ratio value to a second value and counting a required time while fixing a target frequency of the phase locked loop by the second value; Changing the frequency division ratio to a first value and calculating a fixed time based on the count value; And detecting the loop bandwidth by applying the fixed time to the following equation (1).

(1)

은 고정시간,

는 루프 대역폭이다.At this time,

The fixed time,

Is the loop bandwidth.

The present invention includes a digital compensator that compensates for low-pass filtering due to the loop bandwidth of the phase locked loop, so that even if the loop bandwidth is set to a low frequency in order to minimize quantization noise, profile distortion can be minimized regardless of the loop bandwidth . As a result, it is possible to maximize the quantization noise canceling characteristic while minimizing the distortion of the profile, thereby generating a spread spectrum clock with improved EMI characteristics.

1 is a schematic block diagram of an SSCG according to one conventional embodiment.
2 is a schematic block diagram of an SSCG according to an embodiment of the present invention.
3 is a schematic block diagram of a digital compensator included in FIG.
FIGS. 4 and 5 are diagrams for explaining operation characteristics of the digital compensator illustrated in FIG.
6 is a schematic block diagram of an SSCG according to another embodiment of the present invention.
Figure 7 is a schematic block diagram of the zero point adjuster included in Figure 6;
8 is a timing chart for explaining operation characteristics of the zero point regulator illustrated in FIG.
9 is a view for explaining count-amplification-zero information according to an embodiment of the present invention.
10 is a diagram illustrating a triangular profile and a clock generated by the SSCG according to an embodiment of the present invention.
11 is a diagram illustrating a triangular profile and a clock generated by the SSCG according to an embodiment of the present invention.
12 is a schematic flowchart of a spread spectrum clock generation process according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings, which will be described in detail to facilitate the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification. And a detailed description thereof will be omitted to omit descriptions of portions that can be readily understood by those skilled in the art.

Throughout the specification and claims, where a section includes a constituent, it does not exclude other elements unless specifically stated otherwise, but may include other elements.

2 is a schematic block diagram of an SSCG according to an embodiment of the present invention. 2, the SSCG 100 according to an embodiment of the present invention includes a phase frequency comparator 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator 140, a triangular profile generator 150, a Sigma Delta Modulator (SDM) 160, a frequency divider 170, and a digital compensator 200.

In this case, the phase frequency comparator 110, the charge pump 120, the loop filter 130, the voltage controlled oscillator 140, and the frequency divider 170 may be a general PLL (Phase Locked Loop) , The PLL performs low-pass filtering by a predetermined loop bandwidth to fix the phase of the frequency source, and for this purpose, each of them operates as follows.

The phase frequency comparator 110 compares the phase of the reference clock frequency F _ref with the feedback clock frequency (i.e., the frequency divided by the frequency divider 170) F _div so that the two clocks are phase difference up- (up / dn) pulse, and the charge pump 120 receives the up / down pulse and outputs a predetermined current for a time corresponding to the phase difference. At this time, the predetermined current is a current of a size and shape that can be set in consideration of the size and shape of a control voltage required by a person having ordinary knowledge in the technical field of the present invention. The loop filter 130 receives the predetermined current output from the charge pump 120, and the voltage controlled oscillator 140 outputs the control voltage. At this time, the control voltage corresponds to the magnitude or period of the predetermined current. The voltage-controlled oscillator 140 receives the control voltage and controls a multi-phase clock having a frequency corresponding to the control voltage level.

The frequency divider 170 divides the clock signal CK _out , which is the output of the voltage controlled oscillator 140, into a predetermined divided value and feeds it back to the phase frequency comparator 110 input signal F _div .

In general, the frequency dividing method is an integer dividing method (integer-N), which is a method of dividing by an integer value, and a fractional-N, which is a method of dividing by a fractional value. In general, the fractional dispense method is more advantageous than the integer dispense method in terms of in-band noise, lock time, reference spurious or reference spur.

Accordingly, it is preferable that the frequency divider 170 of the present invention also employs a fractional dividing method. For this purpose, the SDM 170 dynamically changes the frequency division value of the frequency divider 170 to provide the frequency divider 170.

The triangular profile generator 150 outputs a low-pass filtered profile by a phase locked loop. In particular, triangular profile generator 150 digitally generates a triangular profile with the highest EMI reduction performance. At this time, many standards set the frequency of the triangular profile at 30 to 33 kHz.

The digital compensator 200 compensates the low-pass filtering applied to the profile T _in input from the triangular profile generator 150 and outputs the compensation to the SDM 160. That is, the digital compensator 200 sets a zero point corresponding to the loop bandwidth of the phase locked loop and applies the zero point to the profile to compensate the low-pass filtering process.

A schematic block diagram of this digital compensator 200 is illustrated in FIG. Referring to FIG. 3, the digital compensator 200 may be implemented with a finite impulse response (FIR) filter structure having a plurality of taps. That is, the digital compensator 200 includes a plurality of delay circuits 211, 212, 213, 214, 215 and a plurality of amplifiers 221, 222, 223, 224, And the sum of amplitudes of the taps calculated by the adder 230 is '0'. In the example of FIG. 3, the digital compensator 200 is implemented by an FIR filter structure. However, the digital compensator 200 is not limited to the example illustrated in FIG. That is, the digital compensator 200 can be applied to any filter that creates a zero point that is within the range predicted by a person skilled in the art to which the present invention belongs.

Figs. 4 and 5 are diagrams for explaining the operating characteristics of the digital compensator as illustrated in Fig.

4 is a diagram illustrating an example in which low frequency filtering processing is compensated when five different frequencies are set as a zero point and the zero point is applied to a profile. First, 'a' is set to a frequency fz1 as a zero point, 'B' represents an example of a signal obtained by compensating the low-pass filtering process by setting the frequency fz2 as a zero point, 'c' represents a signal obtained by compensating the low-pass filtering process by setting the frequency fz3 as a zero point 'D' is an example of a signal obtained by compensating the low-pass filtering process by setting the frequency fz4 to a zero point, and 'e' is an example of a signal obtained by compensating the low-pass filtering process by setting the frequency fz5 to zero . When the present invention compensates the frequency through the digital compensator, the low frequency component (i.e., the frequency component before the frequency set to the zero point) is transmitted as it is, and the high frequency component (i.e., the frequency component after the frequency set as the zero point) Amplified and transmitted.

Figure 5 shows an example of the loop bandwidth of a phase locked loop performing low pass filtering. FIG. 5A shows a case where the frequency of the loop bandwidth is fz1, FIG. 5B shows a case where the frequency of the loop bandwidth is fz2, and FIG. 5C shows a case where the frequency of the loop bandwidth Is fz3.

Therefore, in the case of the signal low-pass filtered by the loop bandwidth as illustrated in FIG. 5A, it is preferable to compensate the low-pass filtering process by setting the frequency fz1 to zero as shown by 'a' In the case of the signal low-pass filtered by the loop bandwidth as illustrated in (b) of FIG. 5, it is preferable to compensate the low-pass filtering process by setting the frequency fz2 to zero as shown by 'b' In the case of the signal low-pass filtered by the loop bandwidth as illustrated in FIG. 4C, it is preferable to compensate the low-pass filtering process by setting the frequency fz3 to zero as shown by 'c' in FIG.

Thus, in order for the digital compensator to compensate the low-pass filtering process in the phase locked loop, a step of detecting the loop bandwidth of the phase locked loop and adjusting the zero point based on that frequency is needed.

Thus, another embodiment in which the zero point adjuster for performing the zero point adjustment is further illustrated in FIG.

6 is a schematic block diagram of an SSCG according to another embodiment of the present invention. Referring to FIG. 6, SSCG 300 according to another embodiment of the present invention includes a phase frequency comparator 310, a charge pump 320, A loop filter 330, a voltage controlled oscillator 340, a triangular profile generator 350, a sigma-delta modulator (SDM) 360, a frequency divider 370, a digital compensator 380, ).

At this time, a phase frequency comparator 310, a charge pump 320, a loop filter 330, a voltage controlled oscillator 340, a triangular profile generator 350, a sigma-delta modulator (SDM) The periodic filter 370 and the digital compensator 380 may each include a phase frequency comparator 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator 140 included in the SSCG illustrated in FIG. 2, The operation is also similar to that described in the description with reference to FIG. 2, with the configuration similar to that of each unit 150, sigma-delta modulator (SDM) 160, frequency divider 170, and digital compensator 200, . Therefore, a repetitive description thereof will be omitted.

Meanwhile, the zero point adjuster 400 included in another embodiment of the present invention selects the amplification degree of each of the taps constituting the digital compensator 380 to automatically set the frequency closest to the loop bandwidth of the phase locked loop to zero.

FIG. 7 is a schematic block diagram of the zero point adjuster 400 included in FIG.

Referring to FIG. 7, the zero point adjuster 400 includes a fixed detector 410, an AND gate 420, a counter 430, an amplification degree determination unit 440, and a frequency setting unit 450.

The fixed detector 410 determines whether or not the phase locked loop is fixed at a predetermined target frequency and outputs a signal LOCK for indicating it. The fixed detector 410 discriminates the phase difference between the reference clock signal F _ref applied in the phase locked loop and the output signal F _div of the frequency divider 370 illustrated in FIG. 6, It is determined that the target frequency is locked at the target frequency. If the phase difference is changed, it is determined that the target frequency is not fixed (Unlocked). When the phase locked loop is locked at the target frequency, the LOCK signal is outputted as '0', and when it is not locked, the LOCK signal is outputted as '1'.

The AND gate 420 is connected to the input terminal of the counter 430 and transmits the logical product of the LOCK signal and the reference clock signal F _ref applied to the phase locked loop to the counter 430. If the LOCK signal is '1', the signal triggered by the reference clock signal F _ref will be delivered to the counter 430, and if the LOCK signal is '0', the input signal of the counter 430 will not be triggered . Therefore, the counter 430 counts time only when the LOCK signal is '1', that is, the phase locked loop is not locked to the target frequency (Unlocked). In other words, the counter 430 counts the time taken for the phase locked loop to be fixed at the target frequency.

The amplification degree determination unit 440 receives the count value from the counter 430 and determines the amplification degree of the digital compensator ('380' in FIG. 6). More specifically, the amplification determination unit 440 determines the amplification degree of the digital compensator based on the generated count-amplification-zero-point information by previously calculating the amplification degree and the zero point of the digital compensator according to the range of the count value. The count-amplification-zero information will be described later with reference to the example of FIG.

The frequency setting unit 450 temporally fixes the frequency division ratio to temporarily set the target frequency of the phase locked loop. In particular, the frequency setting unit 450 initially sets the frequency division ratio to a first value (e.g., 'N'), and the target frequency of the phase locked loop is fixed by the first value (e.g., 'N' The frequency division ratio is set to a second value (e.g., 'N-1'). Further, when the target frequency of the PLL is fixed by the second value (e.g., 'N-1'), the frequency division ratio value is changed again to a first value (e.g., 'N').

8 is a timing chart for explaining operation characteristics of the zero point regulator illustrated in FIG. (a) is a reference clock signal f _ref applied in a phase locked loop, (b) is a start signal START, (c) is a division ratio N [7: 0] the phase difference between which is applied to the reference clock signal (F _ref) and the output of the frequency divider signal (F _div) (ΦPFD = ΦF _ref - ΦF _div), (e) is a fixed signal output from a fixed detector 410 of FIG. 7 (F) is the count value CNT [13: 0] output from the counter 430 of FIG. 7, and (g) is the amplification degree selection value determined by the amplification degree determination unit 440 of FIG. GAIN_SEL [2: 0]). Referring to FIG. 8, the target frequency of the phase locked loop is fixed by fixing the division ratio N when the START signal b is' 0 ', and the START signal b is set to' 1 '. At this time, the target frequency is changed by changing the frequency division ratio from "1" to "N-1" from the target value. Then, the phase difference which is fixed in the section where the START signal 'b' is '0' moves. That is, the signal d is changed from the locked state to the unlocked state. At this time, the LOCK signal e maintains a value of '1' during the interval B from the time when the phase difference (signal d) moves to the fixed time point A (that is, during the non-fixed interval) . Therefore, the count value (CNT [13: 0]) (f) '0 ~ 361' is output during the period B, and the determined amplification degree selection value GAIN_SEL [2: 0] It can be seen that the value is changed from [3'b100] to [3'b011] based on the point at which the count value is '358'.

9 is a view for explaining count-amplification-zero information according to an embodiment of the present invention.

Referring to FIG. 9, five zeros are calculated corresponding to the range of count values of five intervals, and each of the five tabs g1 to g5 of the digital compensator for generating frequencies corresponding to the five zero points Amplification degree-zero point information showing the amplification degree and the amplification degree selection value GAIN_SEL [2: 0] for determining the amplification degree of the five taps g1 to g5 is shown. 9, the first column (CNT [13: 0]) in the left-to-right direction indicates the range of the count value output from the counter 430 in FIG. 7 and the second column (GAIN_SEL [2: 0] (G1 to g5) represent the amplifications to be applied to each tap of the digital compensator implemented in the FIR structure, and the third to seventh (g1 to g5) zero) represents the frequency set to zero.

At this time, the zero point is preferably set to a frequency closest to the loop bandwidth of the phase locked loop.

In the example of Fig. 9, the amplification degree selection value GAIN_SEL is [3'b1xx] when the count value is less than [14'd358], the amplification degree to be applied to the first tap of the digital compensator is 2, The amplification to be applied to the third tap of the digital compensator is 2, the amplification to be applied to the fourth tap of the digital compensator is 2, the amplification to be applied to the fifth tap of the digital compensator is 2, and the frequency set to zero is 1.35MHz .

At this time, the count value [14'd358] means that the count value is 358 as a 14-bit decimal number, and the amplification degree selection value [3'b1xx] means that the amplification degree selection value is 3xx binary Respectively.

According to an embodiment of the present invention, the count-amplification-zero point information of FIG. 9 may be generated through the following process.

First, the number of the zero points is determined to be five, and the frequencies corresponding to the five zero points are determined as 54 kHz, 120 kHz, 240 kHz, 541 kHz, and 1.35 MHz, respectively. (g1 to g5), and selects the amplification degree selection value for determining the amplification degree of the five tabs (g1 to g5). As described above, the frequency corresponding to the five zero points is determined to be the frequency closest to the loop bandwidth of the phase locked loop.

Further, the fixed time is calculated by substituting the frequency corresponding to the five zero points into the loop bandwidth value of Equation (1) to be described later, and then the range of the count value is determined based on the fixed time, Is generated.

In the embodiment of FIG. 9, the range of the count value is divided into five intervals. However, in another embodiment, the range of the count value may be divided into more or less than five intervals, The number of zero points corresponding to the range of values and the frequency corresponding to the zero point will also be changed.

10 and 11 are diagrams for explaining the effect of the present invention visually, FIG. 10 is a diagram showing a triangular profile and a clock generated by the SSCG according to a conventional example, and FIG. Lt; RTI ID = 0.0 > SSCG < / RTI > according to one embodiment.

Comparing the graphs of FIGS. 10 and 11 (a), it can be seen that the triangular profile of the present invention maintains a sharp state although the peak and the lowest point are distorted in a round shape in the conventional triangular profile. That is, it can be seen that the triangular profile of the present invention is not distorted.

On the other hand, when comparing the graphs of FIGS. 10 and 11 (b), the peak value appears at both ends of the output waveform and the shape of the output waveform is unstable in the output waveform of the prior art shown in FIG. 10 (b) 11 (b), the peak value is smaller than the output waveform of FIG. 10 (b), and the output waveform is stable. Accordingly, EMI is reduced in the present invention compared to the prior art.

12 is a schematic flowchart of a spread spectrum clock generation process according to an embodiment of the present invention. 6 and 12, a spread spectrum clock generation process according to an embodiment of the present invention is as follows. First, low frequency filtering is performed by a loop bandwidth preset in a phase locked loop including a phase frequency comparator 310, a charge pump 320, a loop filter 330, a voltage controlled oscillator 340 and a frequency divider 370 (S110). The triangular profile generator 350 outputs the low-pass filtered profile T _in (S120). At this time, it is preferable that the profile has a triangular profile frequency.

Meanwhile, the digital compensator 380 compensates the low-pass filtering process in the profile (S130). To this end, the digital compensator 380 includes detecting a loop bandwidth applied at low-pass filtering of the phase locked loop; Setting the loop bandwidth to a zero point; The step of applying the zero point to the profile may be performed sequentially. In particular, the digital compensator 380 may refer to the zero point information that is automatically set in the zero point adjuster 400 to detect the loop bandwidth. To automatically set the zero point of the digital compensator 380, the zero point adjuster 400 Sets the frequency division ratio to a first value (e.g., 'N') and fixes the target frequency of the phase locked loop by the first value (e.g., 'N'). When the target frequency of the PLL is fixed by the first value (e.g., 'N'), the zero point adjuster 400 sets the frequency division ratio value to a second value (e.g., 'N-1') And the required time is counted while fixing the target frequency of the phase locked loop by the second value (e.g., 'N-1'). When the target frequency of the phase locked loop is fixed by the second value (e.g., 'N-1'), the zero point adjuster 400 returns the frequency division ratio value to a first value (e.g., 'N' . Then, the fixed time is calculated based on the count value. That is, the fixed time is calculated by multiplying the count value by the reference clock period.

When the fixed time is calculated as described above, the zero point adjuster 400 detects the loop bandwidth by applying the fixed time to the following equation (1).

은 고정시간이고,

는 루프 대역폭이다. At this time,

Is a fixed time,

Is the loop bandwidth.

When the loop bandwidth is detected in this manner, the digital compensator 380 compensates the low-pass filtered profile with the frequency at that time as a zero point.

When the low-pass filtering process is completed, the SDM 3620 applies the compensated profile to perform sigma delta modulation (S140) to determine a frequency division value, and in a phase locked loop, outputs a clock divided by the frequency division value (S150).

In the above-described exemplary system, the methods are described on the basis of a flowchart as a series of steps or blocks, but the present invention is not limited to the order of the steps, and some steps may occur in different orders .

It will also be understood by those skilled in the art that the steps shown in the flowchart are not exclusive and that other steps may be included or that one or more steps in the flowchart may be deleted without affecting the scope of the invention.

Claims (15)

A spread spectrum clock generator comprising:
A phase locked loop including a frequency divider for dividing and feeding an output frequency and fixing the phase of the frequency circle by performing low-pass filtering based on a preset loop bandwidth;
A sigma-delta modulator for dynamically varying a frequency division value of the frequency divider and outputting the divided value;
A profile generator for outputting a low-pass filtered profile by the phase locked loop;
A digital compensator for compensating the low-pass filtering applied to the profile input from the profile generator and outputting the compensation to the sigma-delta modulator; And
And a zero point adjuster for automatically setting a frequency corresponding to a loop bandwidth of the phase locked loop to a zero point based on the amplification degree of each of the taps constituting the digital compensator. 2. The method of claim 1, wherein the profile generator
Wherein the triangular profile generator is a triangular profile generator that generates a triangular profile frequency. 2. The apparatus of claim 1, wherein the digital compensator
A finite impulse response filter structure having a plurality of taps and setting a zero point corresponding to a loop bandwidth of the phase locked loop and applying the zero point to the profile to compensate the low pass filtering process Features a spread spectrum clock generator. 4. The apparatus of claim 3, wherein the digital compensator
And the sum of amplitudes of each tap is " 0 ". The apparatus of claim 1, wherein the zero point adjuster
And selects the amplification degree of each of the taps constituting the digital compensator to automatically set a frequency closest to the loop bandwidth of the phase locked loop as a zero point. 6. The apparatus of claim 5, wherein the zero point adjuster
A frequency setting unit for temporarily setting a target frequency of the phase locked loop by temporarily fixing a frequency division ratio value for zero point adjustment;
A fixed detector for determining whether the phase locked loop is fixed at the target frequency based on a phase difference between a reference clock signal applied to the phase locked loop and an output signal of the frequency divider;
A counter for counting a time taken for the phase locked loop to be fixed at the target frequency; And
And an amplification degree determination unit that determines an amplification degree of the digital compensator based on the count value. 7. The apparatus of claim 6, wherein the frequency setting unit
The frequency division ratio is initially set to a first value and the frequency division ratio is changed to a second value when the target frequency of the phase locked loop is fixed by the first value, And when the target frequency of the loop is fixed, the frequency dividing ratio value is changed back to the first value. The method of claim 7, wherein the frequency division ratio is
When the first value is 'N', the second value is 'N-1'. 7. The apparatus of claim 6, wherein the counter
And counts the output signal of the fixed detector as a signal triggered by a logical product of the output signal of the fixed detector and the reference clock signal. 7. The apparatus according to claim 6, wherein the amplification degree determining unit
And selects the amplification degree of the digital compensator based on the count-amplification-zero-point information generated by previously calculating the amplification degree and the zero point of the digital compensator according to the range of the count value. A spread spectrum clock generation method using a spread spectrum clock generator including a phase locked loop, a sigma-delta modulator, a profile generator, and a digital compensator,
Performing low-pass filtering by a loop bandwidth of the predetermined phase locked loop;
Outputting a low-pass filtered profile in the profile generator;
Compensating the low pass filtering process in the profile;
Applying the compensated profile to the sigma-delta modulator to determine a frequency division value; And
And outputting a clock divided by the frequency division value,
The low-pass filtering process compensation step
Detecting a loop bandwidth applied in the low-pass filtering of the phase locked loop;
Automatically setting a frequency corresponding to a loop bandwidth of the phase locked loop to a zero point based on the amplification degree of each of the taps constituting the digital compensator; And
And applying the zero point to the profile. ≪ Desc / Clms Page number 21 > 12. The method according to claim 11, wherein the profile output step
And generating a triangular profile frequency. delete 12. The method of claim 11, wherein the loop bandwidth detection step
Setting a frequency division ratio value to a first value and fixing a target frequency of the phase locked loop by the first value;
Setting the frequency dividing ratio value to a second value and counting a required time while fixing a target frequency of the phase locked loop by the second value;
Changing the frequency division ratio to a first value and calculating a fixed time based on the count value; And
And detecting the loop bandwidth by applying the fixed time to the following equation (1). ≪ EMI ID = 1.0 >
(1)

At this time,

The fixed time,

Is the loop bandwidth. 15. The method of claim 14, wherein the fixed time calculating step
And multiplying the count value by the reference clock period to calculate the fixed time.

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