KR101579587B1 - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same are provided. A semiconductor device comprising: a semiconductor substrate on which a recessed region and a protruded region are formed, the recessed region including a bottom surface and a side surface; a plurality of gate conductive films including a flat portion on a bottom surface of the recessed region and side walls extending sideways from the flat portion, And a peripheral circuit formed on the protruding region and active pillars passing through the plurality of gate conductive films, and a method of forming the same.

Peripheral circuit, opening bend, recessed area, protruded area

Description

Semiconductor device and method of forming same

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having a peripheral circuit and a method of forming the same.

Due to the development of the electronic industry, various electronic devices in which semiconductor devices are used are becoming more versatile, smaller, and higher in capacity. Accordingly, a larger capacity, higher integration, and lower power consumption of semiconductor devices are being sought. In order to meet such a demand, semiconductor technology has evolved from a conventional planar type device to a semiconductor device including various structures.

However, as the structure of the semiconductor device becomes various, the structure of each pattern constituting the semiconductor device becomes various and complicated. In addition, it is inevitable to form openings with high steps for connecting various complex patterns existing in semiconductor devices and / or wiring of peripheral circuits existing in a complicated structure. Many problems may occur in the process of forming openings having a high step and / or in the process of embedding such openings. For example, if an opening having a high stepped portion is formed at an unexpected position and / or a stepped portion of the opening portion does not have an expected stepped portion and / or an opening portion is not stably embedded, There is a problem that the reliability is deteriorated. In order to solve such a problem, studies have been made to remove openings having a high step.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a semiconductor device having excellent reliability.

Another object of the present invention is to provide a method of forming a semiconductor device including a peripheral circuit formed on a protruding region.

Another object of the present invention is to provide a method of forming a semiconductor device in which openings having high steps are removed.

In order to accomplish the above object, the present invention provides a semiconductor device and a method of forming the same. A method of forming a semiconductor device includes forming a recessed region and a protruded region in a semiconductor substrate, the recessed region including a bottom surface and a side surface; Stacking a plurality of gate conductive films spaced apart from each other and including a flat portion on the bottom surface of the recess region and a side wall portion extending from the flat portion to the side surface; And forming a peripheral circuit on the protruding region.

The semiconductor substrate includes a base substrate and an insulating film on the base substrate, and forming the recessed region includes etching the insulating film in the recessed region to leave the insulating film in the protruding region.

The method for forming a semiconductor device further includes forming a semiconductor film on an insulating film of the protruding region before forming the peripheral circuit.

The method for forming the semiconductor device includes forming the upper surface of the sidewall portion of the gate conductive films to have the same height as the upper surface of the protruding region.

The forming of the gate conductive films includes alternately laminating the inter-gate insulating films and the conductive films on the recessed regions.

The method for forming a semiconductor device includes forming first openings that expose a bottom surface of the recess region by patterning the conductive films and the inter-gate insulating films; And forming active columns disposed in the first openings while being in direct contact with the bottom surface of the recessed region.

The method for forming a semiconductor device includes forming an interlayer insulating film on the conductive films and the inter-gate insulating films on which the active columns are formed; Patterning the interlayer insulating film to form a second opening exposing a sidewall of the gate conductive films, an active column and a peripheral circuit; And filling the second opening to form a plug.

Wherein the plug is formed of a material having a higher conductivity than the gate conductive film.

A semiconductor device includes: a semiconductor substrate including a recessed region including a bottom surface and a side surface, and a protruding region; A plurality of gate conductive films stacked on each other and including a flat portion on the bottom surface of the recess region and a side wall portion extending from the flat portion to the side surface; Active pillars passing through the plurality of gate conductive layers; And a peripheral circuit formed on the protruding region.

The semiconductor device further includes a plug connected to an upper surface of a sidewall portion of the plurality of gate conductive films.

It is possible to provide a semiconductor device having excellent quality by forming a peripheral circuit in a protruding region and a method of forming the same.

It is possible to provide a semiconductor device in which openings having high steps are removed and a method of forming the same, thereby providing a semiconductor device having excellent quality and a method of forming the same.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In addition, since they are in accordance with the preferred embodiment, the reference numerals presented in the order of description are not necessarily limited to the order. In the drawings, the thicknesses of the films and regions are exaggerated for clarity. Also, when a film is said to be on another film or substrate, it may be formed directly on another film or substrate, or a third film may be interposed therebetween. The expression " and / or " is used herein to mean including at least one of the elements listed before and after.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, the base substrate 100 may include a recessed region 106 and a protruded region 108, including a bottom surface and a side surface. The base substrate 100 may be a semiconductor substrate. The recessed region 106 and the protruded region 108 may be the semiconductor substrate of one body. The recess region 106 may be a cell region in which cells are provided, and the cells may include alternately stacked gate conductive films 130 and an inter-gate insulating pattern 140. The gate conductive layers 130 may include a flat portion on the bottom surface of the recess region 106 and a side wall portion extending from the flat portion to the side surface, and may be spaced apart from each other. The semiconductor device includes active pillars (156) extending through the gate conductive layers (130) and the inter-gate dielectric pattern (140), wherein the active pillars (156) To be in contact with the surface. A gate insulating layer pattern 153 is interposed between the active pillars 156 and the sidewalls of the gate conductive layers 130 and the sidewalls of the active pillars 156 and the gate interlayer insulating pattern 140, A part of the substrate 100 can be exposed. A drain region D may be disposed in the region of the active pillar 156 located in the uppermost inter-gate insulating layer 146.

The uppermost gate conductive film 135 may be used as an upper select gate, and the lowermost gate conductive film 131 may be used as a lower select gate. The gate conductive films 132 to 134 between the top gate conductive film 135 and the bottom gate conductive film 131 can be used as control gates. Although three control gates are shown in the figure, further control gates may be included.

The protruding region 108 may be a peripheral circuit region in which the peripheral circuit 160 is provided. The peripheral circuit 160 may include a peripheral circuit gate insulating film 164 and a peripheral circuit gate 166. The peripheral circuit gate 166 is disposed on the protruding region 108 and the peripheral circuit gate insulating film 164 may be interposed between the peripheral circuit gate 166 and the semiconductor substrate.

Plugs 181 to 186 connected to the upper surface of the sidewall of the gate conductive layers 130 and plugs 187 to 189 connected to the peripheral circuit 160 may be disposed. The plugs 181 to 189 may be connected to the conductive patterns 191 to 199 formed on the interlayer insulating layer 170.

2 is a cross-sectional view illustrating a semiconductor device according to a modification of the embodiment of the present invention.

Referring to FIG. 2, the semiconductor substrate may include the base substrate 100 and the insulating film 102 on the base substrate 100. The insulating layer 102 may provide the protruding region 108. The peripheral circuit 161 may be provided on the semiconductor film 162 on the insulating film 102.

3 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 3, the base substrate 200 may include a recessed region 206 and a protruding region 208, including a bottom surface and a side surface. The base substrate 200 may be a semiconductor substrate. The recessed region 206 and the protruding region 208 may be the semiconductor substrate of one body. The recess region 206 may be a cell region in which cells are provided. The cells may include a plurality of gate conductive layers 250 that include a flat portion on the bottom surface and sidewall portions extending from the flat portion to the side surface and are stacked and isolated from each other by an inter- have. Active pillars 232 disposed to contact the bottom surface of the base substrate 200 and penetrating the plurality of gate conductive films 250 may be disposed. An insulating material 234 may be disposed between the active pillars 232 and a drain region may be disposed in an upper region of the active pillars 232 located in the inter-gate insulating pattern 226 of the uppermost layer . A gate insulating layer 240 may be interposed between the gate conductive layers 250 and the active pillars 232 and between the gate conductive layers 250 and the gate insulating pattern 220. A gap fill insulating film 244 is disposed between the plurality of active columns 232 and may be disposed on the gate conductive film 251 of the lowermost layer. A common source line may be disposed on the base substrate 200 of the cell region formed in the recess region 206.

The top gate conductive film 226 may be used as an upper select gate, and the lowermost gate conductive film 221 may be used as a lower select gate. The gate conductive films 222 to 225 between the top gate conductive film 226 and the bottom gate conductive film 221 can be used as control gates. Although four control gates are shown in the figure, further control gates may be included.

The protruding region 208 may be a peripheral circuit 260 region in which the peripheral circuit 260 is provided. The peripheral circuit 260 may include a peripheral circuit gate insulating film 264 and a peripheral circuit gate 266. The peripheral circuit gate 266 may be disposed on the protruding region 208 and the peripheral circuit gate insulating film 264 may be interposed between the peripheral circuit gate 266 and the semiconductor substrate.

The semiconductor device may further include plugs 280 to 286 connected to upper surfaces of the side walls of the gate conductive layers 250 and plugs 287 to 289 connected to the peripheral circuits 260. The plugs 280 to 289 may be connected to the conductive patterns 290 to 299 formed on the interlayer insulating film 268.

4 is a cross-sectional view illustrating a semiconductor device according to a modification of another embodiment of the present invention.

Referring to FIG. 4, the semiconductor substrate may include the base substrate 200 and the insulating layer 202 on the base substrate 200. The insulating layer 202 may provide the protruding region 208. The peripheral circuit 261 may be provided on the semiconductor film 262 on the insulating film 202.

5A to 5H are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5A, the recessed region 106 may be formed by etching the base substrate 100. A recessed region 106 and a protruded region 108 including a bottom surface and a side surface can be formed. The etching process of the base substrate 100 may be performed by a method of bipolar etching. The base substrate 100 may be a semiconductor substrate. The difference between the bottom surface of the recessed region 106 and the top surface of the protruded region 108 may be 0.5 um or more. The recess region 106 may be a cell region in which cells are formed and the protrusion region 108 may be a peripheral circuit region 160 in which the peripheral circuit 160 is formed.

The base substrate 100 may be a semiconductor having a single crystal structure (for example, a P-type silicon wafer). The base substrate 100 may have a region electrically separated by impurity regions of different conductivity types.

Referring to FIG. 5B, the inter-gate insulating films 111 to 116 and the conductive films 121 to 125 may be alternately stacked on the recessed region 106. The inter-gate insulating films 111 to 116 and the conductive films 121 to 125 may also be formed on the protruding region 108. The conductive films 121 to 125 may include doped polycrystalline silicon formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

The inter-gate insulating films 111 to 116 may include a silicon oxide film formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD).

5C, a chemical mechanical polishing (CMP) process or an etch back process is performed on the gate interlayer insulating films 111 to 116 and the conductive films 121 to 125, which are alternately stacked on the protruding region 108 Can be removed. The upper surfaces of the sidewall portions of the inter-gate insulating films 111 to 116 and the conductive films 121 to 125 may have the same height as the upper surface of the protruding region 108. Thus, inter-gate insulating patterns 141 to 146: 140 can be formed and gate conductive films 131 to 135: 130 can be formed. The gate conductive layers 130 are stacked and isolated from each other by the inter-gate insulating pattern 140, and are formed on the bottom surface of the recess region 106 and side walls Section. The upper surface of the sidewall portion of the gate conductive layers 130 may be formed to have the same height as the upper surface of the protruding region 108.

5D, a first opening 150 may be formed by patterning the gate conductive layers 130 and the inter-gate insulating pattern 140 to expose a bottom surface of the recess region 106 . When the side wall of the first opening 150 is formed to be inclined, the width of the channel may be varied. In order to minimize this, the patterning for forming the first opening 150 may be performed using an anisotropic etching technique. Thus, the first opening 150 may have vertical side walls.

According to an embodiment of the present invention, the first opening 150 may be formed by patterning the conductive films 121 to 126 and the inter-gate insulating films 111 to 116, have.

Referring to FIG. 5E, a gate insulating layer 152 may be formed on the resultant structure in which the first opening 150 is formed. The gate insulating layer 152 may include one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition .

The gate insulating layer 152 may include a thin film for information storage. For example, the gate insulating film 152 may include a blocking insulating film, a charge storage film, and a tunnel insulating film sequentially stacked. The charge storage film may comprise a silicon nitride film having a charge trap site or a silicon oxynitride film. The tunnel insulating layer may include a thermal oxide layer or a silicon oxide layer formed by chemical vapor deposition (CVD), and the blocking insulating layer may include at least one of materials having a dielectric constant higher than that of the tunnel insulating layer.

A spacer 154 may be formed in the first opening 150 as an etching mask. The spacer 154 is formed to cover the inner wall of the gate insulating film 152 in the first opening 150 and is formed on the gate insulating film 152 in a subsequent patterning step of etching the gate insulating film 152. [ Can reduce the etch damage. For example, the spacer 154 may be one of materials that can be removed while minimizing etching damage to the gate insulating film 152. For example, when the gate insulating layer 152 contacting the spacer 154 is a silicon oxide layer, the spacer 154 may be formed of a silicon nitride layer.

Referring to FIG. 5F, the exposed gate insulating layer 152 may be etched using the spacer 154 as an etch mask. A gate insulating layer pattern 153 may be formed at the bottom of the first opening 150 to expose the top surface of the bottom substrate 100 of the recess region 106. After the formation of the gate insulating film pattern 153, the spacers 154 can be removed.

Active pillars 156 disposed in the first opening 150 may then be formed in direct contact with the bottom surface of the recessed region 106. The active pillars 156 may be formed of the same material as the base substrate 100. The active pillars 156 and the base substrate 100 may comprise silicon of a single crystal structure successively without crystal defects. To this end, the active pillars 156 may be grown from the exposed base substrate 100 using one of the epitaxial techniques.

Referring to FIG. 5G, a peripheral circuit 160 may be formed on the protruding region 108. First, a peripheral circuit gate insulating film 164 may be formed on the protruding region 108. The peripheral circuit gate insulating film 164 may include a silicon oxide film having a thickness of 40 to 300 Angstroms formed through a thermal oxidation process. A peripheral circuit gate 166 may be formed on the peripheral circuit gate insulating film 164. For example, the peripheral circuit gates 166 may be formed of polycrystalline silicon. On the other hand, a peripheral circuit assist gate (not shown) may be formed on the peripheral circuit gate 166 to reduce the resistance of the peripheral circuit gate 166 because the polysilicon has a relatively high resistivity relative to the metallic material have. The peripheral circuit assist gate (not shown) may include any one of silicide films and metal films.

A source region and a drain region may be formed on both sides of the peripheral circuit gate 166. The source and drain regions may be doped regions by dopants. Alternatively, the source and drain regions may be generated by a fringe field generated at the peripheral circuit gate 166 due to the voltage applied to the peripheral circuit gate 166.

Thereby, the peripheral circuit 160 including the peripheral circuit gate insulating film 164 and the peripheral circuit gate 166 can be formed.

An upper select gate line may be formed by patterning the uppermost gate conductive film 135. Each of the upper select gate lines may be formed to connect the active pillars 156 one-dimensionally.

Referring to FIG. 5H, an interlayer insulating layer 170 may be formed on the substrate 100. The interlayer insulating layer 170 may also be formed on the peripheral circuit region 160. The second openings 171 to 179 may be formed by patterning the interlayer insulating layer 170 to expose the sidewall portions of the gate conductive layers 130, the active columns 156, and the peripheral circuits 160 . A drain region D may be formed through a second opening 171 connected to the active pillar 156. The second openings 171 to 179 may not have a high end difference.

Next, referring to FIG. 1 again, a method of forming a semiconductor device according to an embodiment of the present invention will be described.

Referring to FIG. 1, a plug conductive layer may be formed on the interlayer insulating layer 170. The plug conductive film may fill the second openings 171 to 179. The plug conductive film may include a material having a higher conductivity than the gate conductive films 130. For example, the plug conductive layer may comprise tungsten formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). After formation of the plug conductive layer, A planarization process can be performed using the etch stopper film of the interlayer insulation film 170. This can form plugs 181 to 189. Subsequently, a wiring conductive film can be formed on the interlayer insulation film 170 The wiring conductive film may include aluminum formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). By patterning the wiring conductive film, Conductive patterns 191 to 199 that are in contact with the conductive patterns 181 to 189 may be formed.

According to the method of forming a semiconductor device according to an embodiment of the present invention, the gate conductive layers 130 and / or the peripheral circuits 160 and the conductive patterns 191 - Two openings 171 to 179 can be formed. The gate conductive layers 130 include sidewall portions and the peripheral circuits 160 are formed on the protruding regions 108 so that the second openings 171 to 179 may not have a high end difference . As a result, the position of the opening and the depth of the opening can be easily formed as designed, and the opening can be stably embedded. Thereby, the reliability of the plug filling the opening can be improved, and a method of forming a semiconductor device with excellent quality can be provided.

6A to 6B are cross-sectional views illustrating a method of forming a semiconductor device according to a modification of the embodiment of the present invention.

Referring to FIG. 6A, the semiconductor substrate may include the base substrate 100 and the insulating film 102. The formation of the recessed region 106 may include etching the insulating film 102 of the recessed region 106 to leave the insulating film 102 of the protruded region 108. The insulating layer 102 may include a silicon oxide layer formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). The insulating layer 102 may be etched by an anisotropic etching method.

In addition, according to the above-described embodiment, the semiconductor device includes a flat portion on the bottom surface of the recess region 106 and a side wall portion extending from the flat portion to the side surface, The gate conductive films 130 may be stacked. The active pillars 156 passing through the inter-gate insulating pattern 140 and the gate conductive layers 130 may be formed and the gate insulating pattern 153 may be formed.

Referring to FIG. 6B, a peripheral circuit 161 may be formed on the protruding region 108. FIG. The peripheral circuit 161 may include a peripheral circuit gate insulating film 164 and a peripheral circuit gate 166. The peripheral circuit 161 may be formed on the semiconductor film 162. For example, the semiconductor film 162 may be formed using a process of bonding the semiconductor film 162 on the insulating film 102 on the protruding region 108. Next, the second openings 171 to 179, the drain region D, the plugs 181 to 189, and the conductive patterns 191 to 199 may be formed according to the above-described embodiment. Therefore, it is unnecessary to form openings having a high-stage difference, thereby improving the reliability of the plug, thereby providing a method of forming a semiconductor device with excellent quality.

7A to 7G are cross-sectional views illustrating a method of forming a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 7A, a recess region 206 may be formed by etching the base substrate 200. A recessed region 206 and a protruded region 208 including a bottom surface and a side surface can be formed. The etching process of the base substrate 200 may be performed by a method of bipolar etching. The base substrate 200 may be a semiconductor substrate. The difference between the bottom surface of the recessed area 216 and the top surface of the protruded area 218 may be 0.5 um or more. The recessed region 206 may be a cell region in which cells are formed, and the protruding region 208 may be a peripheral circuit region in which peripheral circuits are provided.

The base substrate 200 may be a semiconductor of a single crystal structure (for example, a P-type silicon wafer). The base substrate 200 may have a region electrically separated by impurity regions of different conductivity types.

The sacrificial films SC1 to SC6 and the inter-gate insulating films 211 to 216 may be alternately formed on the base substrate 200. [ The sacrificial films SC1 to SC6 and the inter-gate insulating films 211 to 216 include a flat portion on the bottom surface of the recess region 206 and a side wall portion extending from the flat portion to the side surface, Can be stacked while being spaced apart. The inter-gate insulating films 211 to 216 may include at least one of a silicon oxide film and a silicon nitride film. The sacrificial layers SC1 to SC6 may be formed of materials that can be selectively etched while minimizing the etching of the inter-gate insulating films 211 to 216. [

7B, the inter-gate insulating films 211 to 216 are formed so that the inter-gate insulating films 211 to 216 and the sacrificial films SC1 to SC6 have the same height as the upper surface of the protruding region 208, And sacrificial films SC1 to SC6 may be removed using a chemical mechanical polishing (CMP) or etch back process. Thus, inter-gate insulating patterns 221 to 226 (220) can be formed.

The first opening 230 may be formed by patterning the inter-gate insulation pattern 220 and the sacrificial layers SC1 to SC6 to expose the upper surface of the base substrate 200. [ When the sidewalls of the first opening 230 are formed to be inclined, the width of the channel can be varied. In order to minimize this, the patterning for forming the first openings 230 may be performed using an anisotropic etching technique. Thus, the first opening 230 may have a vertical side wall.

Referring to FIG. 7C, active pillars 232 may be formed to cover the inner walls of the first openings 230. The active pillars 232 may be formed to conformally cover the inner walls of the first openings 230 using either chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALD). The active pillars 232 may be formed to have the same conductivity type as that of the base substrate 200 to which the active pillars 232 are connected so that the active pillars 232 and the base substrate 200 can be electrically connected. For example, the active pillars 232 may comprise silicon of a single crystal structure that continues to the base substrate 200 without crystal defects. To this end, the active pillars 232 may be grown from the exposed base substrate 200 using one of the epitaxial techniques. The remaining space of the first opening 230 may be filled with an insulating material 234 (e.g., a silicon oxide film, a silicon nitride film, or air).

The gate interlayer insulating pattern 220 and the sacrificial layers SC1 to SC6 may be patterned again to form a preliminary gate isolation region 236 exposing the top surface of the base substrate 200. [ For example, the preliminary gate isolation region 236 may be formed between the adjacent active pillars 232. Accordingly, the sidewalls of the inter-gate insulation pattern 220 and the sacrificial films SC1 to SC6 may be exposed by the preliminary gate isolation region 236. [ The formation process of the preliminary gate isolation region 236 may be the same as the process of forming the first opening 230.

The sacrificial layers SC1 to SC6 exposed by the preliminary gate isolation region 236 can be removed. Gate regions 238 may be formed between the inter-gate insulating patterns 220 to expose the sidewalls of the active pillars 232. The step of removing the sacrificial layers SC1 to SC6 may include a step of removing the sacrificial layers SC1 to SC6 having an etch selectivity with respect to the inter-gate insulating pattern 220, the base substrate 200, the active pillars 232, May be carried out using an etching recipe. In addition, the step of removing the sacrificial layers (SC1 to SC6) may be a dry or wet method, and a method of isotropic etching may be used.

Referring to FIG. 7D, a gate insulating layer 240 may be formed on the resultant structure in which the gate regions 238 are formed. The gate insulating layer 240 may include any one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD) can do.

The gate insulating layer 240 may include a thin film for information storage. For example, the gate insulating layer 240 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer sequentially stacked. Since the side walls of the active pillars 232 are exposed by the gate regions 238, a thermally oxidized film can be directly formed on the exposed surfaces of the active pillars 232. Therefore, the tunnel insulating film may include a thermally oxidized film formed through such a method. The charge storage film and the blocking insulating film may be formed using chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALD) to provide excellent step coverage.

Referring to FIG. 7E, a preliminary gate conductive layer 242 filling the preliminary gate isolation region 236 and the gate region 238 may be formed on the gate insulation layer 240. The preliminary gate conductive film 242 includes at least one of a polycrystalline silicon film, a silicide film, and a metal film formed by using a chemical vapor deposition (CVD) method or an atomic layer chemical vapor deposition (ALD) method, can do. The gate insulating layer 240 is also formed on the upper surface of the base substrate 200 so that the preliminary gate conductive layer 242 is electrically isolated from the base substrate 200. A common source line may be formed on the base substrate 200 of the cell region formed in the recess region 206.

Referring to FIG. 7F, the gate insulating layer 240 and the preliminary gate conductive layer 242 may be removed using a chemical mechanical polishing (CMP) method so as to have the same height as the upper surface of the protruding region 208 . The gate conductive films 251 to 256 may be formed by removing the preliminary gate conductive film 242 formed on the preliminary gate isolation region 236 and forming a gap fill insulating film 244 on the resultant product. The removal of the preliminary gate conductive layer 242 formed on the preliminary gate isolation region 236 is performed until the lowest layer 221 of the intergate insulation pattern 220 is exposed through the patterning process, Etching until the top surface of the bottom layer 251 of the gate conductive layers 250 is exposed, such that the gate conductive layer 200 is not exposed.

Columns arranged two-dimensionally by patterning the active pillars 232 may be formed. The bottom layer 251 of the gate conductive layers 250 may be used as a bottom selection gate and the top layer 256 of the gate conductive layers 250 may be used as an upper selection gate, The intervening gate conductive films 251 to 455 are vertically separated by the inter-gate insulating pattern 220, and can be used as electrically independent word line planes. Thereby, the gate conductive films 250, which include the flat portion on the bottom surface of the recess region 206 and the side wall portion extending from the flat portion to the side surface, may be formed. The upper surface of the sidewall portion of the gate conductive layer 250 may be formed to have the same height as the upper surface of the protruding region 208.

A peripheral circuit 260 may be formed on the protruding region 208. First, a peripheral circuit gate insulating film 264 may be formed on the protruding region 208. The peripheral circuit gate insulating film 264 may include a silicon oxide film of 40 to 300 Angstroms formed through a thermal oxidation process. A peripheral circuit gate 266 may be formed on the peripheral circuit gate insulating film 264. [ For example, the peripheral circuit gates 266 may be formed of polycrystalline silicon. On the other hand, a peripheral circuit assist gate (not shown) may be formed on the peripheral circuit gate 266 to reduce the resistance of the peripheral circuit gate 266 because the polysilicon has a relatively high resistivity relative to the metallic material have. The peripheral circuit assist gate (not shown) may include any one of silicide films and metal films.

A source region and a drain region may be formed on both sides of the peripheral circuit gate 266. The source and drain regions may be doped regions by dopants. Alternatively, the source and drain regions may be generated by a fringe field generated in the peripheral circuit gate 266 due to the voltage applied to the peripheral circuit gate 266. [

Thereby, the peripheral circuit 260 including the peripheral circuit gate insulating film 264 and the peripheral circuit gate 266 can be formed.

Referring to FIG. 7G, an interlayer insulating film 268 may be formed on the base substrate 200. The second opening portions 270 to 279 may be formed by patterning the interlayer insulating layer 268 to expose the sidewall portions of the gate conductive layers 250, the active columns 232, and the peripheral circuits 260. The process of patterning the interlayer insulating layer 268 may be performed through an anisotropic etching process. A drain region may be formed on the active pillars 232 through the second openings 270 exposing the active pillars 232.

Next, referring to FIG. 3 again, a method of forming a semiconductor device according to another embodiment of the present invention will be described.

Referring to FIG. 3, a plug conductive layer may be formed on the interlayer insulating layer 268. The plug conductive film may fill the second openings 270 to 279. The plug conductive film may include a material having a higher conductivity than the gate conductive films 250. For example, the plug conductive layer may comprise tungsten formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). After formation of the plug conductive layer, The plugs 280 to 289 may be formed on the interlayer insulating layer 268. A wiring conductive layer may be formed on the interlayer insulating layer 268. In this case, The wiring conductive film may include aluminum formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). By patterning the wiring conductive film, Conductive patterns 209 to 299 that are in contact with the conductive patterns 280 to 289 may be formed.

The second openings 270 to 279 may be formed for connection between the gate conductive layers 250 and / or the peripheral circuits 260 and the conductive patterns 290 to 299. The gate conductive layers 250 may include sidewall portions and peripheral circuits 260 may be formed on the protruding regions 208 so that the second openings 270 to 279 may not have a high end difference. As a result, the position of the opening and the depth of the opening can be easily formed as designed, and the opening can be stably embedded. Thereby, the reliability of the plug filling the opening can be improved, and a method of forming a semiconductor device with excellent quality can be provided.

8A to 8B are cross-sectional views illustrating a method of forming a semiconductor device according to a modification of another embodiment of the present invention.

Referring to FIG. 8A, the semiconductor substrate may include the base substrate 200 and the insulating film 202. The formation of the recessed region 206 may include etching the insulating film 202 of the recessed region 206 to leave the insulating film 202 of the protruded region 208. The insulating layer 202 may include a silicon oxide layer formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer chemical vapor deposition (ALD). The insulating layer 202 may be etched by anisotropic etching.

According to the above-described embodiment, the inter-gate insulating pattern 220 including the flat portion on the bottom surface of the recess region 206 and the side wall portion extending from the flat portion to the side surface, And the active pillars 232 and the insulating pillars 234 in the active pillars 232 may be formed. The gate conductive films 250 (250) including a flat portion on the bottom surface of the recess region 206 and a side wall portion extending from the flat portion to the side surface, the gate conductive films 250 May be formed. A gate insulating layer 240 may be interposed between the gate conductive layers 250 and the active pillar 232 and between the gate conductive layers 250 and the gate insulating patterns 220, A gap fill insulating film 244 for separating the conductive films 250 may be formed.

Referring to FIG. 8B, a peripheral circuit 261 may be formed on the protruding region 208. The peripheral circuit 261 may include a peripheral circuit gate insulating film 264 and a peripheral circuit gate 266. The peripheral circuit 261 may be formed on the semiconductor film 262. [ For example, the semiconductor film 262 may be formed using a process of bonding the semiconductor film 262 onto the insulating film 202. Next, the second openings 270 to 279, the plugs 281 to 289, and the conductive patterns 291 to 299 may be formed according to the above-described embodiment. Therefore, it is unnecessary to form an opening having a high-stage difference, thereby improving the reliability of the plug, so that a semiconductor device with excellent quality can be provided.

 9 is a block diagram illustrating a memory system including a semiconductor device in accordance with embodiments of the present invention.

9, a memory system 1000 according to the present invention includes a memory device 1100, a memory controller 1100, a central processing unit 1500 electrically connected to the system bus 1250, a user interface 1600, And a power supply device 1700. The memory device 1100 may include at least one of the semiconductor devices disclosed in the above embodiments.

The memory device 1100 is provided with a user interface 1600, or data processed by the central processing unit 1500 is stored through the memory controller 1100. The memory device 1100 may be comprised of a semiconductor disk device (SSD), in which case the writing speed of the memory system 1000 will be dramatically increased. The semiconductor device according to the embodiment of the present invention can be applied to the memory device 1100, the memory controller 1100, the central processing unit 1500, and the like.

Although it is not shown in the drawing, the memory system 1000 according to the present invention can be provided with an application chipset, a camera image processor, a mobile DRAM, and the like. It is clear to those who have learned.

The memory system 1000 may also be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

1 is a cross-sectional view illustrating a semiconductor device and a method of forming the same according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor device according to a modification of the embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor device and a method of forming the same according to another embodiment of the present invention.

4 is a cross-sectional view illustrating a semiconductor device according to a modification of another embodiment of the present invention.

5A to 5H are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention.

6A to 6B are cross-sectional views illustrating a method of forming a semiconductor device according to a modification of the embodiment of the present invention.

7A to 7G are cross-sectional views illustrating a method of forming a semiconductor device according to another embodiment of the present invention.

8A to 8B are cross-sectional views illustrating a method of forming a semiconductor device according to a modification of another embodiment of the present invention.

 9 is a block diagram illustrating a memory system including a semiconductor device in accordance with embodiments of the present invention.

Claims (10)

Forming a recessed region and a protruded region in the semiconductor substrate, the recessed region including a bottom surface and a side surface; Stacking a plurality of gate conductive films spaced apart from each other and including a flat portion on the bottom surface of the recess region and a side wall portion extending from the flat portion to the side surface; And And forming a peripheral circuit on the protruding region. The method according to claim 1, Wherein the semiconductor substrate includes a base substrate and an insulating film on the base substrate, Wherein forming the recessed region and the protruding region comprises: And etching the part of the insulating film on the base substrate to leave the recessed area and the insulating film to expose the base substrate to form the protruding area. 3. The method of claim 2, And forming a semiconductor film on the insulating film of the protruding region before forming the peripheral circuit. The method according to claim 1, And the upper surface of the sidewall portion of the gate conductive films is formed to have the same height as the upper surface of the protruded region. The method according to claim 1, Wherein forming the gate conductive layers comprises: And alternately stacking inter-gate insulating films and conductive films on the recessed region. 6. The method of claim 5, Patterning the conductive films and the inter-gate insulating films to form first openings exposing a bottom surface of the recessed region; And And forming active columns disposed in the first openings while being in direct contact with the bottom surface of the recessed region. The method according to claim 6, Forming an interlayer insulating film on the conductive films on which the active columns are formed and the inter-gate insulating films; Patterning the interlayer insulating layer to form a second opening exposing a sidewall of the gate conductive layer, an active column, and a peripheral circuit; And filling the second opening to form a plug. 8. The method of claim 7, Wherein the plug is formed of a material having higher conductivity than the gate conductive film. A semiconductor substrate including a recessed region including a bottom surface and a side surface, and a protruding region; A plurality of gate conductive films stacked on each other and including a flat portion on the bottom surface of the recess region and a side wall portion extending from the flat portion to the side surface; Active pillars passing through the plurality of gate conductive layers; And a peripheral circuit formed on the protruding region. 10. The method of claim 9, And a plug connected to an upper surface of a sidewall portion of the plurality of gate conductive films.

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