KR101545716B1 - Apparatus and method for reparing memory, and memory chip employing the same - Google Patents

Abstract

The present invention relates to an apparatus and method for repairing a memory, and a memory chip using the same. The apparatus for repairing a memory according to one embodiment of the present invention may comprise: a first and a second storage unit for storing address information of a defective cell within a cell array; a redundancy analysis unit for analyzing whether a spare line for repairing a defective cell having address information stored in the first storage unit, and a spare line for repairing a defective cell having address information stored in the second storage unit are overlapping based on the address information of the defective cell which is stored in the first and the second storage unit; and a control unit for primarily determining whether to replace a line of the cell array, which contains at least a portion of the defective cell, with the spare line while storing address information of the defective cell in the first and the second storage unit and for secondarily determining a line of the cell array to be replaced with the spare line based on the analysis results by the redundancy analysis unit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory repairing apparatus and method, and a memory chip using the memory repairing apparatus and method.

The present invention relates to a memory repairing apparatus and method, and a memory chip using the same.

As semiconductor process technology develops, circuit integration is increasing. As a result, the density of the memory is greatly increased, and a highly integrated memory having a larger storage capacity in a small area is being released. However, the increase in memory density leads to an increase in the number of failures, and thus the improvement of the memory yield is becoming an important issue.

The method of repairing the memory is largely classified into an external repair method for checking and repairing a fault outside the memory, and an internal repair method for inspecting and repairing a failure in the memory using a module built in the memory. The external repair method has the disadvantage of high cost for inspection and repair due to the necessity of additional pins for sending fault information from the memory to the external inspection equipment and expensive equipment for analyzing it. The internal repair method has a lower cost than the external repair method, but has restrictions on the size, repair rate, and speed of hardware for inspection and repair.

Basically, memory repair is a process of replacing a faulty cell in a memory with an extra cell. Placing redundant cells in a two-dimensional memory cell array is related to the NP-complete problem. Therefore, when the repair rate of the algorithm is high, a very large hardware is required. On the contrary, the algorithm using relatively small hardware has a problem that the repair rate drops sharply as the number of fault cells increases.

An embodiment of the present invention aims to provide a memory repairing apparatus and method capable of maximizing a repair rate with small hardware, and a memory chip using the same.

According to an embodiment of the present invention, there is provided a memory repair apparatus including: first and second storage units for storing address information of a fault cell in a cell array; A spare line for repairing the faulty cell of the address information stored in the first storage unit based on the address information of the faulty cell stored in the first and second storage units, A redundancy analyzer for analyzing the redundancy of a spare line for repairing the spare line; And first determining a line to replace the line of the cell array including at least a part of the fault cells with the spare line while storing address information of the faulty cell in the first and second storage units, And a control unit for determining a line to be replaced with the spare line of the cell array based on the analysis result of the cell array.

Wherein if the row address and the column address of the failed cell do not match the row address and the column address of the fault cell stored in the first storage unit, the controller stores the row address and column address of the corresponding fault cell in the first storage Can be stored.

Wherein when the row address or the column address of the failed cell coincides with the row address or the column address of the previously stored fault cell in the first storage unit, In the second storage unit, an address that does not match the row address and the column address of the second storage unit.

The controller may store a row address or column address of a corresponding fault cell that does not match the row address or the column address of the previously stored fault cell with a row address or a row address of the first storage unit In the row address storage space or the column address storage space of the second storage unit corresponding to the storage space or the column address storage space.

Wherein the controller is configured to: if the row address or column address of another failed cell coincides with the row address or column address of the corresponding failed cell that matches the row address or column address of the pre-stored failed cell, A line to replace a row or column of addresses that match one of a stored fault cell, a row address or a column address of the corresponding fault cell and the other fault cell with the spare line.

The controller may determine that the memory is a non-repairable memory if the first storage unit lacks a storage space for storing address information of the failed cell.

Wherein the controller selects a row address storage space or a column address storage space for each storage space of the first storage unit and selects a row address storage space or a column address storage space for each row of the second storage unit corresponding to the selected row address storage space or column address storage space of the first storage unit Wherein the redundancy analyzer fetches a row address from a selected row address storage space of the first storage unit, fetches a row address from a selected row address storage space of the second storage unit, A row address fetched from the first storage unit is compared with a row address fetched from the second storage unit to determine whether or not the row address matches the column address, a column address is fetched from the selected column address storage space of the first storage unit, 2 retrieves a column address from the selected column address storage space of the storage unit, And the column address fetched from the second storage unit to compare the column address with each other.

Wherein all of the row addresses retrieved from the second storage unit match at least a part of the row addresses retrieved from the first storage unit and all of the column addresses retrieved from the second storage unit are stored in the first storage unit, The row and column of the cell array corresponding to the row address and the column address respectively stored in the selected row address storage space and the column address storage space of the first storage unit, Can be determined in a secondary manner with rows and columns to be replaced by < RTI ID = 0.0 >

The redundancy analyzer may further include: a non-matching row address fetched from the second storing unit that does not match a row address fetched from the first storing unit, and a second storing unit that does not match the column address fetched from the first storing unit, And comparing the number of unmatched row addresses and the number of unmatched column addresses with the number of remaining storage spaces of the first storage unit in which address information of the failed cell is not stored, And a comparison unit for comparing the first and second signals.

Wherein the controller is further configured to: store a row address stored in the selected row address storage space and column address storage space of the first storage unit, respectively, if the number of the inconsistent row addresses and the number of unmatched column addresses is less than or equal to the number of the remaining storage spaces And a row and a column of the cell array corresponding to the column address and a row and a column of the cell array corresponding to the mismatched row address and the mismatched column address with the spare line have.

A memory repair method according to an embodiment of the present invention is a method for repairing a memory by replacing a row or a column including a fault cell in a cell array with a spare line, Storing in a second storage unit; Determining a line of the cell array including at least a part of the fault cells as a line to be replaced by the spare line; A spare line for repairing the faulty cell of the address information stored in the first storage unit based on the address information of the faulty cell stored in the first and second storage units, Analyzing whether a spare line for repairing a spare line is duplicated; And secondly determining a line to be replaced with the spare line of the cell array based on the analysis result.

Wherein if the row address and the column address of the failed cell do not match the row address and the column address of the failed cell previously stored in the first storage unit, 1 in a storage unit; And if a row address or a column address of the failed cell coincides with a row address or a column address of a previously stored fault cell in the first storage unit, And storing an address that does not match the column address in the second storage unit.

Storing the row address or the column address of the corresponding fault cell that does not match the row address or the column address of the previously stored fault cell with the stored row address or column address of the previously stored fault cell In a row address storage space or a column address storage space of the second storage unit corresponding to the row address storage space or the column address storage space of the first storage unit.

Wherein the first determining step comprises: if the row address or column address of another failed cell matches the row address or column address of the corresponding failed cell that matches the row address or column address of the pre-stored failed cell, And firstly determining in the array as a line to replace the pre-stored fault cell, the row or column of addresses that coincide among the row or column addresses of the fault cell and the fault cell, with the spare line .

The memory repair method may further include the step of determining the memory as a non-repairable memory if the first storage unit is insufficient to store the address information of the faulty cell.

Wherein the analyzing step comprises the steps of: selecting a row address storage space or a column address storage space for each storage space of the first storage unit, and storing the selected row address storage space or column address storage space in the first storage unit, Selecting a negative row address storage space or column address storage space; Retrieving the row address from the selected row address storage space of the first storage unit, retrieving the row address from the selected row address storage space of the second storage unit, fetching the column address from the selected column address storage space of the first storage unit Retrieving a column address from the selected column address storage space of the second storage; And a row address fetched from the first storage unit and a row address fetched from the second storage unit are compared with each other to determine whether the row address matches the row address fetched from the first storage unit and the row address fetched from the second storage unit, And comparing the column addresses to determine whether they match or not.

Wherein the second determining step comprises the steps of: determining that all of the row addresses retrieved from the second storage match with at least a part of the row addresses retrieved from the first storage, A row and column of the cell array corresponding to a row address and a column address respectively stored in the selected row address storage space and column address storage space of the first storage unit, To the row and column to replace the spare line with the spare line.

Wherein the step of analyzing comprises the steps of: comparing the unmatched row address fetched from the second storage unit that does not match the row address fetched from the first storage unit, and the second column address not matching the column address fetched from the first storage unit, Counting the number of unmatched column addresses retrieved from the storage unit; And comparing the number of unmatched row addresses and the number of unmatched column addresses with the number of remaining storage spaces of the first storage unit in which the address information of the failed cell is not stored.

Wherein the second determining step comprises: if the number of unmatched row addresses and the number of unmatched column addresses are less than or equal to the number of the remaining storage spaces, determining the second row in the selected row address storage space and column address storage space of the first storage unit A row and column of the cell array corresponding to the stored row address and column address, respectively, and a row and column for replacing the row and column of the cell array corresponding to the non-matching row address and the non-matching column address with the spare row And may further include a step of secondarily determining.

A memory chip according to an embodiment of the present invention includes a cell array composed of a plurality of rows and columns; At least one spare line; And a repair device for repairing the memory by replacing a row or column containing the faulty cell in the cell array with the spare line, wherein the repair device comprises: first and second memory cells for storing address information of the faulty cell in the cell array; 2 storage unit; A spare line for repairing the faulty cell of the address information stored in the first storage unit based on the address information of the faulty cell stored in the first and second storage units, A redundancy analyzer for analyzing the redundancy of a spare line for repairing the spare line; And first determining a line to replace the line of the cell array including at least a part of the fault cells with the spare line while storing address information of the faulty cell in the first and second storage units, And a control unit for determining a line to be replaced with the spare line of the cell array based on the analysis result of the cell array.

A memory repair method according to an embodiment of the present invention may be implemented as a program that can be executed by a computer and recorded in a computer-readable recording medium.

A memory repair method in accordance with an embodiment of the present invention may be implemented as a computer program stored on a medium for execution in association with the computer.

According to the embodiment of the present invention, the repair rate can be increased with relatively small hardware.

1 is an exemplary block diagram of a memory chip according to an embodiment of the invention.
2 is an exemplary block diagram of a repair device in accordance with an embodiment of the present invention.
FIG. 3 is an exemplary diagram schematically illustrating storage spaces of first and second storage units according to an embodiment of the present invention. FIG.
FIGS. 4 to 9 are exemplary diagrams for explaining a process of repairing a faulty cell primarily while collecting fault information according to an embodiment of the present invention.
10 is an exemplary circuit diagram of a redundancy analysis unit according to an embodiment of the present invention.
11 is an exemplary diagram for explaining a process of secondary repair of a fault cell by analyzing redundancy according to an embodiment of the present invention.
12 is an exemplary flow diagram of a memory repair method in accordance with an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached hereto.

Embodiments of the present invention can repair faulty cells in the course of collecting fault information to reduce fault information stored for memory repair. Also, embodiments of the present invention can increase the repair rate by analyzing the redundancy using the stored failure information.

As a result, according to the embodiment of the present invention, it is possible to greatly reduce the size of the hardware used for storing the failure information and reading and analyzing the stored failure information to determine the repair algorithm, and the repair rate And the repair rate close to 100% can be achieved.

1 is an exemplary block diagram of a memory chip 100 in accordance with one embodiment of the present invention.

As shown in FIG. 1, the memory chip 100 may include a cell array 110, a spare line 120, and a repair device 130.

The cell array 110 may include a plurality of rows and columns in which bit cells storing data are arranged in a matrix structure. The spare line 120 is also a memory line made up of bit cells, which is used to repair a memory failure by replacing a line, i.e., a row or column, that contains a fault cell in the cell array 110. At least one of the spare lines 120 may be provided in the memory chip 100 and may include row spare lines 121 and 122 for replacing rows of the cell array 110 when a plurality of spare lines are provided, And column spare lines 123 and 124 for replacing the columns of the array 110. [

The repair device 130 may repair the memory by replacing the row or column containing the fault cell in the cell array 110 with the spare line 120. [ As shown in FIG. 1, the repair device 130 according to the embodiment of the present invention may be a built-in module provided in the chip 100.

2 is an exemplary block diagram of a repair device 130 in accordance with an embodiment of the present invention.

2, the repair apparatus 130 may include a first storage unit 131, a second storage unit 132, a redundancy analysis unit 133, and a controller 134.

The first storage unit 131 may store address information of a fault cell in the cell array 110. Similarly, the second storage unit 132 may store the address information of the faulty cell in the cell array 110.

According to an embodiment of the present invention, the first storage unit 131 may be a content addressable memory (CAM), and the second storage unit 132 may be a register. 2 storage unit is not limited to this.

The redundancy analyzer 133 may be configured to recover a fault cell of the address information stored in the first storage unit 131 based on the address information of the fault cell stored in the first and second storage units 131 and 132 It is possible to analyze the redundancy of the spare line and the spare line for repairing the fault cell of the address information stored in the second storage unit 132. That is, the redundancy analysis unit 133 may analyze the redundancy based on the failure information stored in the first and second storage units 131 and 132 to derive an optimal algorithm for repairing the memory.

The controller 134 stores the address information of the fault cell in the first and second storage units 131 and 132 and transfers the line of the cell array 110 including at least a part of the fault cells to the spare line 120. [ Can be determined primarily by the line to be replaced by. The control unit 134 may determine a line to be replaced with the spare line 120 of the cell array 110 based on the analysis result of the redundancy analysis unit 133. [

FIG. 3 is an exemplary diagram schematically illustrating storage spaces of the first and second storage units 131 and 132 according to an embodiment of the present invention.

Referring to FIG. 3, each of the first and second storage units 131 and 132 may include at least one storage space. The number of storage spaces may be equal to the number of spare lines 120 provided in the chip 100. The first and second storage units 131 and 132 shown in FIG. 3 include four storage spaces, respectively, but the number of storage spaces may be changed according to the number of the spare lines 120.

According to the embodiment of the present invention, each storage space of the first storage unit 131 and each storage space of the second storage unit 132 may correspond one to the other. As shown in FIG. 3, the first to fourth storage spaces of the first storage unit 131 may correspond to the first to fourth storage spaces of the second storage unit 132, respectively.

According to an embodiment of the present invention, the first and second storage units 131 and 132 may include a row address storage space for storing a row address of a failed cell and a column address storage space for storing a column address . The row address storage space of the first storage unit 131 corresponds to the row address storage space of the second storage unit 132 and the column address storage space of the first storage unit 131 corresponds to the row address storage space of the second storage unit 132. [ The address storage space of the memory 132 may correspond to the column address storage space.

The embodiment of the present invention firstly repairs at least a part of a fault cell while storing address information of a fault cell, i.e., a row address and a column address, in the first and second storage units 131 and 132 having the above- The failure information stored in the storage unit for memory repair can be greatly reduced.

FIGS. 4 to 9 are exemplary diagrams for explaining a process of repairing a faulty cell primarily while collecting fault information according to an embodiment of the present invention.

The cell array 110 shown in FIGS. 4 to 9 has a 4 × 4 matrix structure. The location of the faulty cell X in the cell array 110 is (0, 0), (1, 0) (1, 1), (2, 1), (0, 3) and (3, 0). The spare line 120 is composed of two row spare lines and two column spare lines, and a total of four spare lines 120 are provided in the chip 100.

The controller 134 may collect at least one of the faulty cells by collecting the faulty information and storing the faulty information in the first and second storage units 131 and 132.

According to the embodiment of the present invention, if the row address and the column address of the failed cell do not match the row address and column address of the previously stored fault cell in the first storage unit 131, And store the row address and the column address of the cell in the first storage unit 131.

If the row address or the column address of the failed cell coincides with the row address or the column address of the previously stored fault cell in the first storage unit 131, the controller 134 reads the row address and column address of the corresponding fault cell, It is possible to store, in the second storage unit 132, an address that does not match the row address and the column address of the failure cell previously stored in the first storage unit 131 among the addresses.

For example, referring to FIG. 4, the controller 134 stores a row address and a column address of a first fault cell having an address of (0, 0) in a storage unit. Since the address information of the failed cell is not stored in the first storage unit 131 and all storage spaces are empty, the row address '0' and the column address '0' of the first failed cell are stored in the first storage unit 131, / RTI >

5, the controller 134 stores the row address and column address of the second fault cell having the address (1, 0) in the storage unit. Since the column address '0' of the row address '1' and the column address '0' of the second fault cell coincides with the column address '0' of the first fault cell stored in the first storage unit 131, 0 " of the first stored fault cell among the row address '1' and the column address '0' of the second fault cell, that is, the address that does not match the column address '0' And stores the cell row address '1' in the second storage unit 132.

Next, referring to FIG. 6, the controller 134 stores the row address and the column address of the third fault cell having the address (1, 1) in the storage unit. Since the row address '1' and the column address '1' of the third fault cell do not coincide with the row address '0' and the column address '0' of the first fault cell stored in the first storage unit 131, The controller 134 stores the row address '1' and the column address '1' of the third failed cell in the first storage unit 131.

Next, referring to FIG. 7, the controller 134 stores the row address and the column address of the fourth fault cell having the address (2, 1) in the storage unit. The column address '1' among the row address '2' and the column address '1' of the fourth fault cell coincides with the column address '1' of the third fault cell previously stored in the first storage unit 131, 134 is an address that does not match the row address '1' and the column address '1' of the previously stored third fault cell among the row address '2' and the column address '1' of the fourth fault cell, 2 'in the second storage unit 132. The second storage unit 132 stores the row address " 2 "

Next, referring to FIG. 8, the controller 134 stores the row address and column address of the fifth fault cell having the address (0, 3) in the storage unit. Since the row address '0' among the row address '0' and the column address '3' of the fifth fault cell coincides with the row address '0' of the first fault cell stored in the first storage unit 131, 134 is an address that does not match the row address '0' and the column address '0' of the first stored fault cell among the row address '0' and the column address '3' of the fifth fault cell, And stores the column address '3' in the second storage unit 132.

According to the embodiment of the present invention, the control unit 134 determines whether a row address or a column address of another failed cell matches a row address or column address of a previously stored fault cell in the first storage unit 131, A row or column of addresses that coincide among the row address or column address of the previously stored fault cell, the corresponding fault cell, and the other fault cell in the cell array 110 It can be determined primarily as a line to be replaced with the spare line 120. [

For example, referring to FIG. 9, the controller 134 stores the row address and the column address of the sixth failed cell having the address (3, 0) in the storage unit. In this case, among the row address '3' and the column address '0' of the sixth fault cell, the column address '0' is not only the column address '0' of the first fault cell stored in the first storage unit 131, The controller 134 determines that the first fault cell, the second fault cell, and the sixth fault cell, which is the other fault cell, are stored in the cell array 110, It is possible to first determine a line to replace the address of the row address or the column address, that is, the address of the column address '0' by the spare line 120.

In this manner, the embodiment of the present invention can repair at least some of the faulty cells primarily while storing the fault information in the first and second storage units 131 and 132, thereby reducing the fault information stored for repair .

According to an embodiment of the present invention, when there is insufficient storage space for storing address information of a fault cell in the first storage unit 131, the controller 134 may determine the memory as a non-repairable memory. The lack of storage space means that there is no usable spare line, so that the control unit 134 can determine the memory as a non-repairable memory.

Once the fault information collection is complete, a redundancy analysis can be performed. According to the embodiment of the present invention, the controller 134 selects a row address storage space or a column address storage space for each storage space of the first storage unit 131 for redundancy analysis, The row address storage space or the column address storage space of the second storage unit 132 corresponding to the selected row address storage space or column address storage space of the first storage unit 131 may be selected.

Then, the redundancy analyzer 133 fetches the row address from the selected row address storage space of the first storage unit 131, and reads the row address from the selected row address storage space of the second storage unit 132 And compares the row address fetched from the first storage unit 131 with the row address fetched from the second storage unit 132 to determine whether they match or not. The redundancy analyzer 133 retrieves a column address from the selected column address storage space of the first storage unit 131 and a column address from the selected column address storage space of the second storage unit 132 And a column address fetched from the first storage unit 131 and a column address fetched from the second storage unit 132 are compared with each other to determine whether they match.

10 is an exemplary circuit diagram of the redundancy analysis unit 133 according to an embodiment of the present invention.

10, the redundancy analyzer 133 receives a row address and a column address from the row address storage space and the column address storage space of the first storage unit 131 and the second storage unit 132 It is possible to judge whether or not the address and the address match with each other.

In order to perform the redundancy analysis, the redundancy analysis unit 133 includes multiplexers MUX1 to MUX4 for fetching address values from storage spaces of the first and second storage units 131 and 132, And XOR gates XOR1 to XOR8 for XORing the values.

According to the embodiment of the present invention, the control unit 134 determines that all the row addresses retrieved from the second storage unit 132 match at least a part of the row addresses retrieved from the first storage unit 131, When all the column addresses retrieved from the first storage unit 131 match at least a part of the column addresses retrieved from the first storage unit 131, And the row and column of the cell array 110 corresponding to the row address and the column address respectively stored in the cell array 110 and the spare line 120, respectively.

11, the redundancy analyzer 133 may store a row address fetched from the second storage unit 132 that does not match the row address fetched from the first storage unit 131, that is, And a column address fetched from the second storage unit 132 that does not match the column address fetched from the first storage unit 131, that is, the number of non-matching column addresses, And a comparing unit comparing the number of matched column addresses with the number of remaining storage spaces (i.e., empty storage spaces) in which the address information of the failed cells among the storage spaces of the first storage unit 131 is not stored .

In this case, if the number of mismatching row addresses and the number of mismatching column addresses are less than or equal to the number of remaining storage spaces, the controller 134 may select the selected row address storage spaces and columns in the first storage unit 131 The row and column of the cell array 110 corresponding to the row address and the column address respectively stored in the address storage space and the row and column of the cell array 110 corresponding to the non-matching row address and the non- May alternatively be determined to be rows and columns to replace the spare line 120 with the spare line 120.

11 is an exemplary diagram for explaining a process of secondary repair of a fault cell by analyzing redundancy according to an embodiment of the present invention.

11, row addresses of '0', '1' and '2' are stored in the first to third row address storage spaces pr1 to pr3 of the first storage unit 131, 0 ',' 1 'and' 4 'column addresses are stored in the first to third column address storage spaces pc1 to pc3 of the unit 131, The spaces pr4 and pc4 are assumed to be empty. In addition, row addresses of '1', '2' and '4' are stored in the first to third row address storage spaces rr1 to rr3 of the second storage unit 132, 3 ',' 3 'and' 4 'column addresses are stored in the first to third column address storage spaces rc1 to rc3 of the row address storage area 132, (rr4 and rc4) are assumed to be empty.

11, the controller 134 controls the first and second row address storage spaces pr1 and pr2 of the storage spaces of the first storage unit 131 and the third and fourth row address storage spaces pr1 and pr2, The first and second row address storage spaces rr1 and rr2 of the second storage unit 132 corresponding to the selected storage space of the first storage unit 131, rr2 and the third and fourth column address storage spaces rc3 and rc4 are selected from the selected row address storage spaces pr1 and pr2 of the first storage unit 131, 1 'and' 2 'from the selected row address storage spaces rr1 and rr2 of the second storage unit 132, and outputs the row addresses' 1' and '2' to the MUX1 'And MUX2'.

Then, the redundancy analyzer 133 receives row addresses' 0 'and' 1 'fetched from the first storage unit 131 through XOR1 to XOR4 and a row address' '1' and '2' can be compared to determine whether they match each other.

Similarly, the redundancy analyzer 133 reads the column address '4' from the selected column address storage spaces pc3 and pc4 of the first storage unit 131 and outputs the column address '4' through the MUX3 and the MUX4, 4 'from the selected column address storage spaces rc3 and rc4 of the memory cells 132 and 132 and output through the MUX3' and the MUX4 '.

Then, the redundancy analysis unit 133 reads the column address '4' fetched from the first storage unit 131 and the column address '4' fetched from the second storage unit 132 through XOR5 to XOR8 It is possible to determine whether or not they match with each other.

As a result of the determination, since the output value of AND3 is 0, the column address '4' fetched from the second storage unit 132 matches the column address '4' fetched from the first storage unit 131, while AND1 and AND2 The row address '1' of the row addresses fetched from the second storage unit 132 matches the row address '1' fetched from the first storage unit 131, '2' does not match the row address fetched from the first storage unit 131.

Meanwhile, according to an embodiment of the present invention, when the storage space of the second storage unit 132 is empty, the corresponding AND gate may be configured to always output '0'. 11, since the address values are not stored in the fourth storage spaces rr4 and rc4 of the second storage unit 132 and are empty, the corresponding AND4 outputs '0'.

As described above, all of the row addresses fetched from the second storage unit 132 coincide with at least a part of the row addresses fetched from the first storage unit 131, and the column addresses fetched from the second storage unit 132 The row address and the column address stored in the selected row address storage space and the column address storage space of the first storage unit 131 are stored in the column address storage unit 131, It is possible to determine the rows and columns of the corresponding cell array 110 as rows and columns to be replaced with spare lines to complete the memory repair.

However, since the row address '2' fetched from the second storage unit 132 does not match any of the row addresses '0' and '1' fetched from the first storage unit 131 in the embodiment of FIG. 11 , The above conditions are not satisfied.

11, the comparator compares the non-matching row address '2' fetched from the second storage unit 132, which does not match the row addresses '0' and '1' fetched from the first storage unit 131, (Not shown in FIG. 11) retrieved from the second storage unit 132 that does not match the column address '4' retrieved from the first storage unit 131, The row address and the number of unmatched column addresses (i.e., 1) and the number of remaining storage spaces (i.e., 1) of the first storage unit 131 can be compared.

As a result, the controller 134 determines that the number of unmatched row addresses and the number of unmatched column addresses (i.e., 1) is smaller than the number of remaining storage spaces (i.e., 1) of the first storage unit 131 0 'and' 1 'and column address' 4', respectively, stored in the selected row address storage spaces pc1 and pc2 and column address storage spaces pr3 and pr4 of the first storage unit 131, And the row and column of the cell array 110 corresponding to the non-matching row address '2' and the non-matching column address (none in FIG. 11) The memory can be repaired by secondary determination with rows and columns to replace with lines.

According to an embodiment of the present invention, when the number of unmatched row addresses and the number of unmatched column addresses are greater than the number of remaining storage spaces in the first storage unit 131, It can be determined that repair is not possible with the selected row address and column address.

If the total number of unmatched row addresses and unmatched column addresses is greater than the number of remaining storage spaces, the number of remaining storage spaces in the first storage unit 131 is equal to the number of available spare lines. The control unit 134 can determine the memory to be a non-repairable memory. In this case, the controller 134 can determine the memory to be a non-repairable memory.

The redundancy analyzer 133 may further include a repair tag checker, as shown in FIG. 11, since the line to be replaced by the spare line firstly includes a line to be replaced with the spare line.

The repair tag check unit receives a control signal, which is input to the redundancy analyzer 133 and selects a row address storage space or a column address storage space for each storage space of the first storage unit 131, Or a row address storage space or a column address storage space of the first storage unit 131 storing the column address, the storage area of the first storage unit 131 selected by the control signal, It is possible to determine whether or not the storage tag 131 includes the storage space of the first storage unit 131 identified by the repair tag.

When the storage space of the first storage unit 131 selected by the control signal includes a storage space of the first storage unit 131 identified by the repair tag, the control unit 134 transmits the corresponding control signal It can be determined that the row address and the column address determined as the basis are valid.

On the other hand, when the storage space of the first storage unit 131 selected by the control signal does not include the storage space of the first storage unit 131 identified by the repair tag, It can be determined that repair is impossible with the row address and the column address determined secondarily based on the control signal.

12 is an exemplary flow diagram of a memory repair method 200 in accordance with an embodiment of the present invention.

The memory repair method 200 may be performed by the memory repair apparatus 100 according to the embodiment of the present invention described above to repair the memory.

12, the memory repair method 200 is a method in which the memory repair apparatus 100 replaces a row or column containing a faulty cell X in the cell array 110 with a spare line 120, The method comprising the steps of: storing address information of the faulty cell in first and second storage units (131, 132) (S210); determining a line of the cell array (110) The first storage unit 131 and the second storage unit 132. The first storage unit 131 and the second storage unit 132 are connected to the first storage unit 131 and the second storage unit 132, A step S230 of analyzing whether a spare line for repairing the faulty cell of the address information stored in the second storage unit 131 and a spare line for repairing the faulty cell of the address information stored in the second storage unit 132 are duplicated, Based on the result, the cell array (110) A line to be replaced by the line 120 may include a step (S240) to determine the secondary.

According to an embodiment of the present invention, the storing step S210 may be performed when the row address and the column address of the failed cell do not match the row address and the column address of the previously stored fault cell in the first storage unit 131 , Storing the row address and column address of the corresponding fault cell in the first storage unit 131 (see FIGS. 4 and 6); And if the row address or column address of the failed cell coincides with the row address or column address of the previously stored fault cell in the first storage unit 131, Storing an address that does not match the row address and the column address of the previously stored fault cell in the second storage unit 132. [

The step of storing in the second storage unit 132 may include storing a row address or a column address of a corresponding fault cell that does not match the row address or the column address of the fault cell stored in the first storage unit 131, A row address storage space or column address of the second storage unit 132 corresponding to the row address storage space or the column address storage space of the first storage unit 131 in which the row address or the column address of the previously stored fault cell is stored And storing them in a storage space (see Figs. 5, 7, and 8).

According to an embodiment of the present invention, the first determining step S220 may be such that the row address or column address of another failed cell is the row address or column address of the failed cell previously stored in the first storage unit 131 The row address or the column address of the pre-stored fault cell, the corresponding fault cell and the fault cell in the cell array 110, if the row address or the column address of the corresponding fault cell coincides with the row address or the column address of the corresponding fault cell, (See FIG. 9) as a line to replace a row or column of addresses to be replaced with a spare line 120. [0033] FIG.

According to an embodiment of the present invention, when there is insufficient storage space for storing address information of a fault cell in the first storage unit 131, the memory repair method 200 may determine that the memory is a non-repairable memory .

According to an exemplary embodiment of the present invention, the analyzing step S230 may include selecting a row address storage space or a column address storage space for each storage space of the first storage unit 131, Selecting a row address storage space or a column address storage space of the second storage unit 132 corresponding to the selected row address storage space or column address storage space of the second storage unit 132; A row address is retrieved from the selected row address storage space of the first storage unit 131, a row address is retrieved from the selected row address storage space of the second storage unit 132, Loading a column address from a selected column address storage space of the second storage unit 132 and a column address from a selected column address storage space of the second storage unit 132; And a row address fetched from the first storage unit 131 is compared with a row address fetched from the second storage unit 132 to determine whether or not the row address matches the row address fetched from the first storage unit 131, And comparing the column address fetched from the second storage unit 132 and determining whether the column address matches.

According to an exemplary embodiment of the present invention, the second determining step S240 may include a step S240 of determining that all row addresses retrieved from the second storage unit 132 are at least one of the row addresses retrieved from the first storage unit 131 And if all of the column addresses retrieved from the second storage unit 132 coincide with at least a part of the column addresses retrieved from the first storage unit 131, And a row and column to replace the row and column of the cell array 110 corresponding to the row address and column address respectively stored in the selected row address storage space and column address storage space with the spare line 120 can do.

According to an exemplary embodiment of the present invention, the analyzing step S230 may include comparing an unmatched row address (e.g., address) fetched from the second storage unit 132, which does not match a row address fetched from the first storage unit 131, And counting the number of inconsistent column addresses retrieved from the second storage unit (132) that does not match the column address retrieved from the first storage unit (131). And comparing the number of the unmatched row addresses and the number of the unmatched column addresses with the number of remaining storage spaces of the first storage unit 131 in which the address information of the failed cell is not stored.

In this case, if the number of unmatched row addresses and the number of unmatched column addresses is less than or equal to the number of remaining storage spaces in the first storage unit 131, the second determining step S240 may include: 1 row and column of the cell array 110 corresponding to the row address and column address respectively stored in the selected row address storage space and column address storage space of the storage unit 131, And then alternately determining the row and column of the cell array 110 corresponding to the address as the row and column to be replaced by the spare line 120. [

The memory repair method 200 may be stored in a computer-readable recording medium that is manufactured as a program for execution on a computer. The computer-readable recording medium includes all kinds of storage devices in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like. The memory repair method 200 may also be implemented as a computer program stored on a medium for execution in association with the computer.

While the present invention has been described with reference to the exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Those skilled in the art will appreciate that various modifications may be made to the embodiments described above. The scope of the present invention is defined only by the interpretation of the appended claims.

100: Memory chip
110: cell array
120: Spare line
130: Repairing device
131: first storage unit
132: second storage unit
133: Redundancy analysis section
134:
X: fault cell

Claims (22)

A first storage unit for storing address information of a fault cell in the cell array;
A spare line for repairing the faulty cell of the address information stored in the first storage unit based on the address information of the faulty cell stored in the first and second storage units, A redundancy analyzer for analyzing the redundancy of a spare line for repairing the spare line; And
The address of the failed cell is stored in the first and second storage units, and the line of the cell array including at least a part of the failed cells is replaced with the spare line. A control unit which determines a line to be replaced with the spare line of the cell array based on the analysis result;
Lt; / RTI > The method according to claim 1,
The control unit includes:
If the row address and the column address of the failed cell do not match the row address and column address of the previously stored fault cell in the first storage unit, the row address and the column address of the corresponding fault cell are stored in the first storage unit Memory repair device. The method according to claim 1,
The control unit includes:
When the row address or the column address of the fault cell coincides with the row address or the column address of the fault cell stored in the first storage unit, the row address and column address of the fault cell, And stores an address that does not match the column address in the second storage unit. The method of claim 3,
The control unit includes:
Storing a row address or a column address of a corresponding fault cell that does not match the row address or the column address of the previously stored fault cell into a row address storage space or column of the first storage unit in which the row address or column address of the pre- In a row address storage space or a column address storage space of the second storage unit corresponding to the address storage space. 5. The method of claim 4,
The control unit includes:
If the row address or column address of another failed cell coincides with the row address or column address of the corresponding failed cell that matches the row address or column address of the pre-stored failed cell, And a line to replace the row or column of addresses that coincide among the row address or column address of the corresponding fault cell and the other fault cell to the spare line. 3. The method of claim 2,
The control unit includes:
And determines the memory as a non-repairable memory if the first storage unit is insufficient to store the address information of the faulty cell. 6. The method of claim 5,
The control unit includes:
A row address storage space or a column address storage space for each storage space of the first storage unit and a row address storage space of the second storage unit corresponding to the selected row address storage space or column address storage space of the first storage unit, Select the column address storage space,
Wherein the redundancy analyzer comprises:
A row address is fetched from a selected row address storage space of the first storage unit, a row address is fetched from a selected row address storage space of the second storage unit, a row address fetched from the first storage unit, And compares the row addresses retrieved from the row addresses to determine whether they match or not,
A column address is fetched from the selected column address storage space of the first storage unit, a column address is fetched from the selected column address storage space of the second storage unit, a column address fetched from the first storage unit, And compares the column addresses retrieved from the column addresses. 8. The method of claim 7,
The control unit includes:
All of the row addresses retrieved from the second storage unit coincide with at least a part of the row addresses retrieved from the first storage unit and all of the column addresses retrieved from the second storage unit are fetched from the first storage unit The row and column of the cell array corresponding to the row address and column address respectively stored in the selected row address storage space and column address storage space of the first storage unit are replaced with the spare line, And a memory repair device that determines the memory secondarily. 9. The method of claim 8,
Wherein the redundancy analyzer comprises:
A non-matching row address fetched from the second storing unit that does not match a row address fetched from the first storing unit, and a non-matching row address fetched from the second storing unit that does not match the column address fetched from the first storing unit, And a comparing unit for counting the number of matched column addresses and for comparing the number of matched row addresses and the number of matched column addresses with the number of remaining storage spaces in the first storage unit for which address information of the failed cells is not stored Memory repair device. 10. The method of claim 9,
The control unit includes:
Matching row address and the unmatched column address is less than or equal to the number of the remaining storage spaces, a row address and a column address stored respectively in the selected row address storage space and column address storage space of the first storage unit And the row and column of the corresponding cell array and the rows and columns of the cell array corresponding to the non-matching row address and the non-matching column address are to be replaced with the spare line. A method of repairing memory by replacing a row or column containing a fault cell in a cell array with a spare line,
Storing address information of the failed cell in first and second storage units;
Determining a line of the cell array including at least a part of the fault cells as a line to be replaced by the spare line;
A spare line for repairing the faulty cell of the address information stored in the first storage unit based on the address information of the faulty cell stored in the first and second storage units, Analyzing whether a spare line for repairing a spare line is duplicated; And
Secondly determining a line to be replaced with the spare line of the cell array based on the analysis result;
≪ / RTI > 12. The method of claim 11,
Wherein the storing comprises:
If the row address and the column address of the failed cell do not match the row address and column address of the previously stored fault cell in the first storage unit, the row address and the column address of the corresponding fault cell are stored in the first storage unit step; And
When the row address or the column address of the fault cell coincides with the row address or the column address of the fault cell stored in the first storage unit, the row address and column address of the fault cell, Storing an address that does not match the column address in the second storage unit;
≪ / RTI > 13. The method of claim 12,
Wherein the storing in the second storage unit comprises:
Storing a row address or a column address of a corresponding fault cell that does not match the row address or the column address of the previously stored fault cell into a row address storage space or column of the first storage unit in which the row address or column address of the pre- Storing in a row address storage space or a column address storage space of the second storage unit corresponding to the address storage space. 14. The method of claim 13,
Wherein the first determining comprises:
If the row address or column address of another failed cell coincides with the row address or column address of the corresponding failed cell that matches the row address or column address of the pre-stored failed cell, Determining as a line to replace the row or column of addresses that coincide among the row address or column address of the corresponding fault cell and the other fault cell with the spare line. 13. The method of claim 12,
Further comprising the step of determining the memory as a non-repairable memory if the first storage unit is insufficient to store the address information of the faulty cell. 15. The method of claim 14,
Wherein the analyzing comprises:
A row address storage space or a column address storage space for each storage space of the first storage unit and a row address storage space of the second storage unit corresponding to the selected row address storage space or column address storage space of the first storage unit, Selecting a column address storage space;
Retrieving the row address from the selected row address storage space of the first storage unit, retrieving the row address from the selected row address storage space of the second storage unit, fetching the column address from the selected column address storage space of the first storage unit Retrieving a column address from the selected column address storage space of the second storage; And
A row address fetched from the first storage unit is compared with a row address fetched from the second storage unit to determine whether or not the row address matches the row address fetched from the first storage unit and the column address fetched from the second storage unit, Comparing the addresses to determine whether they match or not;
≪ / RTI > 17. The method of claim 16,
Wherein the second determining step comprises:
All of the row addresses retrieved from the second storage unit coincide with at least a part of the row addresses retrieved from the first storage unit and all of the column addresses retrieved from the second storage unit are fetched from the first storage unit The row and column of the cell array corresponding to the row address and column address respectively stored in the selected row address storage space and column address storage space of the first storage unit are replaced with the spare line, And < / RTI > 18. The method of claim 17,
Wherein the analyzing comprises:
A non-matching row address fetched from the second storing unit that does not match a row address fetched from the first storing unit, and a non-matching row address fetched from the second storing unit that does not match the column address fetched from the first storing unit, Counting the number of matching column addresses; And
Comparing the number of unmatched row addresses and the unmatched column addresses with the number of remaining storage spaces of the first storage unit in which address information of the failed cell is not stored;
Further comprising the steps of: 19. The method of claim 18,
Wherein the second determining step comprises:
Matching row address and the unmatched column address is less than or equal to the number of the remaining storage spaces, a row address and a column address stored respectively in the selected row address storage space and column address storage space of the first storage unit And secondarily determining the rows and columns of the corresponding cell array and the rows and columns of the cell array corresponding to the mismatched row address and the mismatched column address with the spare line Memory repair method. A cell array composed of a plurality of rows and columns;
At least one spare line; And
And a repair device for repairing the memory by replacing a row or column containing the faulty cell in the cell array with the spare line, the repair device comprising:
A first storage unit for storing address information of a fault cell in the cell array;
A spare line for repairing the faulty cell of the address information stored in the first storage unit based on the address information of the faulty cell stored in the first and second storage units, A redundancy analyzer for analyzing the redundancy of a spare line for repairing the spare line; And
The address of the failed cell is stored in the first and second storage units, and the line of the cell array including at least a part of the failed cells is replaced with the spare line. A control unit which determines a line to be replaced with the spare line of the cell array based on the analysis result;
≪ / RTI > A computer-readable recording medium,
A recording medium on which a program for executing a memory repair method according to any one of claims 11 to 19 is recorded. A computer program stored in a medium for executing a memory repair method according to any one of claims 11 to 19 in combination with the computer.

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