KR101543434B1 - Manufacturing method of semiconductor memory system - Google Patents

Abstract

The present invention relates to a semiconductor memory system, and more particularly, to a method of manufacturing a semiconductor memory system.

A method of manufacturing a semiconductor memory system according to the present invention includes: storing a system code in a first nonvolatile memory; Assembling the first nonvolatile memory and the second nonvolatile memory; And copying the system code stored in the first nonvolatile memory to the second nonvolatile memory, wherein the temperature at which the first nonvolatile memory is capable of holding data is determined by the second non- Is higher than the temperature that can be maintained.

In a semiconductor memory system according to the present invention, data is stored in a variable resistance memory device after assembly of a semiconductor memory system. According to the present invention, the reliability of the semiconductor memory system is improved.

Description

TECHNICAL FIELD [0001] The present invention relates to a manufacturing method of a semiconductor memory system,

The present invention relates to a semiconductor memory system, and more particularly, to a method of manufacturing a semiconductor memory system.

Semiconductor memory devices are used to store data. Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. The data stored in the volatile memory device is consumed when the power supply is interrupted. On the other hand, the data stored in the nonvolatile memory device does not disappear even if the power supply is interrupted.

Since the nonvolatile memory device can store data at a low power, it is attracting attention as a storage medium for portable devices. One type of non-volatile memory device is a flash memory device and a variable resistance memory device. In the following, a flash memory device and a variable resistance memory device are described as examples. However, the scope of the present invention is not limited thereto and can be applied to other memory devices (for example, FRAM, MRAM, DRAM, etc.).

Variable resistance memory devices include ferroelectric RAM (FRAM) using a ferroelectric capacitor, magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) film, and chalcogenide alloys A phase change memory device, and the like. Particularly, the phase change memory device is relatively simple to manufacture and can realize a large-capacity memory at a low cost.

A typical variable resistance memory device has characteristics that are weak to heat. That is, when the variable resistance memory device is exposed to a high temperature for a certain period of time, the data stored in the variable resistance memory device may be lost. This degrades the reliability of the semiconductor memory system.

It is an object of the present invention to provide a semiconductor memory system having improved reliability by safely holding data stored in a variable resistance memory device.

A method of manufacturing a semiconductor memory system according to the present invention includes: storing a system code in a first nonvolatile memory; Assembling the first nonvolatile memory and the second nonvolatile memory; And copying the system code stored in the first nonvolatile memory to the second nonvolatile memory, wherein the temperature at which the first nonvolatile memory is capable of holding data is determined by the second non- Is higher than the temperature that can be maintained.

In an embodiment, the first nonvolatile memory is a NAND flash memory, and the second nonvolatile memory is a variable resistance memory. And copying the system code stored in the first nonvolatile memory to the second nonvolatile memory, and deleting the system code stored in the first nonvolatile memory. The step of copying the system code stored in the first nonvolatile memory into the second nonvolatile memory is performed only when the system code is not stored in the second nonvolatile memory.

As another embodiment, the method further includes updating a replication flag indicating that the system code stored in the first nonvolatile memory has been copied to the second nonvolatile memory. Volatile memory, and when the replication flag indicates that the system code stored in the first nonvolatile memory has been copied to the second nonvolatile memory, the system code stored in the first nonvolatile memory is copied to the second nonvolatile memory Is omitted. And the system code is data for initialization of the semiconductor memory system.

A memory card according to the present invention includes a semiconductor memory system; And a memory controller configured to control the semiconductor memory system, wherein the semiconductor memory system is manufactured by the method according to claim 1.

A solid state drive according to the present invention includes: a semiconductor memory system; And a memory controller configured to control the semiconductor memory system, wherein the semiconducting memory system is fabricated by the method of claim 1.

In a semiconductor memory system according to the present invention, data is stored in a variable resistance memory device after assembly of a semiconductor memory system. According to the present invention, the reliability of the semiconductor memory system is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

In the following, a NAND flash memory device and a variable resistance memory device are used as an example for explaining the features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. The invention may also be embodied or applied in other embodiments. In addition, the detailed description may be modified or changed in accordance with the viewpoint and use without departing from the scope, technical thought and other objects of the present invention.

1 is a cross-sectional view showing a memory cell of a flash memory device. Referring to FIG. 1, a source S and a drain D are formed on a semiconductor substrate with a channel region interposed therebetween. A floating gate is formed over a channel region with a thin insulating film interposed therebetween. A control gate is formed on the floating gate with an insulating film therebetween. Terminals for applying voltages necessary for program, erase, and read operations are connected to the source S, the drain D, the floating gate, the control gate, and the semiconductor substrate.

In the above-described flash memory device, data is read out by distinguishing a threshold voltage of a memory cell. The threshold voltage of the memory cell is determined by the amount of electrons stored in the floating gate or the charge trap film. The more electrons stored in the floating gate or the charge trap film, the higher the threshold voltage.

2 is a graph showing the threshold voltage distribution of a flash memory cell. Referring to FIG. 2, the horizontal axis represents a threshold voltage (Vth), and the vertical axis represents the number of flash memory cells. In the case of a single level cell (SLC), the threshold voltage of the flash memory cell has one of two states ('S0', 'S1').

When the read voltage Vr is applied to the control gate of the flash memory cell (see FIG. 1), the flash memory cell in the 'S0' state is turned on. On the other hand, the flash memory cell in the 'S1' state is turned off. When the flash memory cell is turned on, current flows through the flash memory cell, and when the flash memory cell is turned off, no current flows through the flash memory cell. Therefore, the data can be distinguished according to whether the flash memory cell is turned on or off.

MP3 players, mobile phones, etc. As a storage device, NAND flash memory devices have been mainly used so far. NAND flash memory devices are superior to other nonvolatile memories in terms of density, write performance, lifetime, impact, and power consumption. However, in recent years, characteristics of other types of nonvolatile memories such as variable resistance memory devices have been improved and mass production has been achieved.

Figures 3 and 4 show memory cells of the variable resistive memory device. Referring to FIG. 3, a memory cell 10 includes a memory element 11 and a select element 12. The storage element 11 is connected between the bit line BL and the selection element 12 and the selection element 12 is connected between the storage element 11 and ground.

The memory element 11 includes a variable resistance material GST. The variable resistance material (GST) is an element whose resistance varies with temperature such as Ge-Sb-Te. The variable resistance material GST has one of two stable states depending on the temperature, that is, a crystal state and an amorphous state. The variable resistance material GST changes into a crystal state or an amorphous state according to a current supplied through the bit line BL. Variable resistance memory devices use this characteristic of the variable resistance material (GST) to program data.

The selection element 12 is composed of an NMOS transistor NT. A word line (WL) is connected to the gate of the NMOS transistor NT. When a predetermined voltage is applied to the word line WL, the NMOS transistor NT is turned on. When the NMOS transistor NT is turned on, the memory element 11 is supplied with current through the bit line BL. In Fig. 1, the memory element 11 is connected between the bit line BL and the selection element 12. Fig. However, the selection element 12 may be connected between the bit line BL and the storage element 11. [

4, the memory cell 20 includes a memory element 21 and a selection element 22. [ The storage element 21 is connected between the bit line BL and the selection element 22 and the selection element 22 is connected between the storage element 21 and ground. The memory element 21 is the same as the memory element 11 of Fig.

The selection element 22 is composed of a diode D. A storage element 21 is connected to the anode of the diode D and a word line WL is connected to the cathode. When the voltage difference between the anode and the cathode of the diode D becomes higher than the threshold voltage of the diode D, the diode D is turned on. When the diode D is turned on, the memory element 21 is supplied with current through the bit line BL.

5 is a graph for explaining characteristics of the variable resistance material GST shown in FIGS. 3 and 4. FIG. In FIG. 5, reference numeral 1 denotes a condition for causing the variable resistance material GST to become an amorphous state, and reference numeral 2 denotes a condition for becoming a crystal state.

The variable resistance material (GST) is heated to a temperature higher than the melting temperature (Tm) for T1 hours and then rapidly quenched to an amorphous state. The amorphous state is commonly referred to as a reset state and stores data '1'. The variable resistance memory device provides a reset current to the variable resistance material (GST) for programming into a reset state.

The variable resistance material GST is heated at a temperature higher than the crystallization temperature Tc and lower than the melting temperature Tm for T2 longer than T1 and gradually cooled to a crystal state. The decision state is also referred to as a set state, and stores data '0'. The variable resistance memory device provides a set current as a variable resistance material (GST) for programming into a set state.

However, the inventors of the present invention have found that some of the variable resistive memories having a high degree of integration are vulnerable to heat, and stored data is lost when exposed to a high temperature state to some extent. Such a data loss does not occur in a normal use environment, but when a variable resistance memory is assembled, it can be exposed to a high temperature for a long time. For example, when a variable resistance memory is attached to a substrate, the variable resistance memory can be exposed to a high temperature for a long time. This causes loss of the system code such as the boot loader, the operating system, and the system file stored in the variable resistor memory, thereby increasing the defect rate of the semiconductor memory system.

To solve this problem, a method of storing the system code in a variable resistor memory using a dedicated facility after assembly has been proposed. In order to avoid the effect of heat, the system code is stored in the variable resistor memory using the dedicated equipment after assembly. However, this method has a disadvantage that an additional interface for transferring data between a dedicated facility for storing the system code and the semiconductor memory system is required.

In the semiconductor memory system according to the present invention, the system code is stored in the variable resistor memory after the variable resistor memory is assembled. The system code to be stored in the variable resistor memory is first stored in the NAND flash memory. NAND flash memory is relatively heat resistant, so it retains data even when exposed to heat during assembly. That is, since data is stored after the variable resistance memory is applied with heat, data loss due to heat can be prevented.

6 is a block diagram showing a semiconductor memory system according to the present invention. 6, a semiconductor memory system 100 according to the present invention includes a processor 110, a NAND flash memory 120, a variable resistor memory 130, a boot ROM 140, and a RAM 150 .

The processor 110 controls the overall operation of the semiconductor memory system 100. For example, the processor 110 may process programs stored in the RAM 150. The NAND flash memory 120 may store the system code. In addition, the NAND flash memory 120 may store user data such as music, moving images, and documents. The system code stored in the NAND flash memory 120 will be copied to the variable resistance memory 130. [

The boot ROM 140 controls operations required for booting the semiconductor memory system 100. For example, the boot ROM 140 may load the boot loader into the RAM 150. The bootloader runs before the operating system is started. The operating system is a program for finishing the tasks required for the kernel to start up properly and finally starting the operating system. The RAM 150 is used as a main memory. The program loaded into the RAM 150 can be executed by the processor.

The NAND flash memory 120 may constitute a memory card or a solid state drive. The processor 110 and the RAM 150 may constitute a host. For example, the semiconductor memory system 100 according to the present invention can be used as a portable media player such as an MP3 player, a PMP, or a notebook computer. The processing result by the processor 110 may be stored in the NAND flash memory 120, the variable resistor memory 130, or the RAM 150. [

It is apparent to those skilled in the art that a power supply is required to supply the power necessary for operation of the semiconductor memory system 100 although not shown in the drawings. When the semiconductor memory system 100 is a mobile device, a battery for supplying operating power to the semiconductor memory system 100 may be further required.

7 is a flowchart showing a method of manufacturing a semiconductor memory system according to the present invention. Referring to FIG. 7, in step S110, the system code is stored in the NAND flash memory. The system code is used to initialize the semiconductor memory system. For example, the system code may be a file system, a device driver, an operating system, or the like.

A file system is required for a personal computer or a mobile device to use a storage device such as a solid state drive or a hard disk. A file system is a structure or software used to store data in a storage device such as a solid state drive or a hard disk.

A device driver is referred to as a device driver, a device controller, or a software driver. A device driver is a computer program created for computer programs to interact with a computer hardware device. Device drivers control the hardware and serve as a bridge between programs that use hardware and peripherals.

Referring again to FIG. 7, in step S120, the NAND flash memory and the variable resistance memory device are assembled on the substrate. During the assembly process, heat may be applied to the NAND flash memory and the variable resistor memory device. However, since the NAND flash memory is relatively heat resistant, the data stored in the NAND flash memory is not lost.

After the assembly, the system code stored in the NAND flash memory is stored in the variable resistor memory in step S130. The manner in which the system code stored in the NAND flash memory is stored in the variable resistor memory will be described in detail with reference to FIG. 8 to be described later.

As described above, since the system code is stored in the variable resistor memory after assembly, data loss in the variable resistor memory due to heat during assembly can be prevented.

FIG. 8 is a flowchart illustrating a system code storing method of a semiconductor memory system according to the present invention. Referring to FIG. 8, a system code storage method of a semiconductor memory system according to the present invention includes steps S210 to S280.

In step S210, the semiconductor memory system is turned on. In step S220, the boot ROM loads the boot loader stored in the NAND flash memory into the RAM. The initialization code previously stored in the boot ROM will initialize the NAND flash memory and RAM. In step S230, the boot loader stored in the RAM is executed.

In step S240, the boot loader detects whether the system code is stored in the variable resistor memory. If the system code is stored in the variable resistor memory, in step S280, the processor executes the system code in the variable resistor memory. On the other hand, if the system code is not stored in the variable resistor memory, step S250 is performed.

In step S250, the system code in the NAND flash memory is copied to the variable resistor memory. In step S260, the system code stored in the NAND flash memory is erased. As the system code is deleted, the storage capacity of the NAND flash memory increases.

However, step S260 may be omitted as needed. In this case, when the system code stored in the variable resistor memory is lost, the system code stored in the NAND flash memory can be replicated in the variable resistor memory again.

In step S270, the replication flag is updated. The duplication flag indicates whether or not the variable resistance memory stores the system code. The processor determines whether to replicate the system code in the NAND flash memory to the variable resistor memory by referring to the replication flag. In step S280, the system code stored in the variable resistor memory is executed to control the semiconductor memory system.

As described above, since the system code is copied from the NAND flash memory to the variable resistance memory after assembling the system, data loss due to heat can be prevented.

In addition, it becomes possible to replace the conventional NOR flash memory with a variable resistance memory, and it becomes possible to utilize the variable resistance memory as a boot image storage space instead of a DRAM consuming a lot of power. That is, the variable resistor memory according to the present invention can be used as a substitute for DRAM.

In the present invention, although the NAND flash memory and the variable resistance memory are described as examples, the scope of the present invention is not limited thereto. The present invention can be applied to a combination of a relatively strong memory and a relatively weak memory relative to the heat applied in the assembly process. That is, the system code may be stored in a first memory relatively strong in terms of the column, then a second memory relatively weak in the column may be assembled with the first memory, and the system code stored in the first memory may be stored in the second memory after the assembly. Here, the first and second memories may be composed of arbitrary memories.

The NAND flash memory 350 or the variable resistor memory according to the present invention may be implemented using various types of packages. For example, the NAND flash memory or variable resistor memory may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) , Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package Package (WSP) or the like.

The semiconductor memory system according to the present invention can also be applied to a solid state drive (SSD). SSD products, which are expected to replace hard disk drives (HDDs) in recent years, are getting attention in the next generation memory market. An SSD is a data storage device that uses memory chips, such as flash memory, to store data instead of a rotating disk used in a typical hard disk drive.

SSDs are faster than mechanical moving hard disk drives, are more resistant to external shocks, and have lower power consumption. The SSD can exchange data with the host via the ATA interface. The ATA interface 212 includes a serial ATA (S-ATA) standard and a parallel ATA (P-ATA) standard.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

1 is a cross-sectional view showing a memory cell of a flash memory device.

2 is a graph showing the threshold voltage distribution of a flash memory cell.

Figures 3 and 4 show memory cells of the variable resistive memory device.

5 is a graph for explaining characteristics of the variable resistance material GST shown in FIGS. 3 and 4. FIG.

6 is a block diagram showing a semiconductor memory system according to the present invention.

7 is a flowchart showing a method of manufacturing a semiconductor memory system according to the present invention.

FIG. 8 is a flowchart illustrating a system code storing method of a semiconductor memory system according to the present invention.

Claims (9)

Storing the system code in a first non-volatile memory; Assembling the first nonvolatile memory and the second nonvolatile memory; And And replicating the system code stored in the first nonvolatile memory to the second nonvolatile memory, Wherein a temperature at which said first nonvolatile memory can hold data is higher than a temperature at which said second nonvolatile memory is capable of holding data, Wherein the system code is data for initialization of a semiconductor memory system. The method according to claim 1, Wherein the first nonvolatile memory is a NAND flash memory and the second nonvolatile memory is a variable resistance memory. The method according to claim 1, Further comprising: copying the system code stored in the first nonvolatile memory to the second nonvolatile memory, and then deleting the system code stored in the first nonvolatile memory. The method according to claim 1, The step of copying the system code stored in the first nonvolatile memory into the second nonvolatile memory is performed only when the system code is not stored in the second nonvolatile memory. The method according to claim 1, And updating the replication flag indicating that the system code stored in the first nonvolatile memory has been copied to the second nonvolatile memory. 6. The method of claim 5, Volatile memory, and when the replication flag indicates that the system code stored in the first nonvolatile memory has been copied to the second nonvolatile memory, the system code stored in the first nonvolatile memory is copied to the second nonvolatile memory Is omitted. delete Semiconductor memory system; And And a memory controller configured to control the semiconductor memory system, The semiconductor memory system is manufactured by the method according to claim 1. Semiconductor memory system; And And a memory controller configured to control the semiconductor memory system, The semiconductor memory system is manufactured by the method according to claim 1.

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