KR101538425B1 - Processor and instruction processing method in processor - Google Patents

Abstract

The present invention relates to an instruction cache that stores second instructions each including at least a portion of first instructions stored in an external memory and a plurality of microinstructions, A microcache storing third instructions corresponding to each of the plurality of microinstructions included in each second instruction; And a core for performing operations by reading the first and second instructions from the instruction cache, wherein the core performs operations by first instructions from the instruction cache under normal mode, , The core performs an operation by the third instructions corresponding to the plurality of microinstructions provided from the microcache.

Description

PROCESSOR AND INSTRUCTION PROCESSING METHOD IN PROCESSOR [0002]

The present invention relates to a processor and a method for processing instructions in a processor, and more particularly, to a processor capable of simultaneously processing a plurality of instructions in a core during a single cycle for instructions that are frequently executed or processed in the processor And to a method for processing instructions in a processor.

The background art of the present invention is disclosed in Korean Patent Publication No. 1996-0015584 (published on November 18, 1996).

A processor reads an instruction stored in an external memory such as a memory or a disk, performs a specific operation on the operand according to the operation encoded in the instruction, stores the result again, Hardware that executes the algorithm, and the like.

The application area of the processor is extensively encompassing the entire field of system semiconductors. The application areas of the processor include high performance media data processing for large amounts of multimedia data such as compression and decompression of video data, compression and decompression of audio data, audio data transformation and sound effects, modem for wired and wireless communication, voice codec algorithm, , A touchscreen, a controller for consumer electronics, a minimal-performance microcontroller platform such as motor control, a wireless sensor network or an electronics dust, To devices that can not.

The processor basically comprises a Core, a Translation Lookaside Buffer (TLB), and a Cache. The work to be performed by the processor is defined by a combination of a plurality of instructions. That is, when an instruction is stored in a memory and the instructions are sequentially input to the processor, the processor performs a specific operation every clock cycle. The translation lookaside buffer (TLB) translates virtual addresses into physical addresses for operating applications based on the operating system. The cache temporarily stores instructions stored in the external memory in the chip to increase the speed of the processor .

In general, a cache is a high-speed storage device that temporarily stores information between a processor having a relatively high processing speed and an external memory having a relatively low processing speed. Such a cache can speed up the processing speed of the computer by using the locality of reference when executing the shared program. That is, when a computer program is executed, it is observed that only one or two areas of the external memory are accessed intensively at a certain time when the address in the external memory accessed by the processor is observed. By using such a property, a high-speed cache is provided between the external memory and the processor, thereby storing a portion of the external memory frequently used therein, thereby shortening the time required for the processor to access the external memory.

In other words, a considerable time of 10 to 100 cycles is usually required for the core of the processor to read data from the external memory, which causes the core to stay in idle state for a long time . The cache is a unit that stores frequently used instructions in memory in a chip directly connected to the core, which shortens the time it takes for the core to access the external memory. The cache is used to temporarily store the instructions in the chip instead of the external large memory.

The cache has a significant impact on the performance of the processor. If the core does not have the above-mentioned instruction in the cache when it requests a specific instruction, the core must read the instruction from external memory. It should be operated as much as possible.

However, since power is consumed by the core each time it reads an instruction from the cache, the cache has a significant impact on the power consumption aspect of the processor. Conventionally, even for frequently processed instructions, power consumption is increased each time each instruction is read from the cache. In addition, since the core sequentially reads each instruction from the cache, There is a problem in that there is a limit of.

SUMMARY OF THE INVENTION Accordingly, it is an aspect of the present invention to provide a processor capable of increasing processing power and implementing power reduction by allowing multiple instructions to be processed simultaneously in the core during a single cycle for instructions that are frequently executed or processed in the processor And a method of processing instructions in a processor.

According to one aspect of the present invention, the present invention provides an instruction cache that stores second instructions each including at least a portion of first instructions stored in an external memory and a plurality of microinstructions; A microcache storing third instructions corresponding to each of the plurality of microinstructions included in each second instruction; And a core for performing operations by reading the first and second instructions from the instruction cache, wherein the core performs operations by first instructions from the instruction cache under normal mode, The core performs an operation by the third instructions corresponding to the plurality of microinstructions provided from the microcache.

In the present invention, when the core executes the instruction to change the processor status register among the first instructions, the processor preferably enters the micro instruction mode.

In the present invention, when entering the micro-instruction mode, the core provides the second instructions to the micro-cache, and the micro-cache transfers the provided second instructions to a plurality of micro-instructions included in the second instructions And outputs the third instructions to the core.

In the present invention, it is preferable that each of the plurality of micro-instructions indicates an address where the corresponding third instruction is stored in the micro-cache.

In the present invention, it is preferable that each of the second instructions includes four micro-instructions having an 8-bit width, and the third instruction corresponding to each of the micro-instructions has a 32-bit width.

In the present invention, it is preferable that the core includes an instruction write unit that stores the corresponding third instruction at an address corresponding to each of the plurality of micro instructions in the microcache.

In the present invention, it is preferable that the processor searches for instructions that are frequently executed regularly or irregularly, and updates the third instruction to be stored in the microcache based on the search result.

Further, according to another aspect of the present invention, the present invention provides a method comprising: receiving a second instruction from a instruction cache, the core comprising at least a part of first instructions or a plurality of micro instructions; The core providing second instructions to a microcache when the processor enters a microinstruction mode, the microcache storing third instructions corresponding to each of the plurality of microinstructions contained in each second instruction Doing; step; Outputting the third instructions corresponding to the plurality of microinstructions to the core; And a step in which the core performs an operation in accordance with the third instructions.

In the present invention, the step of outputting the third instructions by the microcache may include converting the second instructions into the third instructions corresponding to the plurality of microinstructions included in the second instructions And outputting to the core.

A processor and a method of processing instructions in a processor in accordance with the present invention can improve the processing power of the processor and implement power reduction by allowing multiple instructions to be processed simultaneously in the core during a single cycle for instructions that are frequently executed or processed in the processor There is an effect to be able to.

1 illustrates a configuration of a processor according to an embodiment of the present invention.
2 is a schematic diagram for explaining a method of processing a command between a core and a microcache in a processor according to the present embodiment.
3 shows the instructions stored in the instruction cache of the processor according to the present embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

FIG. 1 is a diagram illustrating a configuration of a processor according to an embodiment of the present invention. FIG. 2 is a simplified diagram for explaining a method of processing a command between a core and a microcache in a processor according to the present embodiment. FIG. 4 illustrates instructions stored in an instruction cache of a processor according to an embodiment. FIG. The present invention will be described with reference to FIGS. 1 to 3. FIG.

As shown in Figures 1 to 3, the processor according to the present embodiment includes at least a portion of first instructions 10 stored in an external memory (not shown), and a second instruction An instruction cache 130 for storing the data 15; A microcache (140) for storing third instructions (inst0 to inst3) corresponding to each of the plurality of microinstructions included in each second instruction (15); And a core 110 for reading the first and second instructions 10 and 15 from the instruction cache 130 to perform an operation.

Core 110 performs operations by first instructions 10 from instruction cache 130 under normal mode and if core 110 enters a microinstruction mode the core 110 provides from microcache 140 And the third instructions inst0 to inst3 corresponding to the plurality of microinstructions.

When the processor enters the micro-instruction mode, the core 110 provides the second instructions 15 to the micro-cache 140, and the micro-cache 140 provides the second instructions 15, (Inst0 to inst3) corresponding to a plurality of microinstructions included in the second instructions 15, and outputs the third instructions inst1 to inst3 to the core 110. [

In particular, each of the second instructions 15 may include four of the microinstructions having an 8-bit width, and the third instructions inst0 to inst3 corresponding to each of the microinstructions may be 32 Bit width.

The core 110 may include an instruction write unit 112 for storing the corresponding third instructions inst0 to inst3 at addresses corresponding to each of the plurality of micro instructions in the microcache 140. [

The operation and operation of the present embodiment thus configured will be described in detail with reference to Figs. 1 to 3. Fig.

1, the core 110 is a unit that reads various instructions and performs operations of the processor. The translation index buffer (TLB) 120 is a unit for converting a virtual address into a physical address. The instruction cache 130 is a unit for storing a part of program codes stored in an external memory (not shown), and is a unit for reading various instructions at high speed.

The microcache 140 proposed in the present embodiment is a unit connected to the core 110. The microcache 140 is a unit of a normal instruction stored in correspondence with microinstructions provided from the core 110 under the microinstruction mode, To the core (110). The core 110 writes contents to be stored in the microcache 140 through a micro-instruction write bus. The core 110 then reads instructions via the micro-instruction read bus when the current processor operating mode is the micro-instruction mode.

As shown in FIG. 3, the instruction cache 130 includes at least some instructions 10 of the first instructions stored in an external memory (not shown) and a second Instructions 15 are stored. Here, the first instructions 10 mean regular instructions that are computed or processed by the processor. The microinstructions included in the respective second instructions 15 are indexes for reading the third instructions inst0 to inst3 which are not regular instructions but are corresponding instructions stored in the microcache 140 under the microinstruction mode It is a command that plays a role.

The instructions stored in the instruction cache 130 generally have a bit width of 32 bits to specify a type of operation, an operand, and a flag setting method.

Under normal mode, the core 110 reads the first instructions 10, which are regular instructions stored in the instruction cache 130, and performs specific operations accordingly. That is, under the normal mode, the core 110 performs operations based on the same operation mechanism as that of a normal processor that sequentially reads the first instructions 10, which are regular instructions stored in the instruction cache 130, .

However, in the present embodiment, when the core 110 reads the instruction psr 11, which is an instruction for changing the processor status register, from the instruction cache 130 and executes it, the operation mode of the processor becomes " Quot; micro command mode ". The microcommand mode refers to a mode in which the microcomputer included in the second instruction 15 of the present embodiment is used to read the third instructions inst0 to inst3 corresponding thereto and perform the operation.

When the operating mode of the processor enters the micro-instruction mode, the core 110 recognizes 32 bits of each second instruction 15 input from the instruction cache 130 as micro-id, and each second instruction 15 ) Contains four 8-bit microcommands. These 8-bit microcommands are replaced with 32-bit third instructions inst0 to inst3 by the microcache 140 and output to the core 110. That is, the core 110 reads the second instructions 15, which are 32-bit data, from the instruction cache 130 and provides them to the microcache 140. The microcache 140 is connected to each 8-bit microinstruction And outputs the corresponding 32-bit third instructions inst0 to inst3 to the core 110. [ That is, since each 8-bit microinstruction included in the second instruction 15 is replaced with 32-bit third instruction inst0 to inst3, four 32-bit instructions are processed at once.

The process of processing microinstructions by the core 110 and the microcache 140 will be described in more detail with reference to FIG. In the present embodiment, the first instructions 10 and the second instructions 15 read from the instruction cache 130 have a bit width of 32 bits. When the operating mode of the processor enters the micro-instruction mode, the 32-bit second instruction (mid 0, 1, 2, 7) is read from the instruction cache 130 to generate four micro- And is input to the microcache 140. [

At this time, each 8-bit microinstruction becomes the address of the microinstruction memory 141 in the microcache 140. This 8-bit microinstruction may specify 256 different elements in the microinstruction memory 141. That is, an 8-bit microinstruction can be used as an index of a memory element of the microcommand memory 141. [

The micro instruction memory 141 of the microcache 140 stores 32-bit regular third instructions inst0 to inst3 corresponding to the 8-bit micro instructions. With the 8-bit microinstructions as addresses, the microinstruction memory 141 outputs the 32-bit third instructions inst0 to inst3 for each 8-bit microinstruction. The outputted four 32-bit third instructions inst0 to inst3 are input to a fetch unit 111 of the core 110, that is, a unit for reading an instruction, as an instruction of the processor. The core 110 reads the input third instructions inst0 to inst3 and performs an operation according to the instructions.

When the third instruction corresponding to the specific micro instruction 15a for mode return shown in FIG. 3 is executed by the core 110 after executing the third instructions substituted in the micro instruction mode described above, Lt; RTI ID = 0.0 > microcommand < / RTI > When the mode is switched to the normal mode, the core 110 performs the operation according to the normal first instructions 10 stored in the instruction cache 130 again.

Meanwhile, before the processor is switched to the micro-instruction mode, the micro-instruction memory 141 of the micro-cache 140 must receive a third instruction corresponding to each micro-instruction as described above. To this end, the core 110 has a command write unit 112 as shown in FIG. The instruction write unit 112 is a unit for writing third instructions to a position or an address corresponding to each micro instruction, and includes an index (Index) designating a position where the third instruction of each 32 bits is to be stored, And writes the 32-bit third instruction inst to the microcommand memory 141 via the microinstruction update bus.

The processor may search for instructions that are frequently performed on a regular or irregular basis and may update third instructions to be stored in the microcache 140 based on the search results. The input or update of the third instruction may be automatically performed periodically, irregularly, or according to a user's request.

In addition, although the case where the normal instruction word is 32 bits and the micro instruction word is 8 bits has been described above, the bit widths of the regular instruction word and the micro instruction word are not limited thereto and various bit width instructions may be applied according to the environment of the system or the processor have.

As described above, in the processor and the instruction processing method in the processor, a plurality of instructions can be simultaneously processed in the core during a single cycle using micro instructions for instructions that are frequently executed or processed in the processor. Thus, the processing capability of the processor can be improved and the power consumption can be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (13)

A processor comprising:
An instruction cache that stores second instructions each including at least a portion of first instructions stored in an external memory and a plurality of microinstructions;
A microcache storing third instructions corresponding to each of the plurality of microinstructions included in each second instruction; And
And a core for reading the first and second instructions from the instruction cache to perform an operation,
The core performing an operation by first instructions from the instruction cache under normal mode,
Wherein when the processor enters the micro-instruction mode, the core performs an operation by the third instructions corresponding to the plurality of micro-instructions provided from the micro-cache.
The method according to claim 1,
Wherein when the core executes an instruction to change a processor status register among the first instructions, the processor enters the micro-instruction mode.
The method according to claim 1,
Wherein the core provides the second instructions to the microcache when the microcontroller enters the microcommand mode, and wherein the microcache stores the second instructions provided to the microcache in response to a plurality of microinstructions included in the second instructions, 3 < / RTI > instructions and outputs the converted instructions to the core.
The method of claim 3,
Wherein each of the plurality of micro-instructions indicates an address where the corresponding third instruction is stored in the micro-cache.
The method of claim 3,
Wherein each of said second instructions comprises four said microinstructions having an 8 bitwidth and said third instruction corresponding to each of said microinstructions has a 32 bit width.
The method of claim 3,
Wherein the core includes an instruction write unit that stores the corresponding third instruction at an address corresponding to each of the plurality of micro instructions in the microcache.
The method according to claim 6,
Wherein the processor is operative to search for instructions that are frequently performed on a regular or irregular basis and to update the third instruction to be stored in the microcache based on the searched result.
A method of processing instructions in a processor,
The core receiving second instructions from the instruction cache, each instruction comprising at least a portion of the first instructions or a plurality of microinstructions;
The core providing second instructions to a microcache when the processor enters a microinstruction mode, the microcache storing third instructions corresponding to each of the plurality of microinstructions contained in each second instruction Doing; step;
Outputting the third instructions corresponding to the plurality of microinstructions to the core; And
And the core performing an operation in accordance with the third instructions.
9. The method of claim 8,
Wherein when the core executes an instruction to change a processor status register among the first instructions, the processor enters the micro instruction mode.
9. The method of claim 8,
Wherein the outputting of the third instructions by the microcache comprises:
And converting the second instructions into the third instructions corresponding to the plurality of microinstructions included in the second instructions and outputting the third instructions to the core. Way.
11. The method of claim 10,
Wherein each of the plurality of micro-instructions indicates an address in which the corresponding third instruction is stored in the micro-cache.
11. The method of claim 10,
Wherein each of said second instructions comprises four said microinstructions having an 8 bitwidth and said third instruction corresponding to each of said microinstructions has a 32 bit width. Way.
11. The method of claim 10,
Wherein the processor is operative to search for instructions that are frequently performed regularly or irregularly and to update the third instruction to be stored in the microcache based on the result of the search.

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