KR101535332B1 - Current-Feedback Instrumentation Amplifier - Google Patents

Abstract

A current-feedback measurement amplifier is disclosed. The ripple component of the output signal due to the offset voltage of the amplifier is sampled through the switching operation in the ripple removal. The voltage formed through the transconducting and integrating operations on the sampled signal is converted into a compensating current. The compensation current is input to the amplifier to offset the effect of the offset voltage. Therefore, the use of a large capacity capacitor required for sensing the output voltage is avoided, and the common mode gain can be rapidly reduced.

Description

Current-Feedback Instrumentation Amplifier [0002]

The present invention relates to a current feedback measurement amplifier, and more particularly, to a current feedback measurement amplifier for removing ripple generated at an output terminal.

The current-feedback measurement amplifier is used for acquiring a bio-signal having a low frequency band and a small signal. This tends to be used mainly at the input of the analog-front end of a sensor that uses bio-signals. To amplify a small signal in a low frequency band, a current feedback measuring amplifier having an offset canceling function is required. In addition, in order to insert the bio-signal sensor into the body, it is necessary to implement it with a small area.

A chopper is typically used to remove the offset generated at the input stage in the current feedback measurement amplifier. However, when a chopper is used, ripple is generated in the output voltage. A ripple reduction loop is used to remove the generated ripple.

The ripple reduction loop has a configuration for integrating a ripple sensing capacitor at the output and sensed ripple and feeding it back to the input stage. Particularly, there arises a problem that the area of the current-feedback measuring amplifier becomes large due to the capacitor used for detecting the ripple at the output terminal.

Further, when a capacitor having a small capacity is designed to prevent an increase in the area of the current-feedback measurement amplifier, it is difficult to remove the ripple at the output stage. This means that the elimination of the offset voltage in the current-feedback measurement amplifier is not perfect. If the removal of the offset voltage is not perfect, then a common mode gain is generated. This causes a phenomenon in which an input signal input in the form of a differential signal can not be amplified accurately. Therefore, it is essential to remove the ripple voltage at the output stage in order to make the common mode rejection ratio of the current feedback measurement amplifier have an ideal infinite value.

Therefore, a current-feedback measuring amplifier capable of sensing and amplifying a low-frequency band and a low-level signal such as a living body signal and capable of realizing a small area will be required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a current feedback measurement amplifier having a small area and a high common mode rejection ratio.

According to an aspect of the present invention, there is provided a chopper comprising: a first chopper for receiving an input signal and chopping the input signal according to a chopping clock; An amplifier for receiving the output of the first chopper and amplifying the output; A second chopper for performing a chopping operation corresponding to the chopping clock with respect to an output of the amplifier and forming an output signal; And a ripple rejection unit for receiving the output signal to form a compensation current corresponding to the variation period of the output signal and supplying the compensation current to the amplifier to reduce the common mode gain .

The above object of the present invention is also achieved by a method for amplifying an input signal, comprising: a forward path for receiving an input signal and amplifying the input signal using an amplifier to form an output signal; And a ripple rejection unit for receiving the output signal to form a compensation current corresponding to a variation period of the output signal and supplying the compensation current to the amplifier to reduce the common mode gain, .

According to the present invention described above, the output signal is sampled and held through a sampling operation in the ripple removal. In addition, a compensation current corresponding to the ripple portion of the output signal is formed through the integration and transconducting operations. Accordingly, the offset component of the amplifier performing the amplification operation can be effectively removed, and the use of the large capacity capacitor used for sensing or removing the ripple component generated at the output stage is avoided. This minimizes the area of the chip.

1 is a block diagram illustrating a current feedback measurement amplifier according to a preferred embodiment of the present invention.
Fig. 2 is a circuit diagram showing the first chopper or the second chopper shown in Fig. 1 according to a preferred embodiment of the present invention.
3 is a circuit diagram showing the sample / holding circuit of the ripple removal device of FIG. 1 according to a preferred embodiment of the present invention.
4 is a timing chart for explaining the operation of the sample / holding circuit of FIG.
5 is a circuit diagram illustrating the first transconductance stage of FIG. 1 according to a preferred embodiment of the present invention.
6 is a timing chart for explaining the operation of the first transconductance stage of FIG.
FIG. 7 is a circuit diagram showing the integrator of FIG. 1 according to a preferred embodiment of the present invention.
Fig. 8 is a circuit diagram showing an example of the second transconductance stage of Fig. 1 according to a preferred embodiment of the present invention.
FIG. 9 is a timing chart for explaining the operation of the integrator of FIG. 7 and the second transconductance stage of FIG. 8;
10 is a circuit diagram showing an example of the amplifier of FIG. 1 according to a preferred embodiment of the present invention.
11 is a timing chart for explaining the operation of the current feedback measurement amplifier of FIG. 1 according to a preferred embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

1 is a block diagram illustrating a current feedback measurement amplifier according to a preferred embodiment of the present invention.

Referring to FIG. 1, the current-feedback measurement amplifier has a forward path 100 and a ripple removal unit 200. The forward path 100 receives the input signal Vin and amplifies it to form the output signal Vout. The ripple removal unit 200 samples and holds the output signal Vout, converts it into a current corresponding to the sampled value, integrates it, and forms a compensation current Icomp to the amplifier constituting the forward path 100 . The compensating current Icomp supplied compensates the common mode gain according to the offset voltage of the amplifier included in the forward path 100. [

The forward path has a first chopper 110, an amplifier 120, a second chopper 130 and a spark filter 140.

The first chopper 110 forms a square wave corresponding to the chopping clock CLKch supplied to the input signal Vin through a chopping operation on the input signal Vin. For example, when the input signal Vin has a constant level as the differential signal, the output of the first chopper 110 forms a square wave in which the high level and the low level are repeated. The formed waveform is input to the amplifier 120. If the input signal Vin is input in the in-phase mode instead of the differential signal, the output of the first chopper 110 may be constant in size or may not vary in size.

The amplifier 120 receives the output of the first chopper 110 and amplifies it with a predetermined gain. The output of the amplifier 120 is input to the second chopper 130. The compensation current Icomp, which is the output of the ripple removal unit 200, is applied to the amplifier. The offset voltage of the amplifier 200 due to the supply of the compensation current Icomp can be canceled to some extent. However, if the compensation current Icomp is insufficient to offset the offset voltage of the amplifier, the amplifier 200 outputs a differential signal with a certain gain.

The second chopper 130 performs a chopping operation on the output of the amplifier 120. The differential output signal of the amplifier 120 is transformed into a predetermined waveform through the chopping operation in the second chopper 130. [ Also, the second chopper 130 may remove a noise component included in the output of the amplifier 120 through a chopping operation corresponding to the applied chopping clock CLKch. The output of the second chopper 130 is input to the spark filter 130.

The spark filter 140 receives the output of the second chopper 130 and removes the spark component contained in the output of the second chopper 130. The output of the spark filter 140 is used as the output signal Vout of the current feedback measurement amplifier.

The ripple removal unit 200 receives the output signal Vout of the current feedback measurement amplifier and forms a corresponding compensation current Icomp. The compensation current Icomp is applied to the amplifier 120 to remove an offset of the amplifier 120.

To this end, the ripple removal circuit 200 has a sample / holding circuit 210, a first transconductance stage 220, an integrator 230 and a second transconductance stage 240.

Fig. 2 is a circuit diagram showing the first chopper or the second chopper shown in Fig. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 2, the first chopper 110 or the second chopper 130 of the present embodiment has four switches SW1 to SW4. The first switch SW1 and the fourth switch SW4 perform ON / OFF operations in accordance with the chopping clock CLKch. For example, when the chopping clock CLKch is at the high level, the first switch SW1 and the fourth switch SW4 are turned on. Further, the second switch SW2 and the third switch SW3 perform a turn-on operation when the inverted chopping clock / CLKch is at a high level. The chopping clock CLKch and the inverted chopping clock / CLKch have mutually complementary relations.

Accordingly, in the section where the input signal Vin is applied and the chopping clock CLKch is at the high level, the chopper outputs the input signal without changing the phase. In addition, when the chopping clock CLKch is low level, the chopper outputs a signal whose phase of the input signal is inverted.

Referring to FIG. 1, the operation of the first chopper 110, the amplifier 120, and the second chopper 130 will be described. It is assumed that the input signal Vin is applied with a constant voltage difference or in a common mode. In the differential mode, when the input signal Vin has a constant value, a rectangular waveform is input to the amplifier 120 according to the operation of the chopping clock CLKch and the operation of the first chopper 110 according to the reception of the inverted chopping clock / CLKch . Also, when the input of the in-phase mode is applied, the first chopper 110 can input the in-phase mode signal to the amplifier 120. [

The amplifier 120 receives the output signal of the first chopper 110 and receives the compensation current Icomp supplied from the ripple removal unit 200. [ Assuming that the compensation current Icomp is not variable and has a constant level or that the compensation current Icomp does not occur, the signal through the amplifier 120 and the second chopper 130 forms an output signal Vout with ripple do. This is due to the offset voltage formed at one of the inputs of the amplifier 120.

3 is a circuit diagram showing the sample / holding circuit of the ripple removal device of FIG. 1 according to a preferred embodiment of the present invention.

4 is a timing chart for explaining the operation of the sample / holding circuit of FIG.

Referring to Figs. 3 and 4, the sample / holding circuit has a positive peak detecting portion 211 and a negative peak detecting portion 212. Fig.

The positive peak detector 211 is composed of switches for performing an on / off operation at a positive peak clock CLKph, and the negative peak detector 212 comprises switches for performing an on / off operation at a negative peak clock CLKpl .

First, the positive peak detector 211 samples the signal in the rising period of the output signal Vout in the interval in which the positive peak clock CLKph is activated. Thereafter, the value of the sampled output signal Vout is held in a period in which the positive peak clock CLKph is at a low level. Therefore, the positive peak signal Vph samples and holds the output signal Vout in the rising section of the output signal Vout.

In addition, during a period in which the negative peak clock CLKpl is activated, the negative peak detector 212 samples and holds the output signal Vout in the falling period of the output signal Vout. Therefore, the negative peak signal Vpl samples the falling pattern of the output signal Vout in the section where the negative peak clock CLKpl is at the high level, and holds it in the remaining low-level section.

It is assumed in FIG. 4 that the ripple component of the output signal Vout has a constant triangular waveform. However, the component of the output signal Vout in the present invention has a tendency to decrease with time. Therefore, the peak value of the positive peak signal Vph and the peak value of the negative peak signal Vpl have a tendency to decrease with time.

5 is a circuit diagram illustrating the first transconductance stage of FIG. 1 according to a preferred embodiment of the present invention.

6 is a timing chart for explaining the operation of the first transconductance stage of FIG.

5 and 6, the first transconductance stage has a bias portion 221, a positive transconductance portion 222 and a negative transconductance portion 223.

The bias section 221 has a first bias transistor Mb1 and a second bias transistor Mb2. The first bias transistor Mb1 is connected between the positive power supply voltage VDD and the first node N1, and the second bias transistor Mb2 is connected between the ground and the second node N2. The bias current flowing through the first bias transistor Mb1 is determined by the first bias Vb1 and the bias current flowing through the second bias transistor Mb2 is determined by the second bias Vb2. It is also preferable that the bias currents flowing through the respective bias transistors are equal to each other.

Further, a positive transconductance section 222 is connected between the first node N1 and the second node N2, and has four transistors M1 to M4. The gate terminals of the first transistor M1 and the second transistor M2 are connected in common, and receive the positive peak signal Vph +. Further, the gate terminals of the third transistor M3 and the fourth transistor M4 are connected in common, and receive the positive peak signal Vph-. In FIG. 5, since the positive peak signal Vph is input in the form of a differential signal, the signals input to the respective input terminals are denoted by Vph + and Vph-. This applies equally to the negative peak signal Vpl. Therefore, the negative peak signal Vpl becomes a difference value between Vpl + and Vpl-.

The negative transconductance section 223 is connected in parallel with the positive transconductance section 222 and connected between the first node N1 and the second node N2. Also, it has four transistors M5 to M8, and the gate terminals of the fifth transistor M5 and the sixth transistor M6 are connected in common, and receive the negative peak signal Vpl +. In addition, the gate terminals of the seventh transistor M7 and the eighth transistor M8 are connected in common, and receive the negative peak signal Vpl-.

The current flowing through the first transistor M1 decreases and the current flowing through the second transistor M2 increases due to the rise of the voltage applied to the gate in the first section T1 in which the positive peak signal Vph rises. Therefore, the current flowing from the negative output node IGM1- to the second transistor M2 has an increasing aspect. Further, the current flowing through the third transistor M3 increases due to the ascending positive peak signal Vph, and the current flowing through the fourth transistor M4 decreases. Thus, the current flowing from the third transistor M3 to the positive output node IGM1 + increases.

Therefore, the transconductance output current IGM1 increases in the period in which the positive peak signal Vph increases.

 Further, in the second section T2 where the positive peak signal Vph and the negative peak signal Vpl are in the holding state, fluctuations of the input signals applied to the positive transconductance section 222 and the negative transconductance section 223 are not generated Do not. Therefore, the current IGM1 outputted from the first transconductance stage maintains a constant state.

Subsequently, the positive peak signal Vph is held at a constant level in the third section T3 in which the negative peak signal Vpl is decreased.

In the third section T3, the negative peak signal Vpl is reduced. Therefore, the gate voltages of the fifth transistor M5 and the sixth transistor M6 tend to decrease, and the gate voltages of the seventh transistor M7 and the eighth transistor M8 are relatively increased. This means that the current flowing through the fifth transistor M5 increases and the current flowing through the sixth transistor M6 decreases. Therefore, the current flowing from the fifth transistor M5 to the positive output terminal IGM1 + increases. Further, the current flowing from the negative output terminal IGM1- to the sixth transistor M6 also increases. This lasts until the time when the negative peak signal Vpl is reduced.

The first transconductance stage outputs a constant level in the fourth section T4 where the positive peak signal Vph and the negative peak signal Vpl maintain a constant level. However, when the fluctuation width of the output signal Vout gradually decreases with time, the level of the output current IGM1 of the first transconductance stage also tends to decrease gradually. This is due to the reduction of the fluctuation width of the positive peak signal Vph and the negative peak signal Vpl.

FIG. 7 is a circuit diagram showing the integrator of FIG. 1 according to a preferred embodiment of the present invention.

Fig. 8 is a circuit diagram showing an example of the second transconductance stage of Fig. 1 according to a preferred embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the integrator of FIG. 7 and the second transconductance stage of FIG. 8;

Referring to Figures 7, 8 and 9, the integrator has a conventional configuration. Therefore, it has a structure composed of an amplifier and a capacitor. The output current IGM1 of the first transconductance stage is applied to the integrator. The integrator performs the switching operation in accordance with the integral clock CLKint, and thus the integral operation is performed.

The integral clock CLKint is deactivated in the rising period of the output current IGM1 of the first transconductance stage. Therefore, the integration operation is not performed in the period in which the first transconductance stage output current IGM1 rises, and the integration operation is performed in the section in which the output current IGM1 forms a constant level. Therefore, in a situation where the fluctuation width of the output current IGM1 of the first transconductance stage gradually decreases, the output Vint of the integrator tends to converge to a constant level.

The second transconductance stage converts the output voltage Vint of the integrator, which is input in the form of a differential signal, into a current. However, any configuration can be used as long as it can form an output current proportional to the magnitude of the input voltage signal.

When the level of the output voltage Vint of the integrator input in differential form in the second transconductance stage increases, the positive integral signal Vint + increases and the negative integral signal Vint- decreases.

Therefore, the current flowing through the transistor Q1 decreases and the current flowing through the transistor Q2 increases. This is copied to the transistors Q3 and Q4 having the configuration of the current mirror and copied to the transistors Q5 and Q6 having the configuration of the other current mirror. Thus, the current flowing through transistor Q7 decreases and the current through transistor Q8 increases.

Further, the bias current has a constant value due to the bias voltage Vbiasp1. Accordingly, the output current Icomp + flows out to the output terminal in an increased manner due to the decrease in the current flowing through the transistor Q7, and the output current Icomp- flows in the increased direction due to the increase in the current flowing through the transistor Q8. 8, Vcasp, Vcasn and Vbiasp2 are interpreted as bias voltages of the respective transistors.

10 is a circuit diagram showing an example of the amplifier of FIG. 1 according to a preferred embodiment of the present invention.

The amplifier of this embodiment will be applicable to any device capable of performing a predetermined amplification operation on the input voltage with a constant offset voltage.

Referring to FIG. 10, the amplifier has a compensation current supply part 121 and an amplification part 122.

The compensation current supply 122 may be supplied in the form of a current mirror. Further, the compensation current supply unit 122 receives the compensation current Icomp, which is the output of the second transconductance stage.

The amplification unit 122 has a first amplification unit 123 and a second amplification unit 124. Each amplifier section may have a cascode configuration in which a common source and a source follower are cascaded. For example, the positive input signal Vinp is applied to the gate terminal of the transistor Q12 in the inverted phase by the common source amplification operation of the transistor Q11. Further, the transistor Q12 inverts the input through the source follower operation and outputs the amplified signal Voutn.

If the two differential inputs Vinp and Vinn applied to the input terminal have the same level, it is ideal that the voltage difference at the output terminal does not appear. However, when the offset voltage Voff is present in the transistor Q11 constituting the input terminal, the voltage difference at the output terminal appears. For example, when the positive input signal Vinp and the negative input signal Vinn are the same, the voltage at the source terminal of the transistor Q11 rises due to the offset voltage Voff generated at the transistor Q11, the voltage at the source terminal of the transistor Q12 falls, The offset current Ioff flows through R1. If the compensation current supply part 121 is not provided, the offset current Ioff flows through the resistor R1 and the transistor Q13, the resistor R2 and the transistor Q14, and the output terminal outputs a constant voltage difference.

However, when the compensation current Icomp is applied in the compensation current supply section 121, the compensation current Icomp forms an offset current. Therefore, the offset current does not flow through the resistor R1 and the transistor Q13, the resistor R2 and the transistor Q14, and the amplifier generates a 0 V level differential signal when the same level of input is applied.

11 is a timing chart for explaining the operation of the current feedback measurement amplifier of FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIGS. 1 and 11, the output signal Vout through the chopping spark filter 140 has an approximately triangular wave pattern due to the offset voltage of the amplifier 120. Particularly, the chopping spark filter 140 can remove the spark component contained in the triangular wave, but can not remove the ripple component of the voltage ripple in the triangular waveform due to the offset formed at the input terminal of the amplifier 120. Thus, the output signal Vout forms a triangular waveform that pulsates due to the input offset voltage of the amplifier 120, and repeats the rising period and the falling period in synchronization with the chopping clock CLKch. This is due to the inherent operation of the choppers 110 and 130.

The output signal Vout that has passed through the chopping spark filter 140 is input to the ripple removal unit 200. The ripple removal unit 200 forms a compensation current Icomp for removing the ripple component of the triangular waveform shown in the output signal Vout. By the compensation current Icomp, the final output converges to a state where the differential output is zero.

First, the sample / holding circuit 210 of the ripple removal unit 200 samples and holds the output signal Vout in the rising period in the active period of the positive peak clock CLKch. In addition, in the active period of the negative peak clock CLKpl, the output signal Vout in the falling state is sampled and held. The difference between the positive peak signal Vph and the negative peak signal Vpl formed in the sample / holding circuit 210 becomes the difference value of the ripple component of the output signal Vout.

Further, the first transconductance stage 220 receives the input positive peak signal Vph and the negative peak signal Vpl and converts it into a current. During the conversion into the current path, the current varies in the variation period of the positive peak signal Vph. Thus, the first transconductance stage 220 forms an output current IGM1 corresponding to the variation of the output signal of the sample / hold circuit 210. [

The output current IGM1 of the first transconductance stage 220 is input to the integrator 230, and the integrator 230 performs the integration operation in a period in which the integral clock CLKint is activated. The integral clock CLKint is activated in a period in which the output current IGM1 of the first transconductance stage 220 does not fluctuate or in a period in which the difference in the output voltage Vout is held. The integration signal Vint formed in the integrator 230 is input to the second transconductance stage 240. [

The second transconductance stage 240 receives the integration signal to form the compensation current Icomp. The compensation current Icomp is supplied to the amplifier 120 to cancel the common mode gain according to the offset component. This dramatically reduces common-mode gain and avoids the use of large capacitors for sensing the output stage.

According to the present invention, the current feedback measurement amplifier can effectively remove the offset component of the amplifier performing the amplification operation, and the use of the large capacity capacitor used for sensing or removing the ripple component generated at the output terminal is avoided. This minimizes the area of the chip.

100: forward path 110: first chopper
120: amplifier 130: second chopper
140: chopping spark filter 200: ripple removal
210: sample / holding circuit 220: first transconductance stage
230: integrator 240: second transconductance stage

Claims (12)

A first chopper for receiving an input signal and chopping the input signal in accordance with a chopping clock;
An amplifier for receiving the output of the first chopper and amplifying the output;
A second chopper for performing a chopping operation corresponding to the chopping clock with respect to an output of the amplifier and forming an output signal; And
And a ripple removal unit for performing a sampling and holding operation on the output signal and for converting the current into a current corresponding to the sampled value, forming an integration operation and a compensation current, and supplying the compensation current to the amplifier,
Wherein the ripple-
A sample / hold circuit for sampling and holding said output signal;
A first transconductance stage for receiving an output of the sample / holding circuit and for converting a variation of the output of the sample / holding circuit into a current;
An integrator for integrating an output current of the first transconductance stage to form an integration signal; And
And a second transconductance stage for receiving the integrated signal and forming the compensating current for canceling the offset voltage of the amplifier. delete The semiconductor memory device according to claim 1, wherein the sample /
A positive peak detector which is activated in the rising period of the output signal to perform a sampling operation and output a positive peak signal; And
And a negative peak detector which is activated in a falling period of the output signal to perform a sampling operation and output a negative peak signal. 4. The semiconductor device according to claim 3, wherein the first transconductance stage comprises:
Increasing the output current in a period in which the positive peak signal fluctuates, receiving the negative peak signal, and increasing the output current in the period in which the negative peak signal fluctuates Features a current feedback instrumentation amplifier. 4. The semiconductor device according to claim 3, wherein the first transconductance stage comprises:
A positive transconductance section that receives the positive peak signal and increases the output current in a period in which the positive peak signal rises; And
And a negative transconductance section connected in parallel with the positive transconductance section, the negative transconductance section receiving the negative peak signal and increasing the output current in a section where the negative peak signal decreases, amplifier. 2. The current feedback metrology amplifier of claim 1, wherein the second transconductance stage forms the compensation current proportional to the integrated signal. 7. The method of claim 6, wherein the compensation current of the second transconductance stage comprises:
Wherein the offset voltage is increased by the offset voltage of the amplifier until the offset current is equal to the offset current generated by the amplifier. The apparatus according to claim 1, wherein the current-
Further comprising a chopping spark filter connected to the second chopper for removing a spark component included in an output signal of the second chopper. A forward path that receives an input signal and amplifies the input signal using an amplifier to form an output signal; And
And a ripple removal unit for performing a sampling and holding operation on the output signal and for converting the current into a current corresponding to the sampled value, forming an integration operation and a compensation current, and supplying the compensation current to the amplifier,
Wherein the ripple-
A sample / hold circuit for sampling and holding said output signal;
A first transconductance stage for receiving an output of the sample / holding circuit and for converting a variation of the output of the sample / holding circuit into a current;
An integrator for integrating an output current of the first transconductance stage to form an integration signal; And
And a second transconductance stage for receiving the integrated signal and forming the compensating current for canceling the offset voltage of the amplifier. delete 10. The semiconductor memory device according to claim 9, wherein the sample /
A positive peak detector which is activated in the rising period of the output signal to perform a sampling operation and output a positive peak signal; And
And a negative peak detector which is activated in a falling period of the output signal to perform a sampling operation and output a negative peak signal. 10. The method of claim 9, wherein the compensation current of the second transconductance stage comprises:
Wherein the offset voltage is increased by the offset voltage of the amplifier until the offset current is equal to the offset current generated by the amplifier.

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