KR101532840B1 - Method and apparatus for performing data program using coarse writing operation and fine writing operation - Google Patents

Abstract

A memory array comprising a plurality of multi-level cells, each of the plurality of multi-level cells storing a plurality of bits and corresponding to a plurality of pages, the data programming method comprising: receiving a write command; Performing coarse writing to change the state of each of the plurality of multilevel cells for the plurality of pages at the same time in response to the write command; And performing a fine write to adjust the state of each of the plurality of multi-level cells simultaneously changed for the plurality of pages.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method and apparatus for performing a data program using coarse writing and fine writing,

The following embodiments are directed to a method and apparatus for performing a data program using coarse write and fine write in a storage system comprising a controller and at least one memory device.

The write operation in flash memory is executed page by page. That is, a single write operation is required to program one page.

In addition, a multi-level cell is used to increase the degree of integration of the flash memory and to improve the capacity of the storage device. The n-bit multi-level cell stores n-bit data, and the n-bit data is included in n pages. Thus, since programming operations for n pages are required to program n-bit data for one n-bit multilevel cell, the number of write operations required is n.

Also, the state of the n-bit multi-level cell changes for each write operation. For example, three-bit write operations are required for all three-bit data to be programmed in a three-bit multi-level cell, which means that the state of the multi-level cell changes three times. In addition, each time one write operation is executed, the number of candidates determined as the state of the multi-level cell is increased by 2, and in order to perform the next write operation, the state of the multi-level cell determined by the previous write operation must be read .

However, errors may occur, such as in the process of reading the state of a multilevel cell, which may cause unthinkable problems as the write operations are repeated. Thus, repeating the write operations as many as the number of pages does not always produce good results.

By performing a write operation on a multi-level cell, the coarse write operation and the fine write operation are performed to perform a write operation on a multi-level cell without repeating write operations corresponding to the number of pages. This write operation does not need to read the state of the multilevel cell determined by the previous write operation to perform the next write operation, thereby preventing errors due to the read operation. It also reduces interference by neighboring cells and improves the reliability problem that occurs as the write operations are repeated.

A memory array comprising a plurality of multi-level cells, each of the plurality of multi-level cells storing a plurality of bits and corresponding to a plurality of pages, the data programming method comprising: receiving a write command; Performing coarse writing to change the state of each of the plurality of multilevel cells for the plurality of pages at the same time in response to the write command; And performing a fine write to adjust the state of each of the plurality of multi-level cells simultaneously changed for the plurality of pages.

When each of the plurality of multi-level cells is an n-bit multi-level cell,

The step of performing coarse writing is a step of changing the state of each of the plurality of multi-level cells for n pages at the same time.

The step of performing coarse writing further comprises performing the coarse write after the data corresponding to the n pages is stored in the page register.

Wherein the data stored in the page register is maintained until the step of performing the fine writing is completed and the step of performing coarse writing is performed using coarse data, Write is executed.

When each of the plurality of multi-level cells is an n-bit multi-level cell, receiving the write command includes receiving a write command for n pages once to program data on n pages.

If each of the plurality of multilevel cells is an n-bit multilevel cell, receiving the write command includes receiving n write commands for one page to program data on n pages.

The step of performing the fine writing is a step of executing the fine writing after the coarse writing is executed for at least one other writing command different from the writing command.

Wherein performing the fine writing comprises: after the coarse writing for the n pages is performed and after the coarse writing for the other n pages is further performed, the n < RTI ID = 0.0 > And adjusting the state of each of the plurality of multi-level cells with respect to the plurality of pages.

Wherein receiving the write command comprises receiving a single write command and receiving data for the plurality of pages for the single write command; And storing the data for the plurality of pages in a page register.

Wherein the data stored in the page register is maintained until the step of performing the fine writing is completed and the step of performing the fine writing is performed using fine data stored in the page register, Write is executed.

Wherein when the plurality of multi-level cells is an n-bit multi-level cell, the state of each of the plurality of multi-level cells in the operation for coarse writing is determined to be one of 2 ⁿ states, ) ≪ / RTI > changes in the characteristics for any one of the determined states in the operation for writing.

And holding the write command until data corresponding to the n pages is stored in the page register.

A memory device for performing data programming includes a memory array including a plurality of multi-level cells, each of the plurality of multi-level cells storing a plurality of bits and corresponding to a plurality of pages; A receiving unit for receiving a write command; A page register for storing data for the plurality of pages; In response to the write command, performing a coarse write to simultaneously change the state of each of the plurality of multi-level cells with respect to the plurality of pages, And a write executing unit for executing fine writing to adjust the state of each of the level cells.

When each of the plurality of multi-level cells is an n-bit multi-level cell, the write executing unit changes the state of each of the plurality of multi-level cells simultaneously with respect to n pages.

The write execution unit executes the coarse write after the data corresponding to the n pages are stored in the page register.

The write executing unit executes the fine writing after the coarse writing is executed for at least one other write command different from the write command.

Wherein the write implementer is configured to perform the coarse writes on the n pages after the coarse writes have been performed on the other n pages, Level cells of the multi-level cells.

The write execution unit holds the write command until data corresponding to the n pages is stored in the page register.

The storage system includes a controller for receiving data from a host; A plurality of memory devices for receiving data and instructions from the controller via a bus, each of the plurality of memory devices including a plurality of multi-level cells, each of the plurality of multi- Storing a plurality of pages and corresponding to a plurality of pages; A receiving unit for receiving a write command; A page register for storing data for the plurality of pages; In response to the write command, performing a coarse write to simultaneously change the state of each of the plurality of multi-level cells with respect to the plurality of pages, And a write executing unit for executing fine writing to adjust the state of each of the level cells.

By performing a write operation on a multi-level cell, the coarse write operation and the fine write operation are performed to perform a write operation on a multi-level cell without repeating write operations corresponding to the number of pages. This write operation does not need to read the state of the multilevel cell determined by the previous write operation to perform the next write operation, thereby preventing errors due to the read operation. It also reduces interference by neighboring cells and improves the reliability problem that occurs as the write operations are repeated.

1 shows a general flash memory.
2 shows a memory array including n-bit MLCs (Multi Level Cells).
3 is a timing diagram illustrating operations performed on each of the memory devices and commands and data flowing through the bus between the memory devices and the controller in a conventional flash memory.
4 is a diagram showing states of MLCs that can occur in each of a plurality of write operations in a 3-bit MLC.
5 is a timing diagram showing that the next state of the MLC in a general flash memory is determined by the current state and the input data.
6 is a flowchart illustrating a method of performing a data program according to an embodiment.
7 is a timing diagram illustrating operations performed on each of the memory devices and commands and data flowing through the bus in the memory device of the present invention.
8 is a diagram illustrating states of a 3-bit MLC that can be generated according to the coarse write operation of the present invention.
9 is a timing diagram illustrating the coarse write operation and fine write operation of the present invention.
FIG. 10 is a diagram illustrating a state change of a 3-bit MLC when a coarse write operation is performed and a fine write operation is performed according to an embodiment of the present invention.
FIG. 11 is a diagram for explaining execution of a write command for a 3-bit MLC. FIG.
12 illustrates a memory device according to an embodiment of the present invention.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

1 shows a general flash memory.

Referring to FIG. 1, the process of using page-based data 110 in the flash memory chip 120 is shown. The flash memory chip 120 may include a plurality of memory arrays 121. Each memory array may be composed of a plurality of blocks 122 and 123, and each block may be composed of a plurality of pages.

The flash memory executes the data write operation on a page basis. In addition, the flash memory stores data to be stored in a page register. When the flash memory receives a write command, it stores the data corresponding to the write command in the page register in page units, and stores the page in the address received with the write command.

2 shows a memory array including n-bit MLCs (Multi Level Cells).

Referring to FIG. 2, one block includes a plurality of word lines. Each word line includes a plurality of cells. In an n-bit MLC, each cell can store n bits, and the page addresses of n bits stored in one cell are different. For example, in a two-bit MLC, each cell can store two bits, and the two-bit page addresses stored in one cell are different. In a 3-bit MLC, each cell can store 3-bits, and the 3-bit page addresses stored in one cell are different from each other.

3 is a timing diagram illustrating write commands and data that flow through a bus between memory devices and a controller in a conventional flash memory and write operations performed on each of the memory devices.

3, there are data D (i), D (j) and D (k) according to write commands for pages i, j and k in the flash bus, and the flash memory chip has write . Specific data is input to the flash bus according to a write command for specific data, and the flash memory chip performs an operation for writing specific data.

A typical n-bit MLC can store n page data in one cell and n write operations to store n-bit data in the n-bit MLC. For example, a typical flash memory must perform write operations three times to store pages i, j, and k in the flash memory chip.

4 is a diagram showing states of MLCs that can occur in each of a plurality of write operations in a 3-bit MLC.

Referring to FIG. 4, each time the flash memory chip executes a write operation, the number of states of the MLC increases by two times. To store n-bit data in an n-bit MLC requires a total of n write operations, and a write operation doubles each state. Therefore, the maximum value of the number of states of the n-bit MLC is 2 ⁿ . For example, if the state of the MLC before the data is used is 1, and the data write operation is executed 3 times, the state of the MLC is doubled to 2, 4, or 8. In order to store 3-bit data in a 3-bit MLC, three data writing operations are required. Since the number of states of a cell is increased by 2 by each data writing operation, the number of states of a cell is finally 8 .

5 is a timing diagram showing that the next state of the MLC in a general flash memory is determined by the current state and the input data.

Referring to FIG. 5, a general flash memory write operation includes a read operation and a write operation. The read operation may include grasping the current state, and the write operation includes moving to the next state. The next state of a cell in an MLC is determined by the current state of the cell and the input data value. The current state of a cell can be ascertained by reading the data stored in the cell.

Errors that occur when reading from the MLC are accumulated in the next step. Since the next state of a cell is determined by the current state of the cell and the input data value, if an error occurs when reading the current state of the cell, an error also occurs when moving to the next state of the cell. Therefore, as the number of pages stored in one cell increases, the number of read operations also increases, thereby increasing errors occurring in the MLC.

6 is a flowchart illustrating a method of performing a data program according to an embodiment.

Referring to FIG. 6, in step 610, the memory device of the present invention stores n pages in a general page register.

The general page register may be a register for temporarily storing n page data to program n page data into the memory array. The page data must be stored in the general page register until the two-step write of the present invention is completed. The memory device may invalidate the page data stored in the general-purpose page register after the fine writing of the page data stored in the general-purpose page register is completed.

In step 620, the memory device of the present invention performs a coarse write to n pages.

The writing operation of the present invention includes two-step writing. If all the pages that can be stored in one cell are stored in a single write operation, the interference due to the neighboring cells may be increased and the reliability may be deteriorated. Therefore, the write operation of the present invention may be performed by a coarse write operation After that, a fine write operation is performed to increase the reliability of the interfered cells.

The coarse write operation is performed on the cell where the current data is to be stored, and simultaneously changes the state of the bits of the n-page for a series of n-bit MLCs constituting one word line.

In step 630, the memory device of the present invention performs fine writing for n pages that are interfered.

A fine write operation is an operation on a cell that has been interfered by a coarse write operation on the current cell. The fine write operation can improve the reliability of data by adjusting the state of the cell that is interfered by the coarse write operation on the current cell.

Since the two-step write operation of the present invention does not require a read operation unlike a general MLC, it is possible to prevent an error occurring when a read operation is performed in a general MLC to accumulate in a next step.

In step 630, the memory device of the present invention invalidates n pages that have been finely written in the general purpose page register.

The memory device may invalidate n pages that have been finely written in the general purpose page register to block access to the page. For example, the memory device can perform an invalidation process for n pages in which fine writing is completed by controlling bits indicating valid / invalid of the page table.

7 is a timing diagram illustrating operations performed in each of the memory devices and the write command and data flowing through the bus in the memory device of the present invention.

Referring to FIG. 7, the memory device of the present invention stores n-page data that can be stored in one cell at a time. For example, in FIG. 3, in order to store 3-bit data, a general flash memory requires three write commands, three page data according to three write commands, and three write operations. However, the memory device of the present invention can store 3-bit data according to one write command, 3-page data according to one write command, and one write operation. That is, in the case of a 2-bit MLC, 2-pages are stored at once, and in the case of a 3-bit MLC, 3-pages are stored at a time. The memory device of the present invention performs a coarse write operation and a fine write operation in order to store n-page data that can be stored in one cell at a time.

8 is a diagram illustrating states of a 3-bit MLC that can be generated according to the coarse write operation of the present invention.

Referring to FIG. 8, the number of states of a cell after the coarse write operation of the present invention is the maximum number that a specific cell can have. For example, in the case of a 3-bit MLC, since the maximum number of states the cell can have is eight, the number of states of the cells after the coarse write operation of the present invention is eight.

The writing operation of the present invention includes two-step writing. When all pages that can be stored in one cell are stored in a single write operation, reliability may deteriorate due to an increase in interference due to neighboring cells. The write operation of the present invention performs a coarse write operation to increase the performance, and then performs a fine write operation to increase the reliability of the interfered cell.

9 is a timing diagram illustrating the coarse write operation and fine write operation of the present invention.

Referring to FIG. 9, the write operation of the present invention includes a coarse write operation for the current cell and a fine write operation for the interfered cell. The coarse write operation is an operation on the cell where the current data is to be stored. A fine write operation is an operation on a cell that has been interfered by a coarse write operation on the current cell. For the write operation of the present invention, the data must be stored in a register of the flash memory chip until the fine write operation is completed. Since the write operation of the present invention does not require a read operation unlike a general MLC, it is possible to prevent an error that occurs when a read operation is performed in a general MLC to accumulate in a next step.

FIG. 10 is a diagram illustrating a state change of a 3-bit MLC when a coarse write operation is performed and a fine write operation is performed according to an embodiment of the present invention.

Referring to FIG. 10, the number of states of the MLC is maximized according to the coarse write operation. The maximum number of states of the n-bit MLC is 2 ⁿ . Also, according to the fine write operation, each state is modified to a state of better reliability than a state according to a coarse write operation. The fine write operation does not change the number of states of the MLC and improves only the state characteristics of the MLC.

The coarse write operation and the fine write operation change the state of the bits of the n-page at the same time for a series of n-bit MLCs constituting one word line, since they are executed for the word line composed of a series of MLCs. For example, the coarse write operation and the fine write operation for a word line comprised of 3-bit MLCs change the state of the 3-page bits for 3-bit MLCs, respectively.

FIG. 11 is a diagram for explaining execution of a write command for a 3-bit MLC. FIG.

In an n-bit MLC, there can be two ways for a memory device to receive n pages of data for programming n pages of data. First, the memory device can receive n pages of data by receiving a write command for n pages of data once, as in Figures 5 and 7. Secondly, the memory device can receive n pages of data by receiving one write command for one page of data n times. 11 is a diagram for explaining execution of a write command for a 3-bit MLC using the second method of the above method.

Referring to FIG. 11, a flash memory block 1110 is composed of a plurality of word lines, and each of the word lines stores a plurality of pages. Each word line is composed of a plurality of MLCs. Each word line stores a page at a different address. The plurality of page addresses stored in one word line may be sequential.

Table 1120 shows the operations of the flash memory controller and the operation of the flash memory chip according to an embodiment of the present invention.

When the flash memory controller transfers the ProgramPage (B0, P0, D0) instruction to the flash memory chip, the flash memory chip stores the DO in the general page register. For the write operation of the present invention, the data must be stored in a register of the flash memory chip until the fine write operation is completed.

When the flash memory controller transfers ProgramPage (B0, P1, D1) instructions to the flash memory chip, the flash memory chip stores D1 in the general page register.

When the flash memory controller passes ProgramPage (B0, P2, D2) instructions to the flash memory chip, the flash memory chip stores D2 in the general purpose page register and executes the coarse write operation on D0, D1 and D2. Since no fine write operation has been performed on D0, D1 and D2, the flash memory chip continues to store D0, D1 and D2 in the general purpose registers.

When the flash memory controller transfers ProgramPage (B0, P3, D3) instructions to the flash memory chip, the flash memory chip stores D3 in the general page register.

When the flash memory controller passes ProgramPage (B0, P4, D4) instructions to the flash memory chip, the flash memory chip stores D4 in the general page register.

When the flash memory controller passes ProgramPage (B0, P5, D5) instructions to the flash memory chip, the flash memory chip stores D5 in the general purpose page register and executes the rough write operation on D3, D4 and D5. If interference occurs in D0, D1 and D2 according to the coarse write operation for D3, D4 and D5, the flash memory chip performs fine writing for D0, D1 and D2. Since fine writing to D0, D1, and D2 is completed, the flash memory no longer needs to store D0, D1, and D2 in the general purpose page register.

When the flash memory controller passes ProgramPage (B0, P6, D6) instructions to the flash memory chip, the flash memory chip stores D6 in the general page register.

When the flash memory controller sends a ProgramPage (B0, P7, D7) instruction to the flash memory chip, the flash memory chip stores D7 in the general page register.

When the flash memory controller passes ProgramPage (B0, P8, D8) instructions to the flash memory chip, the flash memory chip stores D8 in the general purpose page register and executes the rough write operation on D6, D7 and D8. If interference occurs in D3, D4 and D5 according to the coarse write operation for D6, D7 and D8, the flash memory chip performs fine writing for D3, D4 and D5. Since fine writing to D3, D4 and D5 has been completed, the flash memory no longer needs to store D3, D4, D5 in the general purpose page register.

Each of the data is stored in the flash memory chip by the coarse write and fine write processes. The memory device of the present invention receives a write instruction for a coarse write operation and a fine write operation for one word line and the flash memory controller performs a coarse write operation for one word line Issue a fine write operation command. The coarse write operation and the fine write operation for one word line are performed by a single instruction for the memory device of the present invention. Writing operations by coarse writing and fine writing can not only reduce errors but also improve data writing speed.

12 illustrates a memory device according to an embodiment of the present invention.

12, the flash memory chip 1200 may include a memory array 1210, a general-purpose page register 1220, a receiving unit for receiving a write command, and an execution unit for executing coarse writing and fine writing.

The memory array 1210 may be composed of a plurality of blocks, and each block may be composed of a plurality of pages.

The general-purpose page register serves to store multiple pages until the micro-writing of the page to be stored is completed.

The receiving unit receives a write command for writing data to the flash memory chip 1200. The write command is performed by a save command, a coarse write command, and a fine write command for a series of registers by the flash memory controller. The receiving unit receives a single writing command from the host, and the executing unit executes coarse writing, fine writing, and storage command to the register accordingly.

The execution unit executes coarse write operations and fine write operations. Since the operation procedure for the coarse write operation and the fine write operation has been described above, a detailed description will be omitted.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (21)

A method of programming data in a memory array comprising a plurality of multi-level cells, each of the plurality of multi-level cells storing a plurality of bits and corresponding to a plurality of pages,
Receiving a write command;
Performing coarse writing to change the state of each of the plurality of multilevel cells with respect to a first page group of the plurality of pages at the same time in response to the write command; And
A plurality of pages that are simultaneously changed by the interference of the coarse writing and which are fine to adjust the state of each of a plurality of multilevel cells of a second page group adjacent to the first page group, Steps to run write
/ RTI > The method according to claim 1,
When each of the plurality of multi-level cells is an n-bit multi-level cell,
The step of performing the coarse writing
Varying the state of each of the plurality of multilevel cells for n pages simultaneously
/ RTI > 3. The method of claim 2,
The step of performing the coarse writing
Executing the coarse write after the data corresponding to the n pages is stored in a page register,
Lt; / RTI > The method of claim 3,
The data stored in the page register is held until the step of executing the fine writing is completed,
The step of performing the coarse writing
And performing a coarse write using the data stored in the page register. The method according to claim 1,
When each of the plurality of multi-level cells is an n-bit multi-level cell,
The step of receiving the write command
receiving a write command for n pages once to program data on n pages
/ RTI > The method according to claim 1,
When each of the plurality of multi-level cells is an n-bit multi-level cell,
The step of receiving the write command
receiving a write command for one page n times to program data on n pages
/ RTI > The method according to claim 1,
The step of performing the fine writing
Executing the fine write after the coarse write to at least one other write command distinct from the write command is executed. 3. The method of claim 2,
The step of performing the fine writing
After the coarse writing for the n pages is performed and after the coarse writing for the other n pages has been performed, the plurality of multi-level cells Adjusting each state
/ RTI > The method according to claim 1,
The step of receiving the write command
Receiving a single write command,
Receiving data for the plurality of pages for the single write command; And
Storing the data for the plurality of pages in a page register
Lt; / RTI > 9. The method of claim 8,
The data stored in the page register is held until the step of executing the fine writing is completed,
The step of performing the fine writing
And a fine write is performed using data stored in the page register. The method according to claim 1,
When each of the plurality of multi-level cells is an n-bit multi-level cell,
The state of each of the plurality of multi-level cells in the operation for coarse writing is determined to be one of 2 ⁿ states,
Wherein the characteristic for the determined one of the states changes in the operation for fine writing. 3. The method of claim 2,
Holding the write command until data corresponding to the n pages is stored in a page register
Lt; / RTI > 13. A computer-readable recording medium for performing the method of any one of claims 1 to 12. 1. A memory device for performing data programming,
A memory array including a plurality of multi-level cells, each of the plurality of multi-level cells storing a plurality of bits and corresponding to a plurality of pages;
A receiving unit for receiving a write command;
A page register for storing data for the plurality of pages;
In response to the write command, performing a coarse write to change the state of each of the plurality of multi-level cells with respect to a first page group of the plurality of pages at the same time, A write execution unit which is simultaneously changed by interference of coarse writing and executes fine writing to adjust the state of each of a plurality of multi-level cells of a second page group adjacent to the first page group,
≪ / RTI > 15. The method of claim 14,
When each of the plurality of multi-level cells is an n-bit multi-level cell,
The write-
And simultaneously changes the state of each of the plurality of multi-level cells with respect to n pages. 16. The method of claim 15,
The write-
Wherein the coarse write is performed after data corresponding to the n pages is stored in a page register. 15. The method of claim 14,
The write-
And performs the fine writing after the coarse writing for at least one other write command distinct from the write command is executed. 16. The method of claim 15,
The write-
After the coarse writing for the n pages is performed and after the coarse writing for the other n pages has been performed, the plurality of multi-level cells And each state is adjusted. 15. The method of claim 14,
Wherein the state of each of the plurality of multilevel cells in the operation for coarse writing changes once and the state of each of the plurality of multilevel cells in the operation for fine writing changes more than once
Wherein a change in the state of each of the plurality of multilevel cells in an operation for coarse writing is greater than a change in state of each of the plurality of multilevel cells in operation for fine writing, . 16. The method of claim 15,
And the write execution unit holds the write command until data corresponding to the n pages is stored in the page register. In a storage system,
A controller for receiving data from a host;
A plurality of memory devices for receiving data and instructions from the controller via a bus;
/ RTI >
Each of the plurality of memory devices
A memory array including a plurality of multi-level cells, each of the plurality of multi-level cells storing a plurality of bits and corresponding to a plurality of pages;
A receiving unit for receiving a write command;
A page register for storing data for the plurality of pages;
In response to the write command, performing a coarse write to change the state of each of the plurality of multi-level cells with respect to a first page group of the plurality of pages at the same time, A write execution unit which is simultaneously changed by interference of coarse writing and executes fine writing to adjust the state of each of a plurality of multi-level cells of a second page group adjacent to the first page group,
≪ / RTI >

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