KR101532816B1 - Semiconductor packages and methods of packaging semiconductor devices - Google Patents

Abstract

A semiconductor package and a method of forming a semiconductor package are disclosed. The method includes providing at least one die having a first surface and a second surface. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and one or more dies are attached to the permanent carrier. The first surface of the at least one die faces the support carrier. A cap having a first surface and a second surface is formed to encapsulate the one or more dies. The first surface of the cap is in contact with the permanent carrier and the second surface of the cap is disposed in a plane different from the second surface of the die.

Description

Technical Field [0001] The present invention relates to a semiconductor package and a semiconductor device packaging method,

Cross-reference to related application

This application claims priority to U.S. Provisional Application No. 61 / 413,577, filed November 15, 2010, entitled " Buried Die-out Packaging Structure and Method " This application is a continuation-in-part of U.S. Patent Application No. 13 / 295,097, pending, which is hereby incorporated by reference in its entirety for all purposes.

The industrial fan-out solution includes high capital investment costs for new wafer relocation layer (RDL) and bumping facilities. Moreover, new equipment and retrofit kits for compression molding systems are required to enable wafer handling in pick and place systems for fan-out solutions.

It is desirable to improve the fan-out semiconductor packaging process that can utilize existing tools and processes associated with current wafer level fanout solutions to minimize or avoid the above-mentioned expense. It is also desirable to produce fan-out semiconductor packages with very thin package profiles, higher I / O counts for wafer level chip scale packaging, multi-level redistribution layers, and possible systems in the packaging field. Moreover, it is also desirable to produce a semiconductor package with enhanced heat dissipation capability.

Embodiments generally relate to semiconductor packaging. In one embodiment, there is a method for forming a semiconductor package. The method includes providing at least one die having a first surface and a second surface. The second surface of the die includes a plurality of conductive pads. The method also includes providing a permanent carrier and attaching the one or more dies to a permanent carrier. The first surface of the at least one die faces the support carrier. A cap having a first surface and a second surface is formed to encapsulate one or more dies. The first surface of the cap is in contact with the permanent carrier and the second surface of the cap is disposed in a plane different from the second surface of the die.

In yet another embodiment, a method of forming a semiconductor package is disclosed. The method includes providing at least one die stack having a first surface and a second surface. The second surface of the die stack includes a plurality of conductive pads. A permanent carrier is provided, and one or more die stacks are attached to the permanent carrier. The first surface of the one or more die stack faces the permanent carrier. A cap having a first surface and a second surface is formed to encapsulate one or more die stacks. The second surface of the cap is disposed in a plane different from the second surface of the die stack. The first surface of the cap is in contact with the permanent carrier and the second surface of the cap is disposed in a plane different from the second surface of the die.

BRIEF DESCRIPTION OF THE DRAWINGS In accordance with the other advantages and features of the invention disclosed, these embodiments will become apparent with reference to the following detailed description and accompanying drawings. Moreover, it is to be understood that the features of the various embodiments disclosed herein are not mutually exclusive, and may be present in various combinations and modifications.

In the drawings, like reference numbers generally refer to the same parts throughout the different views. In addition, the drawings are not necessarily to scale, emphasis instead being placed upon generally illustrating the principles of the invention. In the following detailed description, numerous illustrative embodiments of the invention are described with reference to the following drawings.
Figures 1 and 2 show various embodiments of a semiconductor package,
Figures 3A-3H, 4A-4C show various embodiments of a method for forming a semiconductor package.

Embodiments relate to a semiconductor package and a method for forming a semiconductor package. A package is used to package one or more semiconductor die or chips. For the case of more than one die, the die may be arranged in a planar arrangement, a vertical arrangement, or a combination thereof. The die may include, for example, a memory device, a logic device, a communication device, an optoelectronic device, a digital signal processor (DSP), a microcontroller, a system-on-a-chip (SOC) as well as other types of devices, . Such packages can be integrated into devices such as electronics or telephones, computers as well as mobile and mobile smart products. Integration of packages into other types of products may also be useful.

1 shows a simplified cross-sectional view of one embodiment of a semiconductor package 100 showing portion A 'in more detail. The package includes a built-up or integrated wiring substrate 110. The wiring substrate includes first and second major surfaces (111 and 112). The first major surface may be referred to as the top surface, for example, and the second major surface may be referred to as the bottom surface, for example. Other names for the surfaces may also be useful. In one embodiment, the first major surface of the wiring substrate includes first and second regions 111a and 111b. The first region is for example a die or chip region, the die 150 is mounted on a die or chip region, and the second region is for example a non-die region. In one embodiment, the non-die area surrounds the die area. The die area may be disposed, for example, in the central portion where the die 150 is mounted and in the non-die area 111b outside the die attach area. The die area may be disposed concentrically within the periphery of the wiring substrate, for example. Other configurations of die and non-die regions may also be useful.

The die may be a semiconductor die or chip. The die may be of various types including, for example, dynamic random access memory (DRAM), static random access memory (SRAM) and programmable read-only memory (PROM) (IC), such as a memory device, optoelectronic device, logic device, communication device, digital signal processor (DSP), microcontroller, system-on-chip as well as other types of devices, such as non-volatile memory. Type.

The die includes a first surface 150a and a second major surface 150b. The first surface is, for example, the inactive or backside of the die and the second surface is the active surface of the die. Other names for the surfaces of the die may also be useful. The active surface of the die contacts the die area of the wiring substrate. The active surface includes openings in a final passivation layer (not shown) to expose, for example, conductive die pads 155. The surface of the conductive die pad, for example, the can on the second main surface (150b) is substantially the same one plane of the die. It may also be useful to provide a surface of a conductive pad that is not coplanar with the second major surface of the die. The die pad provides the connection of the die to the circuit. The die pad is formed of a conductive material such as copper, aluminum, gold, nickel, or an alloy thereof, for example. Other types of conductive materials may also be used for die pads. The pattern of die pads may be one or more columns disposed at or at opposite sides of the active surface. Other pad patterns such as a grid or matrix array may also be useful.

In one embodiment, the wiring substrate comprises a multi-layer substrate. The multi-layer substrate includes first and second insulating substrate layers 113 and 117 in one embodiment. The first layer includes a first surface 113a and a second surface 113b. The first surface may be referred to as the top surface and the second surface may be referred to as the bottom surface. Other names for the surfaces of the first layer may also be useful. The first surface is in contact with the die. In one embodiment, the first layer includes a through via contact 130 extending from a first surface of the first layer to a second surface. The via contact is formed of a conductive material. For example, the via contact may be formed of copper, aluminum, gold, nickel, or an alloy thereof. Other types of conductive materials may also be useful. The via contacts are insulated from each other by a first insulating substrate layer.

A conductive trace 140 is disposed on the second surface of the first insulating substrate layer. The conductive traces are formed of a conductive material, such as copper, aluminum, gold, nickel, or alloys thereof. Other types of conductive materials may also be useful. The conductive traces are coupled to a substrate via contact forming an interconnect that is coupled to a die pad of the same die. The conductive traces may include conductive pads 168.

The first substrate layer may be a dielectric layer. The dielectric layer is disposed, for example, on the second surface of the die. Other types of first substrate layers may also be useful. In another embodiment, the substrate layer may be patterned to provide vias in which the substrate via contacts are disposed. The formation of vias in the first substrate layer may be achieved by any suitable technique, including laser and mechanical drilling, but is not limited to laser and mechanical drilling.

The second insulating layer layer includes a first surface 117a and a second surface 117b. The first surface may be referred to as the top surface and the second surface may be referred to as the bottom surface. Other names for the surface of the second insulating substrate layer may also be useful. The first surface of the second insulating layer is disposed on the second surface of the conductive trace and the first substrate layer: the second surface functions as the bottom surface of the package. The second substrate layer insulates the conductive traces from each other. The second substrate layer may be formed of a solder mask or other dielectric material. Other types of second substrate layers may also be useful.

An opening is provided in a second substrate layer where a package contact (contact) 170 is disposed. The opening exposes the conductive pad, for example, on the conductive trace. The pattern of openings can be designed to provide the desired package contact pattern. For example, the contact openings can be arranged in a grid pattern to form a BGA type package. Other contact opening patterns may also be useful. The conductive pad is, for example, coplanar with the conductive trace. In other embodiments, the conductive pad may comprise a protruding conductive pad. The conductive pad may be further covered with a surface protective material such as OSP or metal coating or plating.

The outer package contact 170 is disposed on the second substrate layer within the opening. The package contact is, for example, a spherical structure or a ball. The package contact protrudes from the bottom surface of the second substrate layer. It may also be useful to provide a package contact that does not protrude from the bottom surface of the second substrate layer, such as a solder land. The package contact is formed of a conductive material. The package contacts may be formed by soldering in one embodiment. Various types of solder can be used to form package contacts. For example, the solder may be a lead-based or non-lead-based solder. Other types of conductive materials can also be used to form package contacts.

In other embodiments, the package contacts may include other types of package contacts, such as copper pillers or gold stud bumps (not shown). Copper fillers are excellent when they do not impact after reflow. Thus, a copper filler can enable a semiconductor package to be produced with a much more pronounced pitch and a more uniform standoff height. On the other hand, gold stud bumps can sometimes be used in connection with anisotropic conductive adhesive and thermal compression welding methods to achieve title pitch. This is excellent when an IC chip originally designed with peripheral bond pads intended for wire bonding can be used as flip chips. Other suitable types of package contacts may also be used.

The package contacts provide external access to the die via conductive traces, substrate via contacts, and die pads. The package may be electrically coupled to an external device (not shown), such as a circuit board, by package contacts.

In one embodiment, the build-up wiring substrate is an integrated package substrate. As discussed above, the package substrate is in direct contact with the die in the die region, and the conductive traces and via contacts are coupled to die pads of the same die. In one embodiment, an integrated package substrate includes via contacts that are directly coupled to die pads of the same die. The wiring substrate functions as a fanout redistribution structure for the die, enabling the redistributed fan-out external package connection.

As described above, the first substrate layer is a single layer. In another embodiment, the first substrate layer 113 may comprise a plurality of second sub-layers. For example, the first substrate layer may comprise a first and a second first sub-layer. It may also be useful to provide a first substrate layer with a different number of first sub-layers. The first and second first sub-layers may comprise the same material, for example. It may also be useful to provide a first sub-layer having a different material than the second sub-layer. The first sub-layer is similar to the first substrate layer. For example, the first sub-layer comprises first and second surfaces and the substrate via contact extends through the conductive traces and surfaces on the second surface. The first surface of the sub-layer contacts the second surface or die of the adjacent first sub-layer. This creates a layered stack with a first substrate layer or multiple conductive layers. Providing a first substrate layer having multiple build-up conductive layers can facilitate a package for a die having higher density die contacts and package contacts.

In one embodiment, the cap 190 is formed over the second region 111b of the first major surface 111 of the package substrate. The cap serves to protect the die from the environment. For example, the cap can protect the die from moisture. The cap is formed, for example, from an encapsulating material. The encapsulating material may be, for example, a molding epoxy resin material. Other types of encapsulating materials may also be useful.

The cap includes first and second major surfaces 190a-190b. The first surface may be, for example, the top surface and the second surface may be the bottom surface. Other names for the surface of the cap may also be useful. In one embodiment, the cap encircles at least the die. For example, the bottom surface 190b is disposed on the package substrate on the non-die region of the package substrate. The cap protects the die by surrounding the die.

In one embodiment, the non-die area is disposed in a different plane than the die area. For example, as shown by portion A ', the die and non-die regions form a step 187 in the package substrate. In one embodiment, the die area is disposed or recessed into the encapsulant material with respect to the first major surface 190a of the cap. For example, the die area 111a has a greater distance from the bottom 117b of the package substrate than the non-die area 111b. The non-die area is over the conductive die pad or die area, for example, with respect to the first major surface 190a of the cap. Referring to FIG. 1A, the second surface of the die is disposed in a plane different from the second surface of the cap. Providing the bottom surface of the cap in a different plane than the die advantageously alleviates mechanical stress on the die by thermal mismatch of the package material.

In one embodiment, the cap does not cover the first surface or the back surface of the die, as shown in Fig. For example, the top surface 190a of the cap is substantially flush with the back surface 150a of the die. Alternatively, the top surface of the cap need not be flush with the back surface of the die. For example, the first surface 190a of the cap is on the back surface 150a of the die, depending on the thickness of the adhesive layer disposed on the back surface of the die.

In one embodiment, the carrier 185 is permanently disposed on the back surface 150a of the die and on the top or first surface 190a of the cap. For example, the carrier remains a part of the packaged die. The carrier includes first and second major surfaces. The first major surface 180a For example, the top surface of the carrier and the second major surface 180b is the bottom surface of the carrier. Other designs for the surface of the carrier can also be used. In one embodiment, the second surface of the carrier contacts at least the first surface of the cap while the first surface of the carrier is exposed. The second surface of the carrier substantially covers the entire first surfaces of the cap and die, for example.

In one embodiment, adhesive 175 is provided on the second surface of the carrier. The adhesive bonds at least the carrier and the die, for example. In one embodiment, an adhesive is provided at least between the second surface of the carrier and the first surface of the die. In another embodiment, an adhesive may also be provided between the second surface of the carrier and the cap and the first surface of the die. The adhesive includes, for example, a film, paste, liquid or thermally conductive adhesive. Other suitable types of adhesives that facilitate bonding between at least the carrier and the die may also be used. The adhesive may include an appropriate thickness to at least permanently bond the die and carrier during processing.

As shown in FIG. 1, the carrier substantially covers the entire first surfaces of the die and cap. In one embodiment, the carrier may be sufficiently rigid to serve as a permanent carrier or permanent support for holding the die or die stack during assembly. This will be described in detail later. Alternatively or additionally, the carrier may also function as a thermal conductor for dissipating heat from the die or die stack of the semiconductor package. By way of non-limiting example, the carrier may comprise a wafer or a conductive plate. For example, the wafer may comprise a silicon wafer and the conductive plate may comprise a metal plate. Other suitable types of materials may also be used to form the carrier. The semiconductor package may also include an additional heat sink or a heat spreader to reinforce heat dissipation. For example, a thermal sprayer (not shown) may be attached on the carrier to further improve heat dissipation.

FIG. 2 shows another embodiment of the semiconductor package 200. FIG. The semiconductor package is similar to that shown in Fig. As such, the common elements may or may not be described in detail.

The semiconductor package 200 includes a die stack 210 mounted on a die region 111a of the wiring substrate 110. The die stack 210 is mounted on the die region 111a of the wiring substrate 110. [ The die stack includes n dies, where n is at least 2. The bottom die may be referred to as the first (e.g., n = 1) and the top die is n. It may also be useful to refer to the die of the die stack using other conventions. The die stack can be formed by, for example, any suitable type of die stacking method. As shown, the die stack includes first and second dies 250 ₁ and 250 ₂ . The second die 250 ₂ is attached onto the first die 250 ₁ and the first die is attached to the die area 111 a of the wiring substrate 110. The die used for the die stack may be a TSV or a non-TSV die. In one embodiment, both the top die and the bottom die may be TSV dies. In yet another embodiment, the bottom die may include a TSV die and the top die may comprise a non-TSV die. Non-TSV dies may include, for example, bonded wires, direct connections, flip chip die, and the like. For a die stack having more than two dies, the bottom die (bottom and middle die except the top die) is usually a TSV die whereas the top die is a non-TSV die. Other configurations or types of die in the die stack may also be useful.

The TSV die includes first and second major surfaces 250a-b. The first surface includes a first die contact 233 and the second major surface comprises a second die contact 235. [ The die contact has, for example, a first major surface 250a of the die and a top surface coplanar with the second major surface 250b. It may also be useful to provide a surface of a contact pad that is not coplanar with the surfaces of the die. Other configurations of die contacts or die contact pads may also be useful. The first and second die contacts are interconnected by a via via contact (230). Other configurations of TSV dies may also be useful. The via contact and the contact pad are formed of, for example, a conductive material. The conductive material may include, for example, copper. Other types of conductive materials may also be used for via contacts and contact pads.

As shown, the second die contact 235 of the bottom die is mounted onto the die area 111a of the wiring substrate. The first die contact 233 is aligned with the top die of the die stack. In one embodiment, a die attach film or underfill 217 may be provided in the cavity formed between the dies to facilitate stacking and to provide a conductive die (not shown) of the first die contact 233 of the first die and the second die Thereby protecting the bonding contact 240 that couples the pad 155. A redistribution layer may also be provided. Similar to FIG. 1, the die and non-die regions of semiconductor package 200 form step 187 within the package substrate. For the case of two or more dies used to form the die stack, the bottom and intermediate die may include a TSV die. It may also be useful to provide a bottom and intermediate die with a non-TSV die. The second die contact of the n ^th + 1 die above is connected to the first die contact of the n ^th die below.

The cap 190 is provided to encapsulate the die stack 210. In one embodiment, the cap surrounds at least the die stack. For example, the cap surrounds and protects at least the sides of the first and second dies 250 ₁ , 250 ₂ of the die stack. Similar to FIG. 1, the die area is disposed or recessed into the encapsulant material against the first major surface 190a of the cap 190. In one embodiment, the first surface 190a of the cap is substantially coplanar with the first surface 150a of the second end of the die stack. The cap does not cover, for example, the first surface or the rear surface of the second die of the die stack. Alternatively, the first surface of the cap need not be coplanar with the first surface of the second die of the die stack. For example, the first surface of the cap is disposed over the back surface of the second die of the die stack, depending on the thickness of the adhesive layer, which is disposed on the back surface of the second die, as described below. The bottom surface of the cap is disposed on the non-die area of the wiring substrate.

In one embodiment, a carrier 185, similar to the carrier described in FIG. 1, is permanently disposed on the second die of the die stack and the first surface of the cap. The second surface 180b of the carrier contacts at least the first surface 190a of the cap while the first surface 185a of the carrier is exposed. The second surface of the carrier substantially covers the entire first surfaces of the cap and die, for example. An adhesive 175 similar to the adhesive as described in FIG. 1 is provided on the second surface of the carrier. In one embodiment, an adhesive is provided between at least the second surface 185b of the carrier and the first surface 150a of the die. In another embodiment, an adhesive may also be provided between the second surface of the carrier and the first surfaces of the cap and die. The adhesive may, for example, permanently bond at least between the carrier and the die.

3A-3H illustrate an embodiment of a method for forming a semiconductor package 300. FIG. Figure 3A shows a wafer 301 having a first surface 301a and a second surface 301b. The wafer functions as a substrate for forming the die 350. The first surface is for example an inactive surface 350a while the second surface is an active surface 350b. Other names of surfaces may also be useful. The wafer may be, for example, a silicon wafer. Other types of semiconductor wafers may also be useful. In one embodiment, the wafer is processed to include a plurality of dies or chips. For example, a plurality of dies are processed in parallel on a wafer. Illustratively, the wafer includes three dies that are processed in parallel. It may also be useful to provide a wafer having a different number of die or chips.

The die 350 includes circuit components formed on the wafer or substrate. The circuit components include, for example, transistors, resistors, capacitors, and interconnection to form an IC. A final passivation layer may be formed over the die. The final passivation layer includes openings for exposing die pads 355. The surface of the substrate or wafer comprising the openings to the die pads may be referred to as the active surface of the wafer.

In one embodiment, a sacrificial layer 377 is formed on the active surface of the wafer 301b. The sacrificial layer is a temporary layer that is subsequently removed. The sacrificial layer is, for example, an adhesive material. Other types of sacrificial layers may also be used. The sacrificial layer may be formed on the substrate using a variety of techniques. For example, the sacrificial layer may be provided by spin coating or lamination. Other techniques for forming a sacrificial layer may also be useful. The technique may depend, for example, on the type of sacrificial layer. In one embodiment, the sacrificial layer can be semi-cured to reduce stickiness during the capsule process. In another embodiment, the sacrificial layer remains tacky to improve adhesion to the support carrier when used.

The process continues by dicing the wafer being processed with the sacrificial layer and the die on the active surface of the wafer. Dicing the wafer separates the die into individual dies with a sacrificial layer on the active surface. In yet another embodiment, the sacrificial layer 377 may be formed on the active surface of the die after dicing the wafer into individual dies.

Referring to Figure 3B, a carrier 385 is provided. In one embodiment, the carrier is, for example, the permanent carrier or permanent support used to process the chip package. In one embodiment, the carrier should have sufficient stiffness to withstand further processing steps and function as a support that permanently releases the die. For example, the carrier should have sufficient stiffness to reduce or prevent deflection of the chip assemblies during the assembly process. Alternatively or additionally, the carrier may also serve as a thermal conductor for dissipating heat, for example, from a die of a semiconductor package. By way of non-limiting example, the carrier may be a wafer or a conductive plate. For example, the wafer may comprise a silicon wafer and the conductive plate may comprise a metal plate. Various other types of materials may be used to form the carrier.

The carrier includes a first surface 385b on which the die is processed to form a package. The carrier may be configured in strip format to process the rows of die. In another embodiment, the carrier is configured to process a plurality of rows of die. For example, the carrier may have a panel format to form a two-dimensional array of packages. It may also be useful to provide a carrier configured in wafer format to form a plurality of packages. In some embodiments, the carrier may be configured to form a single package, e.g., a single format. The type of the selected format may be subject to, for example, the requirements of the process, available equipment, or cost considerations.

Illustratively, the carrier is configured in a strip format with zones 380a through 380c for forming three pocket regions or three pockets. It may also be useful to provide a carrier with a different number of pocket regions or formats. The package region includes a die region and a non-die region. The size of the package area is almost the same as the size of the package. A die 350 coated with a sacrificial layer 377 on the active surface 350b is attached to the die area. For example, three dies 350 _1-3 are attached to the die area on the permanent carrier.

In one embodiment, adhesive 375 is provided on the first surface 385b of the carrier to facilitate die attachment. Other bonding techniques may also be used to attach the die to the carrier. The adhesive is provided at least in the die area on the carrier, for example, to permanently hold the chip assembly thereon. In one embodiment, the adhesive is provided only in the die area. In another embodiment, the adhesive is provided on the entire first surface 385b of the carrier.

In another embodiment, adhesive 375 may be provided on the inert surface of the wafer. The adhesive may be applied, for example, either before or after dicing the wafer into individual dies.

The adhesive may be any type of adhesive that provides permanent bonding of the chip assembly to the chip assembly surface of the carrier. The adhesive 375 may comprise the same material as the sacrificial layer 377, for example. In other embodiments, the adhesive 375 may comprise a different material than the sacrificial layer. The adhesive may include an appropriate thickness to bond the die and carrier permanently during processing. The adhesive may be of a different type. For example, the adhesive may be a film, a liquid, or a thermally conductive adhesive. The adhesive may be provided to the inert surface of the wafer or die or to the carrier using a variety of techniques. The technique applied may depend on the type or type of adhesive. For example, a tape glue may be provided on the carrier by a laminate, and the paste glue may be provided on the carrier by printing, while the liquid glue may be provided on the carrier by spin-coating. It may also be useful to provide an adhesive to the inert surface of the wafer or die, carrier, using other techniques.

In one embodiment, the inert surface 350a or the back side of the die is attached to the die area of the carrier. The die is attached to the die area using any suitable technique depending on the type of adhesive used and the equipment.

Referring to FIG. 3C, a cap 390 is formed to encapsulate the die. In one embodiment, the cap is disposed in the non-die area of the permanent carrier. For example, the encapsulating material is dispensed to fill the space between the dies. In one embodiment, the encapsulating material is a mold compound, such as a molding epoxy resin material. It may also be useful to provide other types of encapsulating material.

In one embodiment, the cap is formed by transfer molding techniques. In one embodiment, the cap is formed by a film-assisted transfer molding technique. For example, the film 393 is disposed in contact with the contour of a mold (not shown). In one embodiment, when the carrier and die are placed against the mold, the film contacts the sacrificial layer on the active surface of the die, leaving a space therebetween in the non-die area. An encapsulating material, such as a mold compound, is dispensed into the mold assembly to fill the space within the non-die area to form a cap. The sacrificial layer protects the active layer of the die from the encapsulating material. After molding, the molded panel of the die is separated from the mold. The sacrificial layer also facilitates the release of the molded panel from the molding tool. Other techniques for forming the cap may also be useful. For example, the cap may be formed by printing or crimp molding.

The removal of the mold leaves a plurality of die attached to each other by the cap 390 and the carrier 385. The carrier provides additional mechanical support for the chip for further processing. The surface of the cap is coplanar with the surfaces of the die in one embodiment. For example, the first surface 390a of the cap is coplanar with the first surface 350a or the rear surface of the die and the second surface 3390b is the active surface of the die or the sacrificial layer 377). Alternatively, the first surface of the cap need not be flush with the first surface of the die. For example, the first surface 390a of the cap is disposed in a plane different from the back surface 350a of the die, depending on the thickness of the adhesive layer 375 disposed in the die area on the surface 385b of the carrier. External heat sink or heat spreader (city May also be attached to the back surface 385a of the carrier to further improve heat dissipation.

Referring to FIG. 3D, the sacrifice layer 377 is removed. In one embodiment, the sacrificial layer is removed by dissolving the layer with a chemical. For example, chemicals that preferably do not cause any damage to the second or active surface of the die are used to remove the sacrificial layer. Other techniques can also be used to remove the sacrificial layer. The removal of the sacrificial layer exposes the active or second surface of the die and die contact pads 355. The cleaning step may optionally be performed to clean the contact pad and the second surface of the die. For example, a solvent based on a cleaning step can be applied. Other suitable cleaning techniques are also useful.

In one embodiment, the second surface 390b of the cap is not coplanar with the active surface 350b of the die. For example, the active surface of the die and the second surface of the cap form step 387. In one embodiment, the active surface of the die is recessed below the surface of the cap. The height of the step may be, for example, substantially the thickness of the sacrificial layer. Other step heights may also be useful.

By providing a step between the active surface of the die and the cap surface, the mechanical stress due to the difference between the thermal coefficient of the mold compound and the die in the subsequently formed package is mitigated.

The process continuously forms the package substrate. The process continues to form, for example, a built-up or integrated wiring substrate. The package substrate includes, for example, a multi-layer substrate. In one embodiment, a first insulating substrate layer 313 is provided on the active surface of the die and on the second surface of the cap. For example, the first substrate 313a of the first substrate layer contacts the second surface of the cap and fills the recess on the die.

In one embodiment, the first substrate layer may be a dielectric layer. The dielectric layer is disposed, for example, on the active surface of the die. Other types of first substrate layers may also be used. The dielectric material may be deposited via any suitable technique, such as wafer processing techniques, spin coating, printing, and the like. Other techniques for depositing the first substrate layer may also be useful.

Vias 315 are formed in the first substrate layer. The vias extend from the second surface 313b through the first surface 313a to expose the contact pads of the die. In one embodiment, the vias are formed by laser drilling. Other techniques such as mechanical drilling or RIE are also useful. The vias may have a tapered or straight profile, depending on the type of process and the process requirements of the via formation method used. In one embodiment, the vias are formed with a straight profile. It is also useful to provide a tapered profile (not shown). In particular, tapering of the sidewalls facilitates filling of the vias. For example, the tapered sidewalls facilitate uniform material coverage of the base and sidewalls of the vias that reduce the formation of voids.

Referring to FIG. 3F, the process continues to form the trace 340 of the package substrate and the conductive via contact 330. In one embodiment, a conductive layer is formed on the first substrate layer to fill the via by covering the second surface of the first substrate layer. The conductive layer may be, for example, copper or a copper alloy. Other types of conductive materials may also be useful. For example, other types of conductive materials may include aluminum, gold, nickel, or combinations or alloys thereof. The conductive layer may be formed by plating. For example, electrochemical or electroless plating may be applied to form a conductive layer. Other suitable methods of forming a conductive layer may also be used. In certain embodiments, a seed layer may be used prior to forming the conductive layer.

The patterning of the conductive layer may be formed by a patterned masking layer prior to the plating process. Alternatively, the conductive layer may be patterned to form a conductive trace 340 that is coupled to a substrate via contact 330 in a via that is coupled to a die pad of the same die. The conductive traces and vias form the interconnect. The patterning of the conductive layer may be achieved by any suitable etching technique. For example, a patterned etch mask, such as a photoresist, is provided over the conductive layer. Etching may be performed using an etch mask to remove portions of the conductive layer that are not protected by the etch mask. For example, isotropic etching such as wet etching. Anisotropic etching, such as reactive ion etching (RIE), may be used. Other techniques for patterning the conductive layer may also be used.

After patterning the conductive layer, the mask is removed. The mask can be removed, for example, by ashing. Other techniques for removing the mask may also be used.

3A, a second insulating substrate layer 317 having a first surface 317a and a second surface 317b is deposited on the first substrate layer to fill and fill the space between the conductive traces . The second substrate layer provides insulation between the conductive traces. The first surface 317a of the second substrate layer is in contact with the first substrate layer. The second substrate layer functions as a contact mask. In one embodiment, the second substrate is formed of a polymer. The second substrate layer may be formed by, for example, spin-coating. Other types of dielectric materials and deposition techniques may be useful for forming the second substrate layer.

The second substrate layer is patterned to form contact openings 319 to expose portions of the conductive traces. The contact openings correspond to the locations of the package contacts of the semiconductor package. For example, the contact openings may be arranged in a grid pattern to form a BGA type package. Other contact opening patterns may also be used.

In one embodiment, a package or conductive pad 368 is formed on the exposed portion of the conductive trace 340, as shown in Figure 3H. In one embodiment, the package pad comprises a conductive material. In one embodiment, the package pads are selectively formed within the openings of the dielectric layer by a coating or plating technique. Other types of conductive materials or techniques may be used to form the contact pads. The conductive pad is, for example, coplanar with the conductive trace. In another embodiment, the conductive pad may comprise a protruding conductive pad. The conductive pad may be additionally covered with a surface protective material such as OSP or metal coating or plating.

The process continues by forming a package contact 370 in the opening of the package mask, as shown in Figure 3H. For example, a package contact is formed on the package pad 368 in the opening of the package mask. The package contact may include, for example, a ball or spherical structure disposed within the grid pattern to form a BGA type package. The package contact is formed of a conductive material. The package contacts may be formed by soldering in one embodiment. Various types of solder can be used to form package contacts. For example, the solder may be a lead-based or non-lead-based solder.

In certain embodiments, other types of package contacts are formed in the openings. For example, the package contact may include a contact that does not protrude from the bottom surface of the second substrate layer. It may also be useful to provide a package contact that does not protrude from the bottom surface of the second substrate layer, such as a solder land. The package contacts may be formed using materials other than solder or other techniques.

In yet another embodiment, the package contact may include copper pillers or gold stud bumps (not shown). The use of copper fillers is excellent when they do not collide after reflow. Thus, a copper filler can enable a semiconductor package to be produced with a much more pronounced pitch and a more uniform standoff height. On the other hand, gold stud bumps can sometimes be used in connection with anisotropic conductive adhesive and thermal compression welding methods to achieve title pitch. This is excellent when an IC chip originally designed with peripheral bond pads intended for wire bonding can be used as flip chips. Other suitable types of package contacts may also be used.

The process consecutively sums the structure to form an individual semiconductor package. A semiconductor package is formed as shown in Fig.

4A-4C illustrate another embodiment of a process for forming a semiconductor package 400. FIG. The process is similar as described in Figures 3A-3H. As such, the common elements may not be described above or may not be described in detail. 4A, a wafer 401 having a die stack arrangement is provided. In one embodiment, the wafer is processed to include a plurality of die stacks 410.

The die stack includes n dies and n is 2 or more. The bottom die may be referred to as the first (e.g., n = 1) and the top die is n. It may also be useful to refer to the die of the die stack using other conventions. The die stack can be formed, for example, by any suitable type of die stacking methods. As such, the die stack includes first and second dies 450 ₁ and 450 ₂ . The second die 450 ₂ is attached onto the first die 450 ₁ , and the first die is attached to the die area of the wiring substrate. The die used for die stack may be TSV or non-TSV. In one embodiment, both the top and bottom dies can be TSV dies. In yet another embodiment, the bottom die may include a TSV die and the top die may comprise a non-TSV die. Non-TSV dies may include, for example, bonded wires, direct connections, flip chip die, and the like. For a die stack having two or more dies, the bottom die (bottom and middle die except the top die) may be a TSV die, while the top die may be a non-TSV die. Other configurations or types of die in the die stack may also be useful.

The TSV die includes first and second major surfaces 450a and 450b. The first surface includes a first die contact 433 and the second major surface includes a second die contact 435. [ The die contacts are die contact pads having, for example, an upper surface that is flush with the first and second major surfaces of the TSV die. It may also be useful to provide a surface of the contact pad that is not coplanar with the surface of the die. Other configurations of die contacts or die contact pads may also be useful. The first and second die contacts are interconnected by a via via contact (430). Other configurations of TSV dies may also be useful. The via contact and the contact pad are formed of, for example, a conductive material. The conductive material may include, for example, copper. Other types of conductive materials may also be used for via contacts and contact pads.

As shown in FIG. 4A, the first die contact 433 coincides with the second die of the die stack. Die attach film or underfill 417 may be used to protect the bonding contact 440 coupling the first die contact 433 of the first die and the conductive die pad 355 of the second die, May be provided in the cavity formed between the dies to facilitate the operation of the die. For the case where two or more dies are used to form the die stack, the bottom and middle dies may be TSV dies. Other types of dies may also be used for the bottom and middle dies. n ^th The second die contact of the + 1 die is connected to the first die contact of the n ^th die below.

In one embodiment, a sacrificial layer 377 is formed on the die stack or the second major surface 450b of the first die 450 ₁ of the wafer 401.

The process continues by dicing the wafer being processed with the sacrificial layer and the die stack on the second surface of the wafer. The dicing the wafer to separate the individual dies in the die stack stack (410 _1-3). Although three die stacks are shown in FIG. 4B, it is understood that a different number of die stacks may also be provided on top of the second surface 450b. In yet another embodiment, the sacrificial layer 377 may be provided after dicing the wafer into individual die stacks.

Referring to FIG. 4B, the process is in a similar stage as described in FIG. 3B. For example, the carrier 385 with the adhesive 375 on the first surface (385b) of the carrier is provided with a die stack (410 _1-3) which is attached to the die area on the carrier. In one embodiment, the backside or first surface 350a of the second die of the die stack is in contact with the die region having the adhesive 375 of the carrier 385. [ The die stack is attached to the die area using any suitable technique depending on the type of equipment and adhesive used. In one embodiment, the carrier serves as the used permanent carrier for processing the chip package. In one embodiment, the carrier should have sufficient stiffness to function as a permanent support for holding the die stack during assembly. Alternatively or additionally, the carrier may also serve as a thermal conductor for dissipating heat, for example, from the die stack of the semiconductor package. By way of non-limiting example, the carrier may be a wafer or a conductive plate. For example, the wafer may comprise a silicon wafer and the conductive plate may comprise a metal plate. Various other types of materials may be used to form the carrier.

In one embodiment, an adhesive 375 is provided on the first surface of the carrier to facilitate die stack attachment. Other bonding techniques may also be used to permanently bond the die stack to the carrier. The adhesive is provided at least in the die area on the carrier, for example, to permanently hold the chip assembly thereon. In one embodiment, the adhesive is provided in the die area of the cradle. In another embodiment, an adhesive is provided on the entire first surface of the carrier.

In another embodiment, an adhesive 375 may be provided on the first surface of the wafer. The adhesive may be applied, for example, either before or after dicing the wafer into individual die stacks. For example, the adhesive may be applied to the back surface or first surface 350a of the second die of the die stack.

The process continues forming a cap 390 as shown in Fig. 4c. In one embodiment, the cap is formed of an encapsulation material similar to that described in Fig. 3C. In one embodiment, the cap covers the sides of the die stack as shown in Figure 4c.

After forming the cap, the process continues as described similarly in Fig. 3d. For example, the process continues to form a semiconductor package as described in FIG. 3D and proceeds to produce a semiconductor package as described and illustrated in FIG.

The process as described with respect to Figures 3a-3h and 4a-4c yields excellent results. For example, the sacrificial layer is used to protect the second major surface or active surface of the die or die stack from contamination during molding. In particular, the sacrificial layer is a temporary coating that is removed after molding to reduce the mechanical stresses that result from thermal mismatch between the mold compound and the die or die stack by making recesses on the second surface of the die or die stack Function. In addition, the process allows various molding techniques such as printing, transfer and crimp molding to be used to form the cap.

It is understood that although only one conductive via and trace levels are formed and bonded to the die pads of the same die in the package substrate, additional conductive vias and trace levels may be included. For example, the first substrate layer may comprise a plurality of first sub-layers. Therefore, the process can build up a plurality of wiring structures within the package substrate, as compared to existing wafer based fanout processes, which are limited to a single metal layer fanout structure. Moreover, since the cap functions as a multipurpose machine support and the structure made from the package substrate is made in the form of a panel or strip, the substrate process can be used to form a redistribution structure on the active surface of the die. Likewise, a conventional wafer redistribution layer forming process is not necessarily required. This avoids the need for investment in new wafer-based process equipment.

Additionally, the carrier as described serves as a permanent carrier or permanent support for holding the die or die stack during assembly. Likewise, the permanent carriers provide additional support for die or die stack during assembly and during formation of the redistribution structure on the active surface of the die. Moreover, the carrier remains as part of the packaged structure. Likewise, the process for forming a semiconductor package is simple since the step of removing the adhesive from the carrier and the carrier is removed. Additionally, depending on the material used for the carrier, the permanent carrier also serves as a thermal conductor for dissipating heat from the die or die stack of the semiconductor package. The permanent carrier therefore makes it possible to produce a semiconductor package with a reinforced thermal span.

In addition, at least the permanent adhesive used to bond the carrier and the die avoids problems such as resin leakage and prevents shifting of the die during the molding process to form the cap. In addition, the processor for forming the semiconductor package may be further configured so that additional process steps are not required to remove the extra encapsulation material to expose the first or second surface of the die for further processing. It becomes simple.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. Accordingly, the above-described embodiments are to be considered in all respects as illustrative and not restrictive on the invention as described herein.

Claims (20)

A method for forming a semiconductor package,
Providing at least one die having a first surface and a second surface, wherein the second surface of the die comprises a plurality of conductive pads;
Providing a permanent carrier, and attaching the one or more dies to the permanent carrier, wherein a first surface of the one or more dies faces the permanent carrier;
Forming a cap having a first surface and a second surface to encapsulate said one or more dies to form a structure, wherein a first surface of said cap contacts a permanent carrier and a second surface of said cap And is disposed in a plane different from the second surface of the die; And
Wherein the permanent carrier remains as part of the discrete semiconductor package after the step of developing the semiconductor package. ≪ RTI ID = 0.0 > 11. < / RTI &
A method for forming a semiconductor package.
The method according to claim 1,
Providing an adhesive on a first surface of the permanent carrier,
A method for forming a semiconductor package.
3. The method of claim 2,
Providing the adhesive to a die region on a first surface of the permanent carrier to at least permanently hold the at least one die in the permanent carrier,
A method for forming a semiconductor package.
The method according to claim 1,
Providing an adhesive on a first surface of the die,
A method for forming a semiconductor package.
The method according to any one of claims 2 to 4,
The adhesive may comprise a film, paste, liquid or thermally conductive adhesive.
A method for forming a semiconductor package.
The method according to claim 1,
The permanent carrier comprises a wafer or a conductive plate.
A method for forming a semiconductor package.
The method according to claim 1,
Wherein attaching the one or more dies to a permanent carrier is performed prior to forming the cap,
A method for forming a semiconductor package.
The method according to claim 1,
Forming a sacrificial layer on a second surface of the one or more dies;
A method for forming a semiconductor package.
9. The method of claim 8,
And removing the sacrificial layer after forming the cap.
A method for forming a semiconductor package.
The method according to claim 1,
Wherein the cap is formed by a molding technique comprising transfer molding or crimp molding,
A method for forming a semiconductor package.
The method according to claim 1,
Forming a build-up package substrate having an interconnect on a second surface of the at least one die, wherein the interconnect is coupled to a conductive pad of the same die,
A method for forming a semiconductor package.
12. The method of claim 11,
The step of forming the build-up package substrate comprises:
Providing a first patterned substrate layer having vias on a second surface of the at least one die; And
And forming the interconnect,
Wherein forming the interconnect comprises providing a conductive layer on a surface of the substrate layer to form a substrate via contact and a conductive trace in the via, wherein the conductive trace and the contact are coupled to a conductive pad of the same die ,
A method of forming a semiconductor package.
A method of forming a semiconductor package,
Providing at least one die stack having a first surface and a second surface, wherein the second surface of the die stack comprises a plurality of conductive pads;
Providing a permanent carrier and attaching the at least one die stack to the permanent carrier, the first surface of the at least one die stack facing the permanent carrier;
Forming a cap having a first surface and a second surface to encapsulate the one or more die stacks to form a structure, wherein a first surface of the cap is in contact with the permanent carrier and a second surface Is disposed in a plane different from the second surface of the die stack; And
Wherein the permanent carrier remains as part of the discrete semiconductor package after the step of developing the semiconductor package. ≪ RTI ID = 0.0 > 11. < / RTI &
A method of forming a semiconductor package.
14. The method of claim 13,
Providing an adhesive on a first surface of the permanent carrier,
A method for forming a semiconductor package.
15. The method of claim 14,
Providing the adhesive to a die region on a first surface of the permanent carrier to at least permanently hold the at least one die in the permanent carrier,
A method for forming a semiconductor package.
14. The method of claim 13,
Providing an adhesive on a first surface of the die,
A method for forming a semiconductor package.
The method according to any one of claims 14 to 16,
The adhesive may comprise a film, paste, liquid or thermally conductive adhesive.
A method for forming a semiconductor package.
14. The method of claim 13,
The permanent carrier comprises a wafer or a conductive plate.
A method for forming a semiconductor package.
14. The method of claim 13,
Wherein attaching the one or more dies to a permanent carrier is performed prior to forming the cap,
A method for forming a semiconductor package.
14. The method of claim 13,
Forming a sacrificial layer on a second surface of the one or more dies;
A method for forming a semiconductor package.

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