KR101502998B1 - Memory system and management method therof - Google Patents

Abstract

The memory system includes a plurality of layers of memory, and includes an upper memory layer, a first sub-memory disposed below the upper memory layer, the first sub-memory including a non-volatile memory, and a second sub- And a memory management unit for controlling operations of the upper memory layer and the intermediate memory layer, wherein the intermediate memory layer is referred to by the upper memory layer, The data corresponding to a predetermined condition among the data stored in the second sub-memory in the normal mode operation of the user terminal including the user terminal in advance in the first sub-memory.

Description

[0001] MEMORY SYSTEM AND MANAGEMENT METHOD THEROF [0002]

The present invention relates to a memory system of a new structure and a management method thereof.

2. Description of the Related Art Recently, various types of electronic devices have been used. Particularly, due to the development of communication technology and computer manufacturing technology, a smart phone, a personal digital assistant (PDA) , Portable terminals such as tablet PCs, and the like are also widely used.

Such various user terminal devices often require low power consumption characteristics and heat prevention characteristics while improving computing performance.

The present invention intends to satisfy the low power consumption characteristic and the heat generation prevention characteristic required for the user terminal by improving the structure of the memory system included in the portable terminal.

1 is a diagram illustrating a memory hierarchical structure applied to a memory system according to a conventional technique.

The memory system 1 according to the prior art includes a L1 / L2 cache memory layer 10, a main memory layer 20 and a storage device 30 and is connected to a central processing unit (CPU) Data.

The L1 / L2 cache memory layer 10 and the main memory layer 20 are constituted by volatile memories such as SRAM and DRAM, and the storage device 30 may be a flash memory or a hard disk drive drive, HDD), and other non-volatile memory.

Generally, in a hierarchical structure of a memory, an expensive memory having a higher read / write speed is used for a higher layer memory, and a lower memory having a lower read / write speed is used for a lower layer memory. In the embodiment shown in FIG. 1, the L1 / L2 upper memory layer 10 will be the uppermost memory layer, and the storage device 30 will be the lowest memory layer.

1, the CPU 40 acquires data from the storage device 30 for execution of a program or the like and transfers the acquired data to the L1 / L2 cache memory layer 10 and the main memory Layer 20 as shown in FIG.

The CPU 40 requests the L1 / L2 cache memory layer 10 for data necessary for performing a data read or write operation, that is, requests a memory reference, If there is no L1 / L2 cache memory layer 10, a cache miss may occur.

If a cache miss occurs, the main memory layer 20 is again requested to process a read reference or write reference for the data where the reference failure occurred.

According to the conventional technique, when a reference failure occurs in an upper memory layer, for example, an L1 / L2 cache memory layer, a read reference or a write reference is performed to an intermediate memory layer lower than the upper memory layer , The upper memory layer and the intermediate memory layer are both constituted by volatile memories.

Volatile memory and non-volatile memory have different characteristics in density, read and write speed, and power consumption. In general, volatile memory has faster read and write speed than non-volatile memory. Non-volatile memory has higher density than volatile memory. Is high.

Recently, as the development of nonvolatile memory has progressed actively, the access speed of nonvolatile memory is gradually improving. For example, recent nonvolatile memories such as MRAM (Magnetic Random Access Memory), PRAM (Phase-change memory) and FRAM (Ferroelectric Random Access Memory) And it has similar performance to the conventional volatile memory in reading performance.

However, nonvolatile memory has disadvantages in terms of write speed compared to volatile memory. However, it proposes a new memory system that maximizes the advantages of nonvolatile memory such as density and static power consumption. We want to improve the characteristics.

Korean Patent Laid-Open Publication No. 2011-0037092 discloses a hybrid memory structure having a control interface for a RAM memory and a flash memory, have.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory system and a method for managing the memory system of a new structure including a volatile memory and a nonvolatile memory as a main memory .

According to a first aspect of the present invention, there is provided a memory system including a plurality of layers of memory, the memory system including an upper memory layer, a lower memory layer disposed below the upper memory layer, And a memory management unit for controlling operations of the upper memory layer and the intermediate memory layer, wherein the intermediate memory layer includes a first sub-memory and a second sub- Wherein the memory management unit refers to data corresponding to a predetermined condition among data stored in the second sub-memory during a normal mode operation of a user terminal including the memory system, Pre-stored in the sub-memory.

According to a second aspect of the present invention, a memory system includes a plurality of hierarchical memories and includes an upper memory layer, a first sub-memory disposed below the upper memory layer and made of a non-volatile memory, and a volatile memory The data stored in the second sub-memory is transferred to the first sub-memory based on the intermediate memory layer including the second sub-memory in a parallel structure and the time elapsed since the most recent reference occurred among the data stored in the upper memory layer Wherein the memory management unit transfers the data to the first sub memory when the time elapsed since the most recent reference has elapsed exceeds a threshold value.

According to a third aspect of the present invention, a memory system used by a memory management method includes an upper memory layer and an intermediate memory layer, wherein the intermediate memory layer is disposed under the upper memory layer, And a second sub-memory composed of a first sub-memory and a volatile memory in a parallel structure, wherein (a) data corresponding to a predetermined condition among data stored in the second sub-memory is stored in the first sub-memory (B) storing the remaining data stored in the second sub-memory in the first sub-memory according to an operation state of the user terminal including the memory system; and (c) if the storage of the remaining data is completed, And stopping the driving of the second sub-memory.

According to the above-mentioned problem solving means of the present invention, a new type of memory system including a volatile memory and a non-volatile memory as a parallel structure preliminarily stores a part of data stored in the volatile memory in a nonvolatile memory, The driving of the volatile memory can be selectively stopped according to the operation state. Therefore, the power consumption due to the refresh operation of the volatile memory can be minimized, and the problem of heat generation of the user terminal can also be solved.

1 is a diagram illustrating a memory hierarchical structure applied to a memory system according to a conventional technique.
FIG. 2 is a diagram illustrating a memory system according to an embodiment of the present invention.
3 is a block diagram illustrating a memory management unit according to an embodiment of the present invention.
4A and 4B are diagrams for explaining a data transfer method of the memory management unit according to an embodiment of the present invention.
5 is a diagram for explaining a data transfer method of the memory management unit according to an embodiment of the present invention.
6 is a flowchart illustrating a memory management method according to an embodiment of the present invention.
7 is a diagram illustrating a memory system according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

2 shows a memory system according to an embodiment of the present invention.

The memory system 100 includes an upper memory layer 110, an intermediate memory layer 120, a storage layer 130, and a memory management unit 140, and is connected to the CPU 200.

The central processing unit (CPU) 200 refers to data stored in the storage layer 130, which is the lowest layer, for execution of a specific program, through the intermediate memory layer 120 in the middle layer. Data referenced by the CPU 200 is stored in the upper memory layer 110 and the intermediate memory layer 120 through this process.

The CPU 200 can quickly process a read or write operation using the data stored in the upper memory layer 110 having a faster read / write speed.

The upper memory layer 110 may include a register, an L1 cache, an L2 cache, or the like, and may be constituted by a volatile memory such as SRAM or DRAM. The upper memory layer 110 receives a request for specific data for reading or writing from the CPU 200 and searches for the requested data and stores the requested data in the upper memory layer 110 .

The upper memory layer 110 stores the data for the requested read operation or the write operation in the intermediate memory layer 110. When the data for the requested read operation or the write operation does not exist in the memory of the upper memory layer 110, (120) requesting data in which a reference failure occurs. That is, when a reference failure occurs, the upper memory layer 110 requests data in which the reference failure occurs in the first sub memory 122 and the second sub memory 124 of the intermediate memory layer 120.

The intermediate memory layer 120 is a memory layer having a lower read / write speed performance than the upper memory layer 110. But may have a higher degree of integration than the upper memory layer 110.

When the requested data exists in the first sub-memory 122 or the second sub-memory 124 included in the intermediate memory layer 120, the upper memory layer 110 transfers the data to the first sub-memory 122 or the second sub- From the second sub-memory (124).

The intermediate memory layer 120 includes a first sub-memory 122 and a second sub-memory 124. The first sub-memory 122 and the second sub-memory 124 may be included in the intermediate memory layer 120 in a parallel structure.

In one embodiment of the present invention, the first sub-memory 122 may include one or more non-volatile memory. Preferably, one or more of the MRAM, PRAM, and FRAM memory may be used as the first sub-memory 122. In addition, a plurality of nonvolatile memories of different kinds can be included. At this time, when a plurality of types of nonvolatile memories different from each other are included, the physical location can be determined so that the nonvolatile memory having the fastest memory access speed is located on the upper memory layer 110 side. That is, even within the first sub-memory 122, a hierarchical structure can be used based on the memory access speed.

On the other hand, the second sub-memory 124 includes SRAM or DRAM having a higher read / write speed performance than the first sub-memory 122. At this time, a plurality of types of volatile memories different from each other can be included. In this case, the physical location can be determined so that the volatile memory having the fastest memory access speed is located on the upper memory layer 110 side. That is, even within the second sub-memory 124, a hierarchical structure can be used based on the memory access speed.

As such, the first sub-memory 122 may be configured with low-cost memories having lower read / write speed performance than the second sub-memory 124. [ Non-volatile memory has lower read / write performance than volatile memory. In particular, the difference in read speed between nonvolatile memory and volatile memory is not large, but the difference in write speed between nonvolatile memory and volatile memory is very large. That is, the read speed of the nonvolatile memory is relatively good compared to the write speed. Since the read speed of a memory is generally faster than the write speed, the difference between the read speed and the write speed of the nonvolatile memory is larger than the difference between the read speed and the write speed of the volatile memory.

Thus, if the first sub-memory 122 is configured as a non-volatile memory, the difference between the read speed and the write speed may be greater than the difference between the read speed and the write speed of the second sub-memory 124 comprised of volatile memory. That is, the difference in the writing speed between the first sub-memory 122 and the second sub-memory 124 is larger than the difference between the read speeds of the first sub-memory 122 and the second sub-memory 124.

When a reference failure occurs in the upper memory layer 110, data in which a reference failure occurs is loaded from the first sub memory 122 and the second sub memory 124 included in the intermediate memory hierarchy 120. If there is no corresponding data in the intermediate memory hierarchy 120, the data in which the reference failure occurs is loaded from the storage hierarchy 130.

The storage layer 130 stores all data for the execution of the program. The storage layer 130 is composed of a nonvolatile memory, and may be configured as a flash memory or a hard disk drive.

The storage layer 130 provides the requested data to the CPU 200 through the intermediate memory layer 120 and the upper memory layer 110 at the request of the CPU 200. [

Meanwhile, the second sub-memory 124 may load data from the storage layer 130 and provide the data to the upper memory layer 110 when loading the initial data. The data initially provided to the upper memory layer 110 constituted of the storage device layer 130 and the volatile memory is first transferred to the upper memory layer (not shown) through the second sub memory 124 configured as volatile memory, 110). Thereafter, when a memory reference failure occurs in the upper memory layer 110, the upper memory layer 110 requests all of the corresponding data to the first sub memory 122 and the second sub memory 124, The sub-memory 122 and the second sub-memory 124 can receive the corresponding data.

The memory management unit 140 is connected to the cache memory layer 110, the intermediate memory layer 120, or the storage device layer 130 to control whether data stored in each memory layer is transferred. Particularly, in the present invention, data having low probability of being referred to again among the data stored in the second sub-memory 124 is transferred to the first sub-memory 122 in advance. According to this operation, in stopping the operation of the second sub memory 124 according to a specific condition, the time and effort required to transfer the data stored in the second sub memory 124 to the first sub memory 122 Can be minimized.

3 is a block diagram illustrating a memory management unit according to an embodiment of the present invention.

The memory management unit 140 may include an access time management unit 142, a data transfer control unit 144, and a data information management unit 146. [

Prior to the description of each component, the type of data managed by the memory management unit 140 will be described. The data stored in the second sub-memory 124 can be largely divided into dirty data and clean data. Generally, when writing new data in the cache memory via the CPU, the same data is recorded in the main memory such as the RAM as well as the cache memory so that the data are consistent. However, it is divided into a write through method and a write back method depending on whether data is simultaneously recorded or not. The write-through method is a method of writing data to the cache memory and the RAM at the same time. The write-back method is a method of writing data only to the cache memory and writing the data to the RAM when the corresponding data of the cache memory is replaced later. That is, according to the light-through method, the write operation is performed for the main memory, which is slower than the cache memory, and the write back method is mainly used to solve the drawback that the overall operation speed is slowed down. However, according to the write-back method, it is necessary to distinguish whether the state of the main memory is the same as the data of the cache memory, or whether it is necessary to update the data in the relationship with the cache memory in the future.

At this time, if the data in the cache memory and the data stored in the RAM are the same, the data is referred to as clean data (hereinafter referred to as "clean data"). In addition, if the data of the cache memory is modified but the data of the RAM is not updated, the data is referred to as dirty data (hereinafter referred to as dirty data). In a normal case, a flag or a dirty bit is configured to indicate whether or not each data is dirty. That is, in relation to the cache memory as the upper memory and the RAM as the lower memory, the dirty bit is used to indicate that the value stored in the cache memory is changed with reference to the RAM, and the data block of the cache memory in which the dirty bit is activated is stored in the RAM The value of the cache memory is written into the RAM in the future when the value of the cache memory is replaced.

 When the data stored in the second sub memory 124 is to be transferred to the first sub memory 122 for stopping the driving of the second sub memory 124 as in the present invention, And the data of the second sub-memory are made to coincide with each other, so that a considerable amount of time can be consumed. Therefore, the data stored in the second sub-memory 124 is transferred to the first sub-memory 122 in advance for data having a low probability of occurrence of a re-access event.

To this end, the access time management unit 142 manages information on access times of the cache memory layer 110 with respect to data stored in the first sub memory 122 or the second sub memory 124, for each data. Then, it is determined whether or not the data is transferred based on the access time information for each data.

The data transfer control unit 144 identifies data having a low probability of occurrence of a re-access event and transfers the data to the first sub-memory 122. [ At this time, the re-access event may include both a read event or a write event to the memory.

The data information management unit 146 manages various states of data stored in the first sub memory 122 or the second sub memory 124, address information, and address conversion information according to data transfer. Accordingly, when there is an access request to the intermediate memory layer 120 or the storage device layer 130 by the upper memory layer 110, the data corresponding to the request is transmitted to the upper memory layer 110.

Now, a specific conveying method will be described with reference to the drawings.

4A and 4B are diagrams for explaining a data transfer method of the memory management unit according to an embodiment of the present invention.

First, referring to FIG. 4A, the memory management unit 130 periodically examines the elapsed time after the dirty data becomes a dirty state. If the time exceeds the preset threshold value, (d2) to the first sub-memory (122). That is, if there is no access to the data for a predetermined period of time, it is determined that no additional access to the data occurs, and the corresponding data is transferred to the first sub-memory 122.

Next, referring to FIG. 4B, when a data replacement event occurs in which the dirty data is replaced with the replacement candidate block, the memory management unit 130 determines whether the dirty data has elapsed from the dirty state until the data replacement event occurs If the time exceeds the preset threshold value, the dirty data is transferred to the first sub-memory 122. For example, assuming that there is data d2 of the associated second sub-memory 124 with respect to data A2 of the upper memory hierarchy 110, the other data d3 of the second sub- The data A2 of the upper memory layer 110 may be replaced. At this time, the dirty data d2 may be data update based on the data A2. If a considerable time has elapsed before the occurrence of the data replacement event after the dirty state has been established, it is determined that there is no access to the data in the future, and the corresponding data is transferred to the first sub-memory 122.

In the case of the prior method of examining the elapsed time period after the periodic dirty state, the process is performed periodically, and thus may not be suitable for optimization. Accordingly, only when a data replacement event occurs in the cache memory associated with the dirty data, the elapsed time is compared with the threshold value.

Meanwhile, although the method of transferring dirty data has been described in the foregoing, it is possible to transfer selected dirty data or clean data according to a general cache block replacement policy.

That is, when the elapsed time after the dirty data stored in the second sub-memory 124 becomes dirty is smaller than the threshold value or the number of dirty data stored in the second sub-memory 124 is smaller than the preset threshold value And selects any one of the clean data and transfers it to the first sub-memory 122. When there is a plurality of pieces of clean data, the clean data having the oldest access time from the upper memory layer 110 among the clean data can be transferred.

When the data most recently accessed from the upper memory layer 110 among the data stored in the second sub memory 124 is dirty data, the clean data stored in the second sub memory 110 is stored in the first sub memory 122, respectively.

In the present invention, data to be transferred to the first sub-memory 122 may be bundled and transferred at once.

5 is a diagram for explaining a data transfer method of the memory management unit according to an embodiment of the present invention.

As shown in the figure, data determined to be transferred is stored in a predetermined area 125 of the second sub memory 124. When the number of data stored in the predetermined area 125 exceeds a threshold value, And transfers it to the sub memory 122. At this time, not only the dirty data but also the clean data can be stored in the predetermined area 125.

On the other hand, the memory management unit 140 can perform memory management in a different manner when operating in a light-through manner. That is, since there is no concept of dirty data and clean data in the light-through system, a space in which the data is stored based on the elapsed time since the most recent reference to the data stored in the upper memory layer 110 1 sub-memory 122 and the second sub-memory 124, as shown in FIG.

That is, a period of time that has elapsed after the most recent reference to data stored in the upper memory layer 110 is periodically checked. If the time exceeds the threshold, the second sub-memory 124 associated with the data, To the first sub-memory (122). That is, it is stored in the first sub-memory 122 that the re-access event does not occur as the data at the time when the most recent reference to each data occurs is older.

6 is a flowchart illustrating a memory management method according to an embodiment of the present invention.

First, data corresponding to a predetermined condition among the data stored in the second sub memory 124 is transferred to the first sub memory 122 (S610).

For example, as described with reference to FIGS. 4A and 4B, when the time elapsed after the dirty data becomes dirty exceeds the threshold value or after the dirty state is established based on the data replacement event occurrence time, If the time elapsed until the occurrence of the replacement event exceeds the threshold value, it is determined that the probability of occurrence of the re-access event for the dirty data is low, and the corresponding dirty data is transferred to the first sub-memory 122.

In some cases, clean data may be transferred instead of dirty data. That is, when the time that has elapsed after the dirty data becomes dirty state is smaller than the threshold value, the number of dirty data is not large, or the access to the dirty data among the various data has been most recently occurred, 1 < / RTI >

Next, the residual data stored in the second sub-memory 124 is transferred to the first sub-memory 122 according to the operation state of the user terminal including the memory system 100. For example, when the user terminal enters the idle mode according to the operation condition of the user terminal or the user's request, all the remaining data stored in the second sub memory 124 is transferred to the first sub memory 122 . At this time, the remaining data may include dirty data or clean data.

This is because the data stored in the second sub memory 124 is transferred to the first sub memory 122 before the second sub memory 124 is stopped to prevent the cache miss state from occurring.

At this time, not only the idle mode but also the temperature state of the user terminal can be sensed and the transport operation can be performed accordingly. For example, when the temperature sensed by the temperature sensor exceeds a threshold value in a state where the temperature sensor is already provided on the user terminal side, the driving of the second sub memory 124 is stopped and the memory system 100 ) Is minimized. On the other hand, the temperature sensor may be optionally included in the user terminal side and may be included in the memory system 100 as the case may be.

Next, when the transfer of the data stored in the second sub-memory 124 is completed, the driving of the second sub-memory 124 is stopped through the memory management unit 140 (S630). With this configuration, it is possible to selectively stop the driving of the second sub-memory 124 according to the operation state of the user terminal. If the second sub-memory 124 is constituted by a DRAM or the like, it is a memory requiring a periodic refresh operation in order to store data. If the second sub-memory 124 can temporarily suspend the operation according to the operation state, the power consumed by the refresh operation, . In addition, the problem of heat generation caused by the refresh operation can be solved. In addition, by using the first sub-memory 122 that stops the operation of the second sub-memory 124 and has a relatively low read / write performance, the memory reference delay time is increased to lower the operation performance of the CPU The power consumption consumed by the CPU is reduced, so that the heat generation problem can be solved.

7 is a diagram illustrating a memory system according to another embodiment of the present invention.

The memory system 700 includes an upper memory layer 710, an intermediate memory layer 720, a storage layer 730, and a memory management unit 740.

Compared to the embodiment of FIG. 2, the configuration of the intermediate memory hierarchy 720 is somewhat different. For example, the upper memory layer 710 corresponds to the L1 cache, and the first non-volatile memory 723 and the first volatile memory 725 of the first sub-memory 722 and the second sub- L2 / L3 cache. As described above, part of the cache memory can also include a nonvolatile memory and a volatile memory having different characteristics in a parallel structure.

The configuration of each sub-memory may be configured similar to that of the intermediate memory hierarchy 120 of FIG. That is, the first sub-memory 722 may use one or more of the MRAM, PRAM, and FRAM as the first non-volatile memory 723 or the second non-volatile memory 724. [

On the other hand, the second sub-memory 726 includes SRAM or DRAM having a faster read / write speed performance than the first sub-memory 722.

As described above, the first sub-memory 722 and the second sub-memory 726 are also configured for the cache memory, and data satisfying predetermined conditions stored in the second sub-memory 726 is stored in the first sub-memory 722, respectively.

In other words, as described with reference to FIGS. 3 to 6, it is possible to perform the operation of previously transferring dirty data or clean data of a predetermined condition among the dirty data in the second sub-memory 726 to the first sub-memory 722 have. With this configuration, it is possible to selectively stop the driving of the second sub-memory 726 according to the operation state of the user terminal. When the second sub-memory 726 is formed of a DRAM or the like, it is necessary to periodically refresh the data to store data. If the second sub-memory 726 can temporarily suspend the driving according to the operation state, the power consumed by the refresh operation is reduced . In addition, the problem of heat generation caused by the refresh operation can be solved.

While the methods and systems of the present invention have been described with reference to particular embodiments, some or all of their components or operations may be implemented using a computer system having a general purpose hardware architecture

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: memory system 110: upper memory layer
120: intermediate memory layer 122: first sub-memory
124: second sub-memory 130: storage device layer
140: memory management unit

Claims (14)

1. A memory system comprising a plurality of layers of memory,
Upper memory layer,
Storage layer,
An intermediate memory layer disposed between the upper memory layer and the storage layer and including a first sub-memory of non-volatile memory and a second sub-memory of volatile memory,
And a memory management unit for controlling operations of the upper memory layer, the intermediate memory layer, and the storage layer,
The intermediate memory layer and the storage layer are referred to by the upper memory layer,
Wherein when the temperature of the user terminal exceeds a threshold value during operation of the user terminal including the memory system, the memory management unit stores the remaining data stored in the volatile memory included in the upper memory layer or the intermediate memory layer, 1 < / RTI > sub-memory, and then stops driving the volatile memory. The method according to claim 1,
Wherein the first sub-memory includes a first non-volatile memory that operates as a cache memory and a second non-volatile memory that operates as a main memory,
Wherein the second sub-memory comprises a first volatile memory acting as a cache memory and a second volatile memory acting as a main memory. The method according to claim 1,
The memory management unit includes:
Storing the remaining data stored in the second sub-memory in the first sub-memory and then stopping driving the second sub-memory if the temperature of the user terminal exceeds a threshold value. The method according to claim 1,
The memory management unit includes:
And stores the dirty data in the first sub-memory in advance when the elapsed time since the dirty data is exceeded exceeds a preset threshold value. The method according to claim 1,
The memory management unit includes:
And when the data replacement event occurs in the second sub-memory, dirty data is preferentially stored in the first sub-memory. The method according to claim 1,
The memory management unit includes:
And stores the clean data stored in the second sub-memory in the first sub-memory if the most recently accessed data from the upper memory layer is dirty data. 7. The method according to any one of claims 1 to 6,
The memory management unit includes:
Storing data corresponding to a predetermined condition among data stored in the second sub-memory in a predetermined area of the second sub-memory, and if the number of data stored in the predetermined area exceeds a threshold value, In a first sub-memory. The method according to claim 1,
The memory management unit includes:
Storing the remaining data stored in the second sub-memory in the first sub-memory according to the entry of the user terminal in the idle mode, and then stopping the driving of the second sub-memory. The method according to claim 1,
Wherein the first sub-memory comprises one or more of an MRAM, a PRAM, and a FRAM. A memory system for controlling operations of a plurality of hierarchical memories,
Wherein the memory system controls operation of an upper memory layer and an intermediate memory layer,
The intermediate memory layer is referred to by the upper memory layer. The intermediate memory layer includes a first sub-memory disposed below the upper memory layer and made of a non-volatile memory and a second sub-memory comprised of a volatile memory.
Wherein the memory system stores the remaining data stored in the second sub-memory in the first sub-memory when the temperature of the user terminal exceeds a threshold value during a normal mode operation of the user terminal including the memory system, And stops the driving of the second sub-memory. delete Wherein the intermediate memory layer comprises a first sub-memory comprised of a non-volatile memory and a second sub-memory comprised of a volatile memory disposed between the upper memory layer and the storage device layer, 1. A memory management method for a memory system including a memory,
(a) storing, in the first sub-memory, data corresponding to a predetermined condition among data stored in the second sub-memory;
(b) storing the remaining data stored in the second sub-memory in the first sub-memory if the temperature of the user terminal including the memory system exceeds a threshold value; And
(c) stopping the driving of the second sub-memory when the storage of the remaining data is completed. 13. The method of claim 12,
The step (b)
Sensing a temperature of the user terminal;
Storing the remaining data stored in the second sub-memory in the first sub-memory if the temperature of the user terminal exceeds a threshold value. 13. The method of claim 12,
The step (b)
And stores the remaining data stored in the second sub-memory in the first sub-memory in accordance with the entry of the user terminal into the dormant mode.

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