KR101483533B1 - Non-volatile memroy device and method for the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same, which are characterized by stacking conductive films and insulating films alternately on a substrate and electrically connecting the active columns electrically connected to the substrate through the conductive films and insulating films, The size of the upper and lower ends of the active pillars is minimized to improve the cell scattering characteristics.

Semiconductor, non-volatile memory, NAND flash, active bar,

Description

[0001] NON-VOLATILE MEMORY DEVICE AND METHOD FOR THE SAME [0002]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.

It is required to increase the degree of integration of semiconductor memory devices in order to satisfy excellent performance and low price required by consumers. Since the degree of integration of the semiconductor memory device is an important factor in determining the price of the product, an increased degree of integration is required in particular. In the case of a conventional two-dimensional or planar semiconductor memory device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional semiconductor memory device is increasing, but it is still limited, because it requires expensive equipment to miniaturize the pattern.

As an alternative to overcome these limitations, there has been proposed a technique for three-dimensionally forming memory cells, for example, "Nonvolatile semiconductor memory device and manufacturing method thereof" of U.S. Patent Application Publication 2007/0252201 proposed by Kito et al. According to this technique, vertical semiconductor pillars are used as active regions and memory cells are formed in three dimensions. Such an integrated circuit can efficiently utilize the area of the semiconductor substrate, and as a result, the degree of integration can be greatly increased as compared with the conventional two-dimensional memory semiconductor memory device. Furthermore, this technique is not based on a method of repeating the step of two-dimensionally forming memory cells, but because the word lines are formed by using a patterning process for defining an active region, manufacturing cost per bit can be greatly reduced have.

An object of the present invention is to provide a nonvolatile memory device in which electrical characteristics can be improved and a manufacturing method thereof.

In order to achieve the above object, a nonvolatile memory device and a method of manufacturing the same according to the present invention are characterized in that a width of an active column used as a channel of a transistor is minimized.

According to another aspect of the present invention, there is provided a method for fabricating a nonvolatile memory device, comprising: stacking conductive films and insulating films alternately on a substrate; And forming active pillars that are electrically connected to the substrate through the conductive films and the insulating films by dividing the active pillars at least twice.

In the method of this embodiment, laminating the conductive films may include forming a first gate on the substrate and then forming a first opening through the first gate; Forming a plurality of second gates vertically stacked on the first gate, forming a second opening vertically connected to the first opening through the plurality of second gates; And forming a third gate on the plurality of second gates and then forming a third opening through the third gate and perpendicular to the second opening.

In the method of this embodiment, forming the active column may include forming a first active column that fills the first opening and is perpendicular to the substrate; Forming a second active pillar filling the second opening and vertically connected to the first active pillar; And forming a third active column that fills the third opening and is perpendicular to the second active column.

In the method of this embodiment, forming the active column may include forming a first gate insulating film on the sidewall of the first opening; Forming a second gate insulating film including a charge storage film on a side wall of the second opening; And forming a third gate insulating film on the sidewall of the third opening.

A method for fabricating a nonvolatile memory device according to an alternative embodiment of the present invention that can implement the above feature includes a lower select gate on a substrate and a first active column vertically extending from the substrate through the lower select gate To form a first structure; Forming a second structure including a plurality of first control gates stacked on the first structure and a second active column extending vertically from the first active column through the plurality of first control gates; And forming a third structure on the second structure including an upper select gate and a third active column vertically extending from the second active column through the upper select gate.

The method of the present alternate embodiment may further comprise: a plurality of second control gates stacked on the second structure prior to forming the third structure; And forming a fourth structure including an extended fourth active column.

In the method of this modified embodiment, it may further comprise forming a bit line electrically connected to the third active column on the third structure.

In the method of this modified embodiment, one of the upper and lower selection gates is formed in a plate shape and the other is formed in a plurality of line shapes; The plurality of control gates may be formed in a plate shape.

A nonvolatile memory device according to an embodiment of the present invention capable of realizing the above features includes a plurality of vertically stacked gates on a semiconductor substrate; Active pillars extending vertically from the semiconductor substrate through the plurality of gates; And a gate insulating film disposed between the active pillars and the plurality of gates, wherein the active pillars comprise a plurality of pillars vertically connected to the same material as the semiconductor substrate, And may include inclined columns with a smaller cross-sectional area.

In the element of this embodiment, the active column may further include an insulator therein.

According to the present invention, a plurality of active pillars having a height enough to ignore the degree of cell scattering can be neglected, so that a large number of conducting films and insulating films can be stacked to increase the degree of integration, . As a result, the electrical characteristics of the nonvolatile memory element can be improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages of the present invention and its advantages over the prior art will become apparent from the detailed description and claims that follow. In particular, the invention is well pointed out and distinctly claimed in the claims. The invention, however, may best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. Like reference numerals in the drawings denote like elements throughout the various views.

(Device Embodiment)

1 is a perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention.

1, the nonvolatile memory device 1 of the embodiment of the present invention may include a cell area 2 including memory cells and a peripheral area 3 including peripheral circuits for operating memory cells . The configuration of the nonvolatile memory device 1 of the embodiment of the present invention described below is an example of the present invention, and the present invention is not limited thereto, and various modifications are possible. As an example of a modified example, it may be that disclosed in U.S. Published Patent Application 2007/0252201, which is incorporated herein by reference.

The cell region 2 includes a plurality of plate-shaped control gates 27 vertically stacked in the Z direction on the semiconductor substrate 20 and forming an XY plane, a plurality of control gates 27 formed on upper and lower portions of the plurality of control gates 27 A plurality of bit lines 21 stacked on the upper select gate 25 and extending in the Y direction and a plurality of active columns 22 extending vertically in the Z direction on the semiconductor substrate 20, (29: active pillar or active bar). Each of the active pillars 29 may be provided to extend from the semiconductor substrate 20 to the bit line 21 and penetrate the upper and lower selection gates 23 and 25 and the control gate 27. The semiconductor substrate 20 may be a P-type silicon substrate, and the active pillar 29 may be formed on the N + region formed in the P-well region. As another example, an N + region may not be formed between the semiconductor substrate 29 and the active pillar 29.

Either the lower select gate 23 or the upper select gate 25 may be provided in the form of a plate forming the X-Y plane and the other may be provided in the form of a separate line extending in the X direction. As another example, each of the lower selection gate 23 and the upper selection gate 25 may be provided in the form of a separate line extended in the X direction. In this embodiment, the lower selection gate 23 is a plate-like structure having an X-Y plane, and the upper selection gate 25 is a separation line type extending in the X direction.

The peripheral region 3 includes an upper select line driving circuit 32 connected to the plurality of upper select gates 25, a word line driving circuit 34 connected to the plurality of control gates 27, And a common source line 36 connected to the source 20a. The source 20a may be of a conductive type different from that of the semiconductor substrate 20. For example, when the semiconductor substrate 20 is a P conductive type, the source 20a may be N conductive type.

FIG. 2 is a perspective view showing a cell region of FIG. 1, and FIGS. 3a and 3b are perspective views showing the memory transistor of FIG.

2 and 3a, active pillars 29 and control gates 27 define memory transistors 28 and active pillars 29 and lower selection gates 23 define a lower selection transistor 24 And active column 29 and top select gate 25 may define top select transistor 26. [ The nonvolatile memory device of the present invention is a nonvolatile memory device in which a plurality of memory transistors 28 formed in one active column 29 and upper and lower transistors 26 and 24 are connected in series to form one cell string 22, Flash (NAND Flash) memory device. One cell string 22 in this embodiment has four memory transistors 28. The number of memory transistors 28 of one cell string 22 is not limited to this, May be changed to the number of < / RTI > The active column 29 may have a columnar shape with a circular cross section or a columnar shape with a rectangular cross-section such as a square column shape.

The memory transistor 28 and the upper and lower selection transistors 26 and 24 may be provided with a so-called depletion transistor in which no source / drain is present in the active column 29. As another example, the memory transistor 28 and the upper and lower selection transistors 26 and 24 may be provided as so-called enhancement transistors in which the source / drain is present in the active column 29.

The plurality of active pillars 29 have a Z-axis extending through the plurality of control gates 27 so that the intersections between the plurality of control gates 27 and the plurality of active pillars 29 are three-dimensionally distributed . The memory transistors 28 of the nonvolatile memory element of the present embodiment can be formed at each of these three dimensionally distributed intersections. A gate insulating film 30 including a charge storage film may be disposed between the plurality of active pillars 29 and the plurality of control gates 27.

The charge storage film may include an insulating film capable of trapping charges. For example, when the gate insulating film 30 is a so-called ONO film in which a silicon oxide film, a silicon nitride film (or a silicon oxynitride film) and a silicon oxide film are laminated, the charge can be trapped in the silicon nitride film (or silicon oxynitride film) have. As another example, the charge storage film may comprise a floating gate composed of a conductor.

Referring to FIG. 3B, the active pillars 29 may be in the form of a so-called macaroni having an insulator 32 therein. The insulator 32 may be columnar. Since the insulator 32 occupies the inside of the active pillar 29, the active pillar 29 can have a thinner thickness than the structure of Fig. 3A, which can reduce the deviation of the threshold voltage.

4 is an equivalent circuit diagram showing a part of a nonvolatile memory device according to an embodiment of the present invention.

2 to 4, in the nonvolatile memory element 1 of the embodiment of the present invention, the plurality of control gates 27 are used as a plurality of word lines WL1 to WL4, and the plurality of upper select gates 25 Is used as a plurality of upper select lines USL1 to USL3, and the lower select gate 23 is used as a lower select line (LSL). A plurality of cell strings 22 may be connected to each of the plurality of bit lines BL1 to BL3.

Each of the plurality of control gates 27 can be a two-dimensionally spread flat structure, so that each of the plurality of word lines WL1 to WL4 has a planar structure and can be substantially perpendicular to the cell string 22 . A plurality of memory transistors 28 may be three-dimensionally distributed on the plurality of word lines WL1 to WL4.

The upper select gate 25 can have a separate wiring structure extending in the X direction so that the plurality of upper select lines USL1 to USL3 can be arranged to cross the plurality of bit lines BL1 to BL3. Each of the plurality of upper select lines USL1 to USL3 is electrically connected to each of the plurality of bit lines BL1 to BL3 so that one cell string 22 can be independently selected.

The lower select gate LSL may have a planar structure and may be substantially perpendicular to the cell string 22 since the lower select gate 23 may have a planar flat structure spreading in two dimensions. The lower select line (LSL) can control the electrical connection between the active column (29) and the semiconductor substrate (20).

In the nonvolatile memory element 1 of the embodiment of the present invention, the programming operation can be realized by setting a voltage difference between the selected word line WL and the active column 29 to inject the charge into the charge storage film. For example, by applying the program voltage Vprog to the selected word line WL, the charge of the memory transistor 28 belonging to the word line WL to be programmed from the active column 29, using the Fowler-Nordheim tunneling phenomenon, The program can be implemented by injecting electrons into the storage film. The program voltage applied to the selected word line WL can program the memory transistor belonging to the unselected word line, so that the unintentional program can be prevented using the boosting technique.

The read operation sets the read voltage Vread to, for example, O volts and sets the read voltage Vread to the word line WL to which the memory transistor 28 to be read is connected. As a result, it is determined whether the bit line BL is charged with current depending on whether the write voltage Vth of the memory transistor 28 to be read is greater than or less than 0 volts, The data information of the memory transistor 28 to be read can be read.

The erase operation can be performed block by block using the so-called " gate induced drain leakage current (GIDL) ". For example, the potential of the active column 29 is raised by applying an erase voltage (Verase) to the selected bit line BL and the substrate 20. At this time, the potential of the active column 29 can be raised with a slight delay. Accordingly, GIDL is generated at the terminal of the lower selection gate 24, electrons generated by the GIDL are emitted to the substrate 20, and the generated holes are emitted to the active pillar 29. This allows a potential near the erase voltage (Verase) to be transferred to the channel of the memory transistor 28, that is, to the active column 29. At this time, if the potential of the word line WL is set to 0 volts, the electrons accumulated in the memory transistor 28 are released and data erasing can be realized. On the other hand, the word line of the unselected block can be floated so that an unintended erase operation is not performed.

The operation method of the nonvolatile memory device 1 according to the embodiment of the present invention is for illustrating the technical idea of the present invention by way of example, and the technical features of the present invention are not limited thereto. Thus, it would be obvious to those skilled in the art to implement such variations based on known techniques, so that the technical features of the present invention in connection with the method of operation are based on known techniques And can be variously modified. By way of example, the operation of the non-volatile memory element 1 can be implemented by the method disclosed in U.S. Patent Publication No. 2007/0252201, which is incorporated herein by reference.

(Method embodiment)

5A to 5P are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 5A, an insulating layer 110, a conductive layer 120, and an insulating layer 130 are sequentially formed on a semiconductor substrate 100. The semiconductor substrate 100 may be formed of a semiconductor having a single-crystal structure of a first conductivity type, for example, a P-type silicon wafer. The semiconductor substrate 100 may have an electrically isolated region, i.e., a well region, by impurity regions of different conductivity types. The well region may be formed in a pocket well or a triple well structure. The insulating films 110 and 130 may be formed by depositing an insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The conductive film 120 may be used as a lower selection gate. A conductive film 120 (hereinafter, a lower selection gate) may be formed by depositing a conductive material, such as doped polycrystalline silicon or metal, so that it can be used as a gate.

Referring to FIG. 5B, at least one first opening 102 exposing the semiconductor substrate 100 is formed, for example, by a photo and etching process. The first opening 102 may have a circular cross section or a polygonal shape (e.g., a quadrangle). The first opening 102 is filled with silicon to form active pillars, which are used as channels of the transistor, as described later. If the sidewall 102a of the first opening 102 is formed to be inclined, the size of the active column may vary according to the height, and the channel width of the transistor may be varied. The unevenness of the channel width may be an obstacle to realizing uniform electrical characteristics of the semiconductor memory device. Therefore, it is preferable that the first opening 102 is formed using an anisotropic etching technique, for example, a dry etching technique so as to have a vertical side wall 102a.

Referring to FIG. 5C, an insulating film 104 is formed on the side wall 102a of the first opening 102. As shown in FIG. The insulating film 104 may be used as a gate insulating film of the lower select gate 120 (hereinafter referred to as a first gate insulating film). The first gate insulating film 104 may be formed by depositing a silicon oxide film, for example. A silicon oxide film may be deposited on the semiconductor substrate 100 exposed by the first opening 102 in a deposition process for forming the first gate insulating film 104. [ Since the semiconductor substrate 100 and the active pillars described later are electrically connected to each other, the silicon oxide film deposited on the semiconductor substrate 100 is preferably removed by an etching technique. In this case, when the silicon oxide film deposited on the semiconductor substrate 100 is etched, a spacer may be further formed to protect the silicon oxide film deposited on the side wall 102a of the first opening 102 from etching.

Referring to FIG. 5D, a first active column 106 filling the first opening 102 is formed. The first active pillars 106 may be formed of the same material as the semiconductor substrate 100. In one example, a silicon film may be deposited and planarized using a chemical mechanical polishing (CMP) technique to form the first active pillar 106. The silicon film for forming the first active pillars 106 may be formed by depositing polycrystalline or amorphous silicon. As another example, the first active pillar 106 may be grown from the semiconductor substrate 100 exposed by the first opening 102 using epitaxial techniques. In this case, the semiconductor substrate 100 and the first active pillar 106 may be a single-crystal structure silicon continuously connected without crystal defects. The first active pillar 106 may be formed to have the same conductivity type as that of the semiconductor substrate 100. For example, the semiconductor substrate 100 and the first active column 106 may be P-type. As a result, since no diode is formed between the first active pillars 106 and the semiconductor substrate 100, the first active pillars 106 and the semiconductor substrate 100 can have the same potential.

A first structure 101 including a lower selective gate 120 on the semiconductor substrate 100 and a first active column 106 used as a channel of the lower select gate 120 is formed through the above- Can be implemented.

Referring to FIG. 5E, a first insulating layer group 200a and a first conductive layer group 200b are formed on a first structure 101. The first insulating layer group 200a may include a plurality of insulating layers 210, 230, 250, 270, and 290. The first conductive film group 200b may include a plurality of conductive films 220, 240, 260, and 280. The conductive films 220-280 and the insulating films 210-290 may be alternately arranged to form a so-called sandwich form. The insulating layer 210 may be disposed directly on the first structure 101 and the insulating layer 290 may be formed to cover the conductive layer 280. The plurality of conductive films 220-280 of the first conductive film group 200b may be used as control gates, respectively. To this end, the plurality of conductive films 220-280 may be formed by depositing doped polycrystalline silicon or metal. In this specification, the first conductive film group 200b is used in combination with the first control gate group, and each of the plurality of conductive films 220-280 is used in combination with the first control gate.

Each of the plurality of conductive films 220-280 may be deposited to have the same thickness. Since the thickness of each of the plurality of conductive films 220-280 can determine the channel length, the thickness of the plurality of conductive films 220-280 can be selected within a range that can solve the problem of electrical characteristics according to the short channel. Further, since the plurality of conductive films 220 to 280 can be formed by vapor deposition, the channel length can be precisely controlled.

The plurality of insulating films 210-290 may be formed by depositing a silicon oxide film. As another example, the plurality of insulating films 210-290 may be formed as a high-k film. For example, the plurality of insulating films 210-290 can be formed by depositing a material having a higher dielectric constant (e.g., a silicon nitride film or a silicon oxynitride film) than the silicon oxide film.

The number of the thin films constituting the first insulating film group 200a and the first conductive film group 200b, their respective thicknesses, their respective materials, and the like are determined in accordance with the electrical characteristics of the memory transistors and the process of patterning them The present invention can be variously modified in consideration of the technical difficulties of the present invention. Each of the first insulating film group 200a and the first conductive film group 200b may be formed to have a stepped shape.

Referring to FIG. 5F, a first opening layer 202 is formed by patterning the first insulating layer group 200a and the first conductive layer group 200b by a photo-etching process to expose the first active column 106 . The first gate insulating film 104 may be exposed by the second opening 202. As already mentioned, the second opening 202 may be formed using a dry etch technique, for example, to have a vertical sidewall 202a to achieve uniform electrical characteristics of the transistor. Accordingly, the first opening 102 and the second opening 202 can be vertically connected in a straight line.

The number of the conductive films 220-280 constituting the first conductive film group 200b and the number of the insulating films 210-290 constituting the first insulating film group 200a may be arbitrarily selected. In this embodiment, the number of the conductive films 220-280 constituting the first conductive film group 200b is limited to four, and the number of the insulating films 210-290 constituting the first insulating film group 200a is Although the number is limited to five, the number is arbitrary.

Referring to FIG. 5G, the insulating film 204 is formed on the side wall 202a of the second opening 202. The insulating film 204 can be used as a gate insulating film of the first control gate group 200b (hereinafter referred to as a second gate insulating film). The second gate insulating film 204 may include a charge storage film. For example, the second gate insulating film 204 may be formed in a triple thin film structure by sequentially depositing a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or the like. In the second gate insulating film 204, the silicon nitride film or the silicon oxynitride film is used as a charge storage film for storing information by trapping charges. One of the two silicon oxide films may be used as a blocking insulating film and the other may be used as a tunnel insulating film. have.

The second gate insulating layer may be deposited on the first active pillar 106 exposed by the second opening 202 during the deposition process for forming the second gate insulating layer 204. [ Since the first active pillars 106 and the second active pillars 206 described below are electrically connected to each other, the second gate insulating layer deposited on the first active pillars 106 is preferably removed using an etching technique. In this case, when the second gate insulating film deposited on the first active column 106 is etched, a spacer for protecting the second gate insulating film 204 deposited on the side wall 202a of the second opening 202 from etching .

Referring to FIG. 5H, a similar process as described with reference to FIG. 5D is performed to form a second active column 206 filling the second opening 202. The second active pillars 206 may be vertically connected to the first active pillars 106 in a straight line. The second active pillars 206 may be formed of the same material as the first active pillars 106. For example, an amorphous or polysilicon film may be deposited and planarized using a chemical mechanical polishing (CMP) technique to form the second active pillars 206. As another example, epitaxial techniques may be used to grow monocrystalline silicon from the first active pillar 106 to form a second active pillar 206. The second active pillars 206 may be formed to have the same conductivity type as the semiconductor pillars 100 and the first active pillars 106, for example, P type. Accordingly, the semiconductor substrate 100, the first active pillars 106 and the second active pillars 206 may have the same potential.

A plurality of control gates 220-280 and a second active column 206 used as a channel of the plurality of control gates 220-280 are formed on the first structure 101 through the series of processes The second structure 201 can be realized.

5I, a similar process to that described with reference to FIG. 5E is performed to form a second insulating layer group 300a including a plurality of insulating layers 310, 330, 350, 370, and 390 on a second structure 201 and a plurality of insulating layers 310, 330, 350, A second conductive film group 300b including a plurality of conductive films 320, 340, 360, and 380 alternately disposed. At this time, the insulating layer 310 may be disposed immediately above the second structure 201, and the insulating layer 390 may be disposed at the end to cover the conductive layer 380. The plurality of conductive films 320-380 of the second conductive film group 300b may be used as control gates, respectively. For this, the plurality of conductive films 320-380 may be formed by depositing doped polycrystalline silicon or metal. The plurality of conductive films 320-380 may be formed to have the same thickness. In this specification, the second conductive film group 300b is used in combination with the second control gate group, and each of the plurality of conductive films 320-380 is used in combination with the second control gate. The plurality of insulating films 310-390 can be formed by depositing a silicon nitride film or a silicon oxynitride film having a dielectric constant higher than that of the silicon oxide film or the silicon oxide film. Each of the second insulating film group 300a and the second conductive film group 300b may have a stepped shape.

Referring to FIG. 5J, a third opening (not shown) for exposing the second active pillars 206 is formed by patterning the second insulating layer group 300a and the second conductive layer group 300b by the similar process as described with reference to FIG. 5F 302 are formed. The second gate insulating film 204 may be exposed by the third opening 302. In order to realize uniform transistor electrical characteristics, the third opening 302 is preferably formed using a dry etching technique to have a vertical side wall 302a. Accordingly, the second opening 202 and the third opening 302 can be vertically connected in a straight line.

The third active pillars having a height enough to ignore the extent of cell scattering even if the third openings 302 are formed to be inclined may be formed on the conductive films 320- 380 and the number of the insulating films 310-390 constituting the second insulating film group 300a can be appropriately selected. For example, the second conductive film group 300b may be formed to have the same structure as that of the first conductive film group 200b, and the second insulating film group 300a may be formed to have the same structure as the first insulating film group 200a .

Referring to FIG. 5K, an insulating film 304 is formed on the side wall 302a of the third opening 302 by performing the similar process as described with reference to FIG. 5G. The insulating film 304 can be used as a gate insulating film of the second control gate group 300b (hereinafter referred to as a third gate insulating film). The third gate insulating film 304 may have the same structure as the second gate insulating film 204. For example, the third gate insulating film 304 can be formed as a triple thin film structure by sequentially depositing a silicon oxide film as a blocking insulating film, a silicon nitride film or a silicon oxynitride film as a charge storage film, and a silicon oxide film as a tunnel insulating film in this order.

During the deposition process for forming the third gate insulating layer 304, a third gate insulating layer may be deposited on the second active layer 206 exposed by the third opening 302. Therefore, it is preferable that the third gate insulating film deposited on the second active column 206 is removed using an etching technique. In this case, a spacer may be further formed to protect the third gate insulating film 304 deposited on the side wall 302a of the third opening 302 from etching.

Referring to FIG. 51, a similar process as described with reference to FIG. 5D is performed to form a third active column 306 filling the third opening 302. The third active pillar 306 may be vertically connected to the second active pillar 206 in a straight line. The third active pillars 306 may be formed of the same material as the second active pillars 206. For example, the third active pillar 306 can be formed by depositing an amorphous or polysilicon film and using chemical mechanical polishing (CMP) techniques, or by growing epitaxial silicon using epitaxial techniques. The third active pillar 306 may be formed to have the same conductivity type as the first active pillar 106 and the second active pillar 206, for example, P type. Accordingly, the semiconductor substrate 100, the first active pillars 106, the second active pillars 206, and the third active pillars 306 may have the same potential.

A plurality of control gates 320-380 and a third active column 306 used as a channel of the plurality of control gates 320-380 are formed on the second structure 201 through the above- The third structure 301 may be implemented.

Referring to FIG. 5M, the insulating film 410, the conductive film 420, and the insulating film 430 are sequentially formed on the third structure 301 by performing similar processes as described with reference to FIG. 5A. The insulating films 410 and 430 may be formed by depositing an insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The conductive film 420 may be used as an upper select gate. A conductive layer 420 (hereinafter, an upper select gate) may be formed by depositing a conductive material, such as doped polycrystalline silicon or metal, so that it can be used as a gate.

Referring to Figure 5n, a fourth opening 402 exposing the third active pillars 306 is formed using the same process as described with reference to Figure 5b. The fourth openings 402 may be formed using a dry etching technique so as to have vertical sidewalls 402 as much as possible.

Referring to FIG. 5O, an insulating film 404 is formed on the side wall 402a of the fourth opening 402 using the same process as described with reference to FIG. 5C. The insulating film 404 may be used as a gate insulating film of the upper select gate 420 (hereinafter referred to as a fourth gate insulating film). The fourth gate insulating film 404 may be formed by depositing a silicon oxide film, for example. A silicon oxide film may be deposited on the third active pillar 306 exposed by the fourth opening 402 during the deposition process for forming the fourth gate insulating film 404. Therefore, it is preferable that the silicon oxide film deposited on the third active column 306 is removed using an etching technique. In this case, a spacer may be further formed to protect the silicon oxide film deposited on the sidewall 402a of the fourth opening 402 from etching.

Referring to Fig. 5P, a fourth active pillar 406 filling the fourth opening 402 is formed using the same process as described with reference to Fig. 5D. The fourth active column 406 may be vertically connected to the third active column 306 in a straight line. The fourth active pillars 406 may be formed of the same material as the third active pillars 306. For example, the fourth active pillar 406 can be formed by depositing an amorphous or polysilicon film and using chemical mechanical polishing (CMP) techniques, or by growing monocrystalline silicon using epitaxial techniques. The fourth active column 406 may be formed to have the same conductivity type as the semiconductor substrate 100, for example, a P-type. Accordingly, the semiconductor substrate 100, the first active pillars 106, the second active pillars 206, the third active pillars 306, and the fourth active pillars 406 may have the same potential.

A fourth structure 401 including a top select gate 420 on the third structure 301 and a fourth active column 406 used as a channel of the top select gate 420 is formed through the above- ) May be implemented. The first to fourth active pillars 106 to 406 are connected to the semiconductor substrate 100 and are made of the same material as the semiconductor substrate 100 such as silicon and have the same conductivity type And an active column 506 having an equipotential can be implemented.

Particularly, since the active pillars 506 are divided into the first to fourth active pillars 106 to 406, the widths of the first to fourth active pillars 106 to 406 can be minimized have. Therefore, the width of the active pillars 506 can be set so as not to be large according to the height of the active pillars 506, so that the cell scattering characteristics can be prevented from deteriorating.

A bit line 610 electrically connected to the active pillars 506 may be formed on the fourth structure 401. The bit line 610 may extend in a direction transverse to the upper select gate 420. For example, the bit line 610 may be formed by depositing aluminum on the fourth structure 401 and patterning it by a photo and etch process.

6A and 6B are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to an alternative embodiment of the present invention.

Referring to FIG. 6A, the active pillars 506 may be formed in a so-called macaroni shape shown in FIG. 3B in which an insulator 710 is inserted. The insulator 710 can be formed, for example, by depositing a silicon oxide film. 6B, silicon is deposited on the second opening 202 to form a second active column 206 when the second structure 201 is formed, and the second active column 206 is formed on the second opening 201 202 are not completely filled. For example, when depositing silicon to form a second active column 206, silicon is deposited from the sidewalls of the second opening 202 toward the center of the second opening 202, so that the second active column 206 is hollow hollow < / RTI > Then, the hollow center portion of the second active column 206 is filled with the insulator 710. When this process is repeated in forming the third structure (301 in FIG. 6A), a macaroni-shaped active column (506 in FIG. 6A) can be formed.

7A and 7B are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to another modified example of the present invention.

7A, a gate insulating film 802 serving as a tunnel insulating film and a charge storage film 804 for trapping charges can be formed. The charge storage film 804 can be formed by depositing a silicon nitride film or a silicon oxynitride film when the second structure 201 and the third structure 301 are formed. For example, referring to FIG. 7B, a second gate insulating layer 204 may be formed by depositing the same material as the first gate insulating layer 104, for example, a silicon oxide layer, on the sidewalls of the second opening 202 when the second structure 201 is formed. And the charge storage film 804 can be formed in this order. When this process is repeated in the formation of the third structure (301 in FIG. 7A), a nonvolatile memory device as shown in FIG. 7A can be realized.

8A and 8B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to still another modified embodiment of the present invention.

Referring to FIG. 8A, a nonvolatile memory device can be manufactured using the same process as described with reference to FIGS. 5A to 5P. For example, the insulating film 110, the conductive film 120 (lower selection gate), and the insulating film 130 may be sequentially formed on the semiconductor substrate 100 by a deposition process. The first opening 106 may be formed by a photo-etching process and a first gate insulating film 104 may be formed on a sidewall of the first opening 106 by a deposition process. The first structure 101 may be formed by forming a first active pillar 106 filling the first opening 102 by a deposition and a chemical mechanical polishing process. The first opening 106 may be inclined so that the first active pillar 106 may be formed in an inclined columnar shape. For example, the first active pillars 106 may be tapered so that their cross-sectional area decreases from the top to the bottom.

A first insulating film group 200a composed of a plurality of insulating films 210-290 and a first conductive film group 200b composed of a plurality of conductive films 220-280 (control gates) are formed on the first structure 101 by a deposition process 200b may be formed. A second gate insulating layer 204 is formed on the sidewall of the second opening 202 by a deposition process to form a second opening 202 which is vertically aligned with the first opening 102 by photoetching and etching, Can be formed. The second structure 201 may be formed by forming a second active column 206 filling the second opening 202 by a vapor deposition and mechanical polishing process. It is preferable that the second opening 202 is formed using a dry etching process as much as possible because the shape of the second opening 202 can be set as perpendicular as possible.

Even if the second opening 202 is formed using the dry etching technique, the second opening 202 may be formed to be inclined. For example, the lower portion of the second opening 202 may have a larger width than the upper portion. In particular, if the number of the conductive films 220-280 constituting the first conductive film group 200b increases, the inclination of the second opening 202 will be further increased. If the second opening 202 is formed to be inclined, the width of the second active pillars 206 filling the second opening 202 may vary according to the height. For example, the second active pillars 206 may be tapered so that their cross-sectional area decreases from the top to the bottom.

The channel width of the memory transistor utilizing each of the plurality of conductive films 220-280 of the first conductive film group 200b as the first control gate is changed due to the inclined second active column 206, This fraction can be uniform. Therefore, the inclined second opening 202 can be formed so that the second active column 206 having a height large enough to ignore the degree of cell scattering can be formed. For this, the number of the conductive films 220-280 constituting the first conductive film group 200b and the number of the insulating films 210-290 constituting the first insulating film group 200a can be appropriately selected. In this embodiment, the number of the conductive films 220-280 constituting the first conductive film group 200b is limited to four, and the number of the insulating films 210-290 constituting the first insulating film group 200a is Although the number is limited to five, the number is arbitrary.

A third structure 301 including a plurality of conductive films 320-380 (control gates) and a third gate insulating film 304 capable of trapping charges is formed in a process similar to the process of forming the second structure 201 can do. Like the second active pillars 206, the third active pillars 306 may be formed in an inclined shape.

The insulating film 410, the conductive film 420 (upper select gate), and the insulating film 430 can be formed on the third structure 301 by a deposition process. The fourth opening 402 may be formed by a photo-etching process, and a fourth gate insulating film 404 may be formed on a side wall of the fourth opening 402 by a deposition process. The fourth structure 401 may be formed by forming a fourth active pillar 406 filling the fourth opening 402 by a vapor deposition and mechanical polishing process. At this time, the fourth opening 402 may be inclined, and the fourth active column 406 may be formed in an inclined columnar shape. A bit line 610 electrically connected to the active pillar 406 may be formed by depositing and patterning a conductor such as a metal on the fourth structure 401.

As described above, the active pillars 506 may be implemented by vertically connecting the first to fourth active pillars 106 to 406 formed over four processes, for example. Since each of the first to fourth active pillars 106 to 406 can minimize the difference in width along their heights, as described later with reference to FIG. 8C, the active pillars 506 have a difference in width Can be minimized. 8B, even when the process for forming the active pillars 506 is performed several times, for example, N times in excess of four times, the difference in width of the active pillars 506 can be minimized.

FIG. 8C is a cross-sectional view illustrating a method of fabricating a nonvolatile memory device according to another embodiment of the present invention. Referring to FIG. 8C, the active pillars I may be formed through a number of processes, II). ≪ / RTI >

Referring to FIG. 8C, as described with reference to FIG. 8A, the active pillars 506 may be implemented by connecting first to fourth active pillars 106 - 406 formed four times. Thus, the difference in width along the height of the active pillars 506 can be much smaller than the difference in width along the height of the active pillars 506 '. For example, when dry etch is used to form the active pillars 506 ', the top is continuously dry etched while the bottom is etched, and the damage is relatively large due to the plasma used for dry etching. Thus, the top width W2 'of the active pillars 506' may be larger than the top width W2 of the active pillars 506. In addition, the bottom width W1 'of the active pillars 506' may be smaller than the bottom width W1 of the active pillars 506. Therefore, the difference W2-W1 between the upper width W2 and the lower width W1 of the active column 506 is smaller than the difference between the upper width W2 'and the lower width W1' of the active column 506 ' (W2 ' -W1 ').

The difference W4-W3 between the upper width W4 and the lower width W3 of the second active column 206 in the active column 506 is smaller than the difference W2-W1 in the width of the active column 506 It can be bigger. However, since the height of the second active column 206 is smaller than that of the active column 506 ', the upper width W4 of the second active column 506 is smaller than the upper width W2' of the active column 506 ' ). ≪ / RTI > In addition, the bottom width W3 of the second active column 206 may be larger than the bottom width W1 'of the active column 506'. Therefore, the difference W4-W3 of the width of the second active column 206 can be smaller than the difference W2'-W1 'of the width of the active column 506'. The description of the width difference of the second active pillars 206 is the same for the third active pillars 306 as well.

As described above, the active pillars 506 formed by a plurality of processes in comparison with the active pillars 506 'formed in a single process can minimize the difference in width between the upper and lower sides, so that the electrical characteristics of the transistors, It is possible to ensure the uniformity of the electrical characteristics of the electrodes. This description can also be applied to the active pillars 506 formed over N times described with reference to Fig. 8B.

(Application example)

9A is a block diagram showing a memory card having a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 9A, a memory card 1200 (MEMORY CARD) includes a flash memory 1210 for supporting a high capacity data storage capability. The flash memory 1210 may include a nonvolatile memory device according to an embodiment of the present invention, for example, a NAND flash memory device.

The memory card 1200 may include a memory controller 1220 that controls exchange of various data between the host (HOST) and the flash memory 1210 (FALSH MEMORY). An SRAM 1221 (SRAM) can be used as an operation memory of the central processing unit 1222 (CPU). The host interface 1223 (HOST INTERFACE) may have a data exchange protocol of a host (HOST) connected to the memory card 1200. The error correction code 1224 (ECC) can detect and correct an error included in data read from the flash memory 1210. [ A memory interface 1225 (MEMORY INTERFACE) interfaces with the flash memory 1210. The central processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although not shown in the figure, the memory card 1200 may further include a ROM for storing code data for interfacing with a host (HOST).

9B is a block diagram illustrating an information processing system according to an embodiment of the present invention.

9B, an information processing system 1300 according to an embodiment of the present invention includes a flash memory system 1310 having the above-described nonvolatile memory element, for example, a flash memory element (e.g., a NAND flash memory element) can do. The information processing system 1300 may include a mobile device, a computer, or the like.

The information processing system 1300 includes a flash memory system 1310 and a modem 1320 electrically connected to the system bus 1360, a central processing unit 1330 (CPU), a RAM 1340 (RAM) And a user interface 1350 (USER INTERFACE). The flash memory system 1310 may store data processed by the central processing unit 1330 or externally input data.

The information processing system 1300 may be provided as a memory card, a solid state disk, a camera image sensor, and other application chipsets. In one example, the flash memory system 1310 may be comprised of a semiconductor disk device (SSD), in which case the information processing system 1300 may store a large amount of data reliably and reliably in the flash memory system 1310 .

The flash memory or flash memory system according to the present invention can be mounted in various types of packages. For example, the flash memory or flash memory system according to the present invention may be implemented as a package-on-package, a ball grid array, a chip scale package, a plastic leaded chip Carrier, Plastic Dual In-Line Package, Multi Chip Package, Wafer Level Package, Wafer Level Fabricated Package, Wafer Level Process Stack Package A die-on wafer form, a chip on board, a ceramic dual in-line package, and the like. ), Plastic Metric Quad Flat Pack, Thin Quad Flat Pack, Small Outline Package, Can be packaged in the same manner as the Shrink Small Outline Package, the Thin Small Outline Package, the Thin Quad Flat Package and the System In Package. .

It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

INDUSTRIAL APPLICABILITY The present invention can be effectively applied to semiconductor industries for manufacturing semiconductor memory devices as well as manufacturing industries for producing electronic products using semiconductor memory devices.

1 is a perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention;

2 is a perspective view illustrating a cell region of a nonvolatile memory device according to an embodiment of the present invention;

3A and 3B are perspective views showing a memory transistor in a nonvolatile memory device according to an embodiment of the present invention.

4 is an equivalent circuit diagram of a nonvolatile memory device according to an embodiment of the present invention.

5A to 5P are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

6A and 6B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to a modified embodiment of the present invention.

7A and 7B are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to another modified embodiment of the present invention.

8A and 8B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to still another modified embodiment of the present invention.

FIG. 8C is a cross-sectional view illustrating a method of fabricating a nonvolatile memory device according to another embodiment of the present invention. Referring to FIG. 8C, the active pillars I may be formed through a number of processes, II). ≪ / RTI >

9A and 9B are block diagrams showing an apparatus to which a nonvolatile memory device according to an embodiment of the present invention is applied.

Claims (10)

Alternately laminating conductive films and insulating films on a substrate; And Forming active pillars through the conductive films and the insulating films and electrically connected to the substrate, Alternately laminating the conductive films and the insulating films and forming the active pillars are alternately performed at least twice, Wherein the active pillars comprise a plurality of subactive columns and the sidewalls of each of the plurality of subactive columns have an inclination relative to an upper surface of the substrate. The method according to claim 1, The stacking of the conductive films comprises: Forming a first gate on the substrate, and then forming a first opening through the first gate; Forming a plurality of second gates vertically stacked on the first gate, forming a second opening vertically connected to the first opening through the plurality of second gates; And Forming a third gate on the plurality of second gates and then forming a third opening through the third gate and perpendicular to the second opening; Wherein the nonvolatile memory element is formed of a nonvolatile memory element. 3. The method of claim 2, The active pillars are formed by: Forming a first sub-active column that fills the first opening and is perpendicular to the substrate; Forming a second sub-active column that fills the second opening and is perpendicular to the first sub-active column; And Forming a third sub-active column that fills the third opening and is perpendicular to the second sub-active column; Wherein the nonvolatile memory element is formed of a nonvolatile memory element. The method of claim 3, The active pillars are formed by: Forming a first gate insulating film on a sidewall of the first opening; Forming a second gate insulating film including a charge storage film on a side wall of the second opening; And Forming a third gate insulating film on a sidewall of the third opening; Wherein the nonvolatile memory element is formed of a nonvolatile memory element. Forming a first structure on the substrate including a lower select gate and a first active column vertically extending from the substrate through the lower select gate; Forming a second structure including a plurality of first control gates stacked on the first structure and a second active column vertically extending from the first active column through the plurality of first control gates; And Forming a third structure on the second structure including an upper select gate and a third active column vertically extending from the second active column through the upper select gate, Wherein the cross-sectional area of the second active column gradually increases as the distance from the substrate increases. 6. The method of claim 5, Prior to forming the third structure: Forming a fourth structure including a plurality of second control gates stacked on the second structure and a fourth active column vertically extending from the second active column through the plurality of second control gates; Wherein the nonvolatile memory device further comprises a nonvolatile memory element. 6. The method of claim 5, Further comprising forming a bit line electrically connected to the third active column on the third structure. 6. The method of claim 5, Wherein one of the upper and lower selection gates is formed in a plate shape and the other is formed in a plurality of line shapes; And Wherein the plurality of first control gates are formed in a plate shape; Wherein the nonvolatile memory element is formed of a nonvolatile memory element. A plurality of gates vertically stacked on a semiconductor substrate; Active pillars extending vertically from the semiconductor substrate through the plurality of gates; And And a gate insulating film disposed between the active column and the plurality of gates, Wherein the active pillars are formed of the same material as the semiconductor substrate and include a plurality of vertically connected pillars, each of the plurality of pillars including a sloped column having a smaller cross-sectional area from the upper end to the lower end. 10. The method of claim 9, Wherein the active pillars further include an insulator therein.

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