KR101477809B1 - A computer system and method controlling memory module - Google Patents

Abstract

The present invention relates to a computer system for controlling a memory module and a memory module control method thereof, and more particularly, to a computer system including a memory controller for controlling the use of a memory module having the fastest speed among a plurality of memory modules, . To this end, a computer system for controlling a memory module according to the present invention includes: a plurality of memory modules for storing data; A memory controller for controlling the plurality of memory modules and controlling the memory module having the fastest speed among the memory modules to be used first; An input / output device for outputting data to a user and receiving input from a user; An input / output controller for controlling the input / output device; And a central processing unit for controlling the operation of the components.

Memory module, memory controller, clock speed, clock generator

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a computer system for controlling a memory module,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for controlling a memory module and a memory module control method thereof, and more particularly to a computer system including a memory controller for controlling the use of a memory module having the highest speed among a plurality of memory modules, To a memory module control method.

The memory is collectively referred to as being used for temporarily or permanently storing data or commands used in a computer, a communication system, an image processing system, or the like. Typically, semiconductors, tapes, discs, optical systems, etc. are present, but semiconductor memories are the majority. There are many types of semiconductor memories, such as DRAM, SRAM, Flash Memory, and ROM, which are classified according to the electrical characteristics of the data storage method, among which DRAM is the largest.

Since the storage potential of DRAM (Dynamic Random Access Memory) changes with time, periodic refresh operation is required to periodically restore the storage potential to the original state. Since the amount of charge stored in the capacitor becomes the data decision criterion, the voltage difference according to the difference of the charge amount is maintained in the reading operation, and the detected difference data is outputted to output the data. It has dynamic characteristics.

When such a memory is actually used in a system, it is produced by making a module. A module is a set of elements having one function. A package device such as a semiconductor device is mounted on a printed circuit board (PCB) And is connected to a panel or the like by tabs having a plurality of connection pins.

The dual in-line memory module (DIMM), which is the most commonly used DRAM (SDRAM) memory module among the memory devices used in computer systems, uses signals defined by Joint Electron Device Engineering Council (JEDEC) standard or Intel standard.

The speed at which the characteristics of the memory module are expressed is classified into PC66, PC100, and PC133. This speed represents the operating frequency of the memory, for example, the PC 100 refers to a clock speed of 100 MHz.

For example, with a memory running at 100 MHz and a memory running at 133 MHz, the motherboard knows that both memories are operating at 100 and 133, respectively, and the speed at which both memories can operate without errors It will automatically set both memories to work.

That is, when there are a plurality of memory modules in one computer system, there is an unreasonable necessity to operate each memory module at a slow operating speed in the structure of the system when the operating speeds of the memory modules are different.

Accordingly, even if a memory module with a high operating speed is mounted in the related art, the memory module operates at the operating speed of the memory module having the slowest operating speed, so that the operating speed of the memory module can not be maximized.

In order to solve such conventional problems, the present invention aims to provide a computer system capable of controlling a plurality of memory modules and controlling the memory module having the fastest speed among the memory modules to be used first, thereby improving memory efficiency do.

A computer system according to an embodiment of the present invention includes a plurality of memory modules for storing data; A memory controller for controlling the plurality of memory modules and controlling the memory module having the fastest speed among the memory modules to be used first; An input / output device for outputting data to a user and receiving input from a user; An input / output controller for controlling the input / output device; And a central processing unit for controlling the operation of the components.

A memory controller according to an embodiment of the present invention controls a memory module having the fastest speed among the plurality of memory modules to be used first. The memory controller reads a clock speed of the plurality of memory modules, Controller; A plurality of channel controllers for receiving the compared clock speed from the clock controller and transmitting a clock enable (CKE) signal to the memory module having the fastest speed; And a plurality of registers connected to the channel controllers one by one.

According to another aspect of the present invention, there is provided a method of controlling a memory module, comprising: reading a clock rate of a plurality of memory modules; Comparing the plurality of read clock rates; As a result of comparison, only the clock generator connected to the memory module having the highest clock speed among the plurality of memory modules is operated to use the corresponding module first.

According to the computer system and the memory module control method of the present invention, memory efficiency can be improved by controlling a plurality of memory modules and using the memory module having the highest speed among the memory modules first.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a computer system according to an embodiment of the present invention.

The computer system may include a CPU 1, a memory module 2, a memory controller 3, an input / output device 4, an input / output controller 5 and an HDD 6.

The CPU 1 is a central processing unit and controls most of the devices of the computer system including the memory module 2, the memory controller 3, the input / output device 4, and the input / output controller 5.

The memory module 2 stores programs and various data necessary for the operation of the computer system. The memory module 2 is constituted by a plurality of memory chips, and a predetermined number of memory chips may be constituted by memory banks. Thus, the memory module 2 may be composed of several memory chips or memory banks.

A plurality of memory modules 2 may exist in one computer system. However, each memory module 2 has the same operating characteristics when it is a product of the same company and the same standard, but its operation characteristics are different when each memory module 2 has a different company or different standard.

The memory controller 3 controls the plurality of memory modules 2 to store or fetch data in the memory module 2. [ The memory controller 3 according to the present invention can control so that the memory module 2 having the fastest speed among the plurality of memory modules 2 is used first. A detailed description of the memory controller 3 will be given later.

The input / output device 4 receives input from the user via the input device, and outputs the resultant data processed by the computer through the output device. Input devices include keyboards, scanners, mice, touch screens, joysticks, card readers, voice input devices, optical character readers, and optical mark readers. The output device includes a printer, a CRT, a voice synthesizer, and a voice response device. The input / output controller (5) controls the input / output device (4).

The HDD 6 is an auxiliary storage device for storing and reading data.

2 shows a block diagram of the configuration of the memory controller 3, the first memory module 31 and the second memory module 32 according to an embodiment of the present invention.

The first memory module 31 and the second memory module 32 may have a plurality of memory chips mounted on a PCB. These memory modules include a single in-line memory module (SIMM) and a dual in-line memory module (DIMM). A SIMM is a memory chip mounted on one side of a PCB, and a DIMM is used on both sides of a PCB. Currently, most of the memory modules are occupied by DIMMs.

The first memory module 31 and the second memory module 32 according to the present invention include both SIMMs and DIMMs, but are not limited thereto.

The memory controller 3 supporting the interface between the first memory module 31 and the second memory module 32 and the CPU includes a first channel controller 10 and a first register 14, a second channel controller 20 A second register 24, and a clock controller 40. The first and second registers 24,

The first channel controller 10 may include a data controller 11, an address controller 12, and a command controller 13.

The data controller 11 is an interface for controlling data of the first memory module 31 and stores or fetches data at the position of the first memory module 31 found by the command controller 13 to be described later. And transmits DM, DQ, and DQM signals to the first memory module 31.

When the DM (Data Mask) signal is enabled, no data is input to the corresponding memory module. The DQ (Data Bus) signal is a signal containing actual data. The DQS (Data Strobes) signal is a signal for transmitting data at a point where DQS and DQS # intersect.

The address controller 12 is an interface for controlling the address of the first memory module 31. Specifically, the first memory module 31 interprets the request from the CPU to read out the position or the address at which data is to be written or to read data, thereby converting the system address into a memory address. In accordance with the converted memory address, . The address controller 12 transmits CS, ADD, and BA signals to the first memory module 31.

The CS (Chip Select) signal determines which of a plurality of memory chips constituting one memory module is to be selected. The ADD (MA, Memory Address) signal is used to provide the row and column addresses of the memory modules. A BA (Bank Address) signal is formed of a plurality of cells constituting a memory module, and determines which one of the cells to select.

The command controller 13 transmits the corresponding RAS, CAS, WE, and CKE signals to the first memory module 31 according to the memory address generated by the address controller 12. Thus, the corresponding position of the first memory module 31 is detected so that data can be input and output.

A row address signal (RAS) indicates that a memory address entered at the time of enable is a row address of an address of the first memory module 31. A column address signal (CAS) indicates a memory address Indicates the column address of the address of the first memory module 31. [

The WE (Write Enable) signal is transmitted when the data is stored in the first memory module 31, and is transmitted to the first memory module 31 only when data is stored.

The CKE (Clock Enable) signal generates a clock corresponding to the clock speed of the first memory module 31 to enable the first memory module 31 to be used.

The first register 14 stores commands and data necessary for controlling the first memory module 31. [ A program for operating the first channel controller 10 may be stored in the first register 14. [

The clock controller 40 reads the respective clock rates from the first memory module 31 and the second memory module 32 to compare the speeds. The clock controller 40 stores information on a clock rate corresponding to each of the memory modules 31 and 32 in the registers 14 and 24 connected to the channel controllers 10 and 20 and the channel controllers 10 and 20, ).

The clock controller 40 may include a clock generator (not shown) for one or more memory modules. The at least one clock generator is coupled to a plurality of memory modules to generate a clock suitable for each memory module. The clock generator should correspond to the number of memory modules and the memory module may be added by the user so that it is preferable that the clock generator has as many as the number of memory modules that the memory controller 3 can support.

The clock generator counts the clock only for the corresponding memory module, and when the selected memory module is to be controlled, the clock generator counts the clock using the clock generator corresponding to the memory module.

Therefore, since there is a clock generator corresponding to a plurality of memory modules, the CPU can control each memory module at an operating speed determined according to the operating characteristics of each memory module.

The components of the second channel controller 20, that is, the data controller 21, the address controller 22, the command controller 23 and the second register 24 are connected to the first channel controller 10 and the first channel controller 10 The configuration and the function of the register 14 are the same.

In one embodiment of the present invention, a process of storing or fetching data in the first memory module 31 and the second memory module 32 will be described.

First, the CPU controls to fetch information on the clock speeds of the first memory module 31 and the second memory module 32. The CPU controls the clock controller 40 so that the clock controller 40 operates on the clocks corresponding to the memory modules 31 and 32 according to the number of clocks required for operation of the first memory module 31 and the second memory module 32 Setting.

That is, the clock controller 40 receives information on the clock speeds of the memory modules 31 and 32, and compares the difference in clock speed.

As a result of comparing the clock speed, a memory module with a faster clock speed is first used.

The clock controller 40 transmits information on the clock speeds of the received memory modules 31 and 32 to the respective channel controllers 10 and 20 and the registers 14 and 24.

In one embodiment, if the clock speed of the first memory module 31 is faster than the second memory module 32, then only the first memory module 31 may be used first.

The address controller 12 in the first channel controller 10 finds the address of the data to be used first to use the first memory module 31. At this time, the address controller 12 can transmit the CS, ADD, and BA signals to the first memory module 31.

In response to this, the comment controller 13 transmits the corresponding RAS, CAS, WE, and CKE signals to the first memory module 31 according to the memory address generated by the address controller 12.

Therefore, only the clock generator connected to the first memory module 31 can be operated to use the first memory module 31 first.

At this time, the operation of the clock generator can be prevented by disabling CKE (clock enable) input to the second memory module 32 which is not to be used.

According to an embodiment, the second memory module 32 may be disabled by disabling the CS input to the second memory module 32 that is not to be used.

Also, it is possible to disable RAS and CAS input to the second memory module 32 which is not to be used, thereby preventing the second memory module 32 from being addressed.

However, the clock controller 40 periodically checks the usage amount of the memory, and may further operate the other memory modules in the order of higher speed when the additional memory is required. To this end, additional clock generators connected to different memory modules in the order of higher speed can be operated.

Accordingly, after the first memory module 31 is used, if the second memory module 32 is additionally required, the second memory module 32 can be operated. In this case, the clock generator can be operated by enabling CKE (clock enable) input to the second memory module 32 to be added.

In the above-described embodiment, the case where two memory modules are used has been described. However, it goes without saying that the present invention can be applied to the case of using more memory modules.

1 is a schematic block diagram of a computer system according to the present invention.

2 is a schematic block diagram of a memory controller according to the present invention.

Description of the Related Art [0002]

1: CPU (central processing unit) 2: memory module

3: Memory controller 4: I / O device

5: I / O controller 6: HDD

10: first channel controller 31: first memory module

20: first channel controller 32: second memory module

11, 21: Data controller 12, 22: Address controller

13, 23: Command controller 40: Clock controller

14: first register 24: second register

Claims (10)

A plurality of memory modules for storing data; A memory controller for controlling the plurality of memory modules and controlling the memory module having the fastest speed among the memory modules to be used first; An input / output device for outputting data to a user and receiving input from a user; An input / output controller for controlling the input / output device; And A central processing unit for controlling the operation of the components; ≪ / RTI > A memory controller for controlling to use a memory module having the fastest speed among a plurality of memory modules, A clock controller for reading the clock speeds of the plurality of memory modules and comparing the speeds; A plurality of channel controllers for receiving the compared clock speed from the clock controller and transmitting a clock enable (CKE) signal to the memory module having the fastest speed; And A plurality of registers connected to the channel controllers one by one; . 3. The method of claim 2, Wherein each of the plurality of channel controllers includes a data controller, an address controller, and a command controller. 3. The method of claim 2, Wherein the clock controller comprises one or more clock generators. 5. The method of claim 4, Wherein the at least one clock generator is coupled to a plurality of memory modules to generate a clock suitable for each memory module. 3. The method of claim 2, Wherein the clock controller periodically checks the amount of memory usage and further operates the other memory modules in order of speed when an additional memory is needed. Reading a clock speed of a plurality of memory modules; Comparing the plurality of read clock rates; As a result of the comparison, only the clock generator connected to the memory module having the highest clock speed among the plurality of memory modules is operated to use the corresponding module first; ≪ / RTI > 8. The method of claim 7, Disabling clock enable (CKE) input to a memory module not to be used to prevent operation of the clock generator; ≪ / RTI > 8. The method of claim 7, Further operating other memory modules in order of increasing speed if additional memory is needed; ≪ / RTI > 10. The method of claim 9, And activating a clock enable (CKE) input to the memory module to be added to operate the clock generator.

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