KR101441954B1 - Improvement device for line dim of liquid crystal display device - Google Patents

Abstract

The present invention relates to a technique for compensating data that is alternately charged in a vertical alternating manner in order to prevent generation of vertical dimming in each vertical line in a liquid crystal display device of a DRD pixel structure. According to the present invention, a timing controller for uniformly compensating the charged amount of each of the RGB data corresponding to one of the vertical data lines and the vertical data lines when the RGB data for the DRD pixel structure is output; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to a data signal control signal supplied from the timing controller.

Blue line dim, data compensation

Description

TECHNICAL FIELD [0001] The present invention relates to a line dim improving device for a liquid crystal display,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique of a liquid crystal display, and more particularly, to a liquid crystal display (LCD) having a pixel structure of DRD (Double Reduced Data) To an apparatus for improving the line depth of the apparatus.

In recent years, as information technology (IT) has evolved, display has become more important as a visual information delivery medium. In order to prevail in the future, it is necessary to meet requirements such as low power consumption, thinning, light weight, and high image quality.

2. Description of the Related Art A liquid crystal display (LCD), which is a typical display device of a flat panel display, is an apparatus for displaying an image using optical anisotropy of a liquid crystal. Because of its advantages such as thinness, small size, low power consumption and high picture quality, Ray Tube (CRT)).

2. Description of the Related Art In general, a liquid crystal display device is a display device that supplies image information individually to pixels arranged in a matrix form, and can display a desired image by adjusting light transmittance of the pixels. Therefore, the liquid crystal display device includes a liquid crystal panel in which pixels, which are minimum units for realizing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. In addition, since the liquid crystal display device can not emit light by itself, a backlight unit for supplying light to the liquid crystal display device is provided.

FIG. 1 shows a pixel mapping of the DRD structure, and FIG. 2 shows a waveform of a version driving scheme with two dots.

A pixel whose structure polarity is changed from negative (-) to positive (+) or vice versa of a DRD pixel is different from a pixel whose polarity is not changed, that is, a pixel whose polarity is changed from negative to positive, As the timing becomes longer, the amount of charged charge decreases accordingly.

For this reason, as shown in FIG. 2, the red pixel R is constantly charged, and the green pixel G is always charged with a strong charge, so that no difference in charge amount occurs between the pixels. On the other hand, the blue pixel (B) is alternately filled with strong charge and weak charge per vertical line. Accordingly, as shown in FIG. 3, a blue line dim of a vertical line type is generated for each vertical line only of a blue pixel in a gray test pattern. For reference, the difference in the charging amount between the charging lines of the strong filling agent is 2 to 3 gradations, and the voltage is 20 to 30 mV.

In the conventional liquid crystal display device adopting the DRD pixel structure, two pixels among red, green and blue pixels do not have a difference in vertical charging capacity, but the remaining pixels are alternately charged and charged by vertical lines So that there is a problem that a vertical line-shaped dim is generated for each vertical line.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to compensate for the amount of charge of a pixel in which a strong charge and a weak charge are alternated for each vertical line in a liquid crystal display device adopting a direct current (DRD) structure, .

According to an aspect of the present invention, there is provided a liquid crystal display device including a gate control signal for a double reduced data (DRD) pixel structure in which subpixels commonly connected to one data line of a liquid crystal panel are connected to different gate lines, A timing controller for generating and outputting a signal and RGB data by adjusting a gradation level of one RGB data among the RGB data to compensate for a specific subpixel to be uniformly charged for each vertical line of the liquid crystal panel; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to the gate control signal; And a data driver for outputting the pixel signals for the RGB data to the respective data lines of the liquid crystal panel in response to the data control signal.

In the present invention, when one piece of RGB data is output for RGB data for the DRD pixel structure, the data is compensated for each vertical line to be charged and charged in a vertical manner, It is possible to reliably prevent the occurrence of the line dim (Dim) of the liquid crystal display panel.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram showing an embodiment of a line dim improving apparatus of a liquid crystal display according to the present invention. As shown in FIG. 4, a gate control signal GDC for controlling driving of a gate driving unit 42, And a data control signal DDC for controlling the driving of the data driver 43 and outputting the RGB data for the DRD pixel structure, one of the RGB data is strongly charged and approximately charged per vertical line A timing controller (41) for compensating and outputting the amounts of charge to each other so as to correspond to each other; A gate driver 42 for outputting gate signals to the gate lines GL1 to GLn of the liquid crystal panel 44 in response to a gate control signal GDC supplied from the timing controller 41; A data driver 43 for supplying a pixel signal to the data lines DL1 to DLm of the liquid crystal panel 44 in response to a data control signal DDC supplied from the timing controller 41; And a liquid crystal panel 44 for displaying an image by providing liquid crystal cells driven by the gate signal and the pixel signal in a matrix form.

The timing controller 41 includes a data separator 41A for separating and outputting RGB data from an input signal; A frame rate control unit (41B) for controlling a frame rate of the separated RGB data; In order to prevent the data of a specific pixel among the RGB data output from the frame rate controller 41B from being output toward the RGB pixels of the DRD structure to alternate between the strong charging and the weak charging for each vertical line, A data compensating section 41C for compensating the charge amount to be equalized; A line memory 41D in which data compensated by the data compensating unit 41C is stored in units of horizontal lines; And an interface 41E for processing data stored in the line memory 41D into a form suitable for processing by the data driver 43 and outputting the data.

The operation of the present invention will now be described in detail with reference to FIGS. 5 to 8.

The timing controller 41 receives the gate control signal GDC for controlling the gate driving unit 42 and the data driving unit 43 using the vertical / horizontal synchronizing signal Hsync / Vsync and the clock signal DCLK supplied from the system, And outputs a data control signal DDC for controlling the data control signal DDC. In addition, the timing controller 41 samples the digital pixel data input from the system, rearranges the digital data, and supplies the data to the data driver 43 in RGB data (RGB).

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate-out enable signal GOE. The data control signal DDC includes a source start pulse SSP, (SSC), a source-out enable (SOE), and a polarity signal (POL).

The gate driver 42 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 41, ) Are turned on. Accordingly, the pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

To be more specific, the gate driver 42 shifts the gate start pulse GSP according to the gate shift clock GSC to generate a shift pulse. In response to the shift clock, the gate driver 42 supplies a gate signal composed of a gate on / off period (signal) to the corresponding gate line GL in each horizontal period. In this case, the gate driver 42 supplies a gate-on signal only in an enable period in response to the gate-on enable signal GOE, and supplies a gate-off signal (gate-low signal) in other periods.

The data driver 43 converts the RGB data (RGB) into an analog pixel signal (data signal or data voltage) corresponding to the gray level value in response to the data control signal DDC input from the timing controller 41 And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 44. [

To be more specific, the data driver 43 shifts the source start pulse SSP according to the source shift clock to generate a sampling signal. The data driver 43 sequentially receives and latches the pixel data RGB in units of a predetermined unit in response to the sampling signal. Then, the data driver 43 converts the latched pixel data (RGB) of one line into analog pixel signals and supplies them to the data lines DL1 to DLm.

The liquid crystal panel 44 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC (TFT) connected to each of the TFTs.

The thin film transistor TFT is turned on when a gate signal is supplied from the gate line GL and supplies a pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when a gate off signal is supplied through the gate line GL, so that the pixel signal charged in the liquid crystal cell C _LC is maintained. The liquid crystal cell C _LC includes a common electrode and a pixel electrode connected to the thin film transistor TFT via a liquid crystal. The liquid crystal cell C _LC further includes a storage capacitor C _ST to maintain the charged pixel signal stably until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In such a liquid crystal cell C _LC , the alignment state of the liquid crystal having dielectric anisotropy is varied according to the pixel signal charged through the thin film transistor (TFT), so that the light transmittance is adjusted to realize the gradation.

The process of input data processing in the timing controller 41 will be described in more detail as follows.

The data separation unit 41A separates and outputs RGB data from a signal input from the system, and the frame rate control unit 41B controls the frame rate of the separated RGB data.

The data compensating unit 41C is configured such that the data of a specific pixel among the RGB data output from the frame rate controller 41B toward the RGB pixels of the DRD structure is alternately filled in the vertical line and the vertical direction, The data is appropriately compensated and output.

2, the data of the blue pixel B supplied to the second channel (D-IC ch2) of the data driver in the case of the data of the blue pixel (B) is strongly charged, The data supplied to the third channel (D-IC ch3) of the data driver is charged so that one of the charges is compensated for, thereby making it possible to prevent the generation of the vertical line dim.

To this end, the data of the blue pixel B supplied to the second channel (D-IC ch2) may be lowered to a predetermined gray (for example, 2 Gray) or the blue pixel supplied to the third channel (D- (For example, 2 Gray). However, in this example, the data is compensated in the black direction by lowering the gray level to a predetermined gray level (for example, 2 gray levels).

FIG. 5 is a detailed block diagram illustrating an embodiment of the data compensator 41C. FIG. 6 illustrates a data format of the lookup table in FIG. 5. Referring to FIG. The same data compensation process will be described in detail as follows.

When the current vertical line is a vertical line other than the vertical line at which the blue pixel B to be compensated is located among the input data of the data compensating unit 41C, the multiplexer 52 outputs the output signal of the line counter The data input to the first input terminal is directly selected and output, so data compensation is not performed at this time.

Even if the current vertical line is the vertical line at which the blue pixel B to be compensated is located among the input data of the data compensating unit 41C, it is possible to use a gradation range in which the visibility is insensitive, for example, Since the above data compensation is unnecessary in the gradation periods 42 to 63, the multiplexer 52 selects and outputs the data input to the first input terminal as it is by the output signal of the line counter.

However, if the current vertical line is a vertical line in which the blue pixel B to be compensated is located among the input data of the data compensating unit 41C, the gradation period (0 to 20 gradations, 42 to 63) in which the visibility is insensitive The multiplexer 52 selects and outputs data to be input to the second input terminal by the output signal of the line counter.

Therefore, at this time, the data compensated by the lookup table 51 is outputted through the multiplexer 52.

For example, if the data of the blue pixel B located on the current vertical line is 21 gray data '010101', the data '010101' is supplied to the address of the lookup table 51, Gray low data '010011' is output.

As another example, if the data of the blue pixel B located on the current vertical line is 31 gray data '011111', the data '011111' is supplied to the address of the lookup table 51, Gray low data '011101' is output.

The data and the compensated data as they are output through the multiplexer 52 are stored in the line memory 41D located at the next stage.

The data stored in the line memory 41D is divided into RGB data suitable for processing in the data driver 43 through an interface (mini-LVDS) 41E.

FIG. 7 shows an example in which the RGB data '011111' of 31 gray is compensated by the gray data '011101' of 29 gray through the data compensator 41C as described above.

8 illustrates waveforms compensated in the white direction by raising the corresponding data of the RGB data to a predetermined gray (for example, 2 gray) unlike in the above description.

1 is a pixel mapping diagram of a diallyl structure;

Fig. 2 is a waveform diagram of a version driving method with two dots. Fig.

FIG. 3 is a pattern showing an example in which a blue line dim is formed in a vertical line for each vertical line by blue pixels.

4 is a block diagram of an apparatus for improving the lint-length of a liquid crystal display device according to the present invention.

5 is a detailed block diagram of the data compensating unit in FIG.

6 is a compensation data format diagram of the look-up table in Fig.

FIG. 7 is an exemplary view showing data before and after compensation according to the present invention; FIG.

8 is a data waveform diagram before and after compensation according to the present invention.

DESCRIPTION OF THE REFERENCE SYMBOLS

41: timing controller 41A:

41B: frame rate control unit 41C:

41D: line memory 41E: interface section

42: Gate driver 43: Data driver

44: liquid crystal panel

Claims (8)

A data control signal and RGB data for a DRD (Double Reduced Data) pixel structure in which subpixels commonly connected to one data line of a liquid crystal panel are connected to different gate lines, respectively, A timing controller for adjusting a gradation level of one of the RGB data to compensate for a specific subpixel to be charged uniformly for each vertical line of the liquid crystal panel and outputting the compensated subpixel; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to the gate control signal; And And a data driver for outputting the pixel signals for the RGB data to the respective data lines of the liquid crystal panel in response to the data control signal. 2. The timing controller according to claim 1, A data separator for separating and outputting the RGB data from an input signal; A frame rate control unit for controlling a frame rate of the RGB data; And A data compensating unit for compensating for the uniformity of the specific subpixels for each vertical line of the liquid crystal panel by adjusting the gradation level of RGB data for the specific subpixel among the RGB data whose frame rate is controlled by the frame rate control unit And a line dimming device for adjusting the line depth of the liquid crystal display device. 3. The apparatus of claim 2, wherein the data compensator comprises: A look-up table in which compensation data for compensating the specific sub-pixel to be charged equally is stored; And And a multiplexer for outputting the RGB data whose frame rate is controlled as it is or for selecting the compensation data stored in the lookup table and outputting the selected RGB data as the RGB data. The method of claim 3, If the data line of the liquid crystal panel from which the pixel signal is output from the data driver is not a data line in which the specific sub-pixel is located, And the multiplexer outputs the RGB data whose frame rate is controlled to the data driver. The method of claim 3, The data line of the liquid crystal panel from which the pixel signal is output from the data driver is a data line in which the specific subpixel is located and the RGB data is a grayscale level whose visibility is insensitive, And the multiplexer outputs the RGB data whose frame rate is controlled to the data driver. 6. The method of claim 5, Wherein the gradation level in which the visibility is insensitive is 0 to 20 and 42 to 63 gradation levels of 0 to 63 gradation levels. The method according to claim 1, And the specific sub-pixel of the sub-pixels is a blue sub-pixel. The method of claim 3, When the data line of the liquid crystal panel from which the pixel signal is outputted from the data driver is the data line in which the specific subpixel is located and the RGB data is not a gradation level with insensitivity of visibility, Wherein the multiplexer selects the compensation data stored in the look-up table and outputs the compensation data to the data driver.

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