KR101439815B1 - Circuit and method for processing error of memory - Google Patents

Abstract

In the present invention, disclosed are a circuit and a method for correcting the error of a memory. Specially, the method for correcting the error of a memory according to one embodiment of the present invention includes the steps of: adaptively setting a protection range corresponding to an error correction range among unit data to be written in the memory according to an operation voltage of the memory; performing the error correction encoding of protection data which include the most significant bit (MSB) and corresponds to the protection range among the unit data; and writing the unit data in the memory by matching the unit data with parity data which are generated by the error correction encoding. The setting step narrowly sets the protection range according as the operation voltage of the memory becomes low.

Description

Technical Field [0001] The present invention relates to an error correction processing circuit and an error correction processing method in a memory,

The present invention relates to an error correction processing circuit and an error correction processing method, and more particularly to a circuit for correcting and processing an error occurring in a memory and a method for correcting and processing errors occurring in the memory.

An error correction code (ECC) refers to a coding (channel coding) scheme in which redundant information sufficient for a data block to be transmitted is included so that a receiver can infer what the transmitted character is. Error correction codes occupy an important position in digital communications and are also applied within hardware for data storage and transmission.

1 is a diagram for explaining an error occurring in a memory and a concept of an error correction processing circuit for correcting and processing such error.

As shown in Fig. 1, input data is passed through a write circuit to be written to a memory cell in a channel, and output data is read from a memory cell via a read circuit. At this time, an error may occur in the memory including the recording circuit, the reading circuit, and the memory cell. A circuit to which an error correction code is applied may be connected to correct the errors generated.

Korean Patent Publication No. 2009-0091179 (entitled " ECC protection device, method and system with small data structure ") discloses an error correction code engine that supports error correction operations on data structures of different sizes.

On the other hand, researches on low-power hardware have been actively conducted recently. At this time, a method of lowering the operating voltage of the hardware may be most effective.

However, in the case of a memory, the probability of occurrence of an error increases as the operating voltage decreases, as shown in FIG. 2 is a graph showing the error probability depending on the operating voltage of the memory. That is, if the operating voltage of the hardware is reduced, the power consumption can be reduced. However, there is a problem that the probability of occurrence of errors increases in the vicinity of the memory, thereby deteriorating the overall output quality.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems of the conventional art, and it is an object of the present invention to provide an error correction circuit and an error correction circuit which can correct errors generated with respect to data, And an object of the present invention is to provide a correction processing method.

It is another object of the present invention to provide an error correction processing circuit and an error correction processing method which can reduce the overall power consumption by turning off a part of the decoder for performing decoding.

It should be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to an aspect of the present invention, there is provided an error correction processing method in a memory, the method comprising: Adaptively setting a protection range; Performing error correction encoding on protection data corresponding to the protection range of the unit data and including an MSB (Most Significant Bit); And writing the unit data in the memory by matching with the parity data generated according to the error correction encoding, wherein the setting step narrows the protection range as the operating voltage of the memory is lowered.
Setting a protection range of unit data to be written in the memory according to an operating voltage of the memory; Performing error correction encoding on the protection data corresponding to the protection range of the unit data; And writing the unit data to the memory by matching the unit data with the parity data generated according to the error correction encoding.

The error correction processing circuit in the memory according to another embodiment of the present invention may further include a protection range adaptively setting a protection range corresponding to an error correction range of unit data to be written in the memory in accordance with an operating voltage of the memory, Setting section; An encoder for performing error correction encoding on protection data corresponding to the protection range of the unit data and including an MSB (Most Significant Bit); And a write unit for matching the unit data with parity data generated according to the error correction encoding and recording the unit data in the memory. The protection range setting unit narrows the protection range as the operating voltage of the memory decreases.

The error correction processing circuit and the error correction processing method according to any one of the above objects of the present invention perform error correction encoding on the protection data corresponding to the protection range of the unit data so as to minimize the power consumption and the calculation result error There is an advantage that it can be.

According to another aspect of the present invention, there is provided an error correction processing circuit and an error correction processing method for performing error correction decoding on protected data on which error correction encoding has been performed based on information on read parity data and a protection range The error generated in the protected data can be clearly corrected. Further, in performing error correction decoding, it is possible to reduce the overall power consumption by performing a turn-off process on an unnecessary configuration.

1 is a diagram for explaining an error occurring in a memory and an error correction processing circuit for correcting and processing such error,
2 is a graph showing the error probability depending on the operating voltage of the memory,
3 is a block diagram showing the entire structure of an error correction processing circuit according to an embodiment of the present invention;
4 is a diagram for explaining unit data, protected data, and unprotected data;
5 is a diagram for explaining the operation of the encoder shown in FIG. 3,
FIG. 6 is a diagram for specifically explaining an encoding process by the encoder of FIG. 5,
FIG. 7 is a view for explaining the detailed structure of the decoder shown in FIG. 3,
8 is a view for explaining the detailed structure of the syndrome generator in the configuration shown in FIG. 7,
9 is a view for explaining the detailed structure of the error detector in the configuration shown in FIG. 7,
10 is a flowchart for explaining an error correction processing method according to an embodiment of the present invention,
11 is a diagram for explaining a process of correcting and processing an error generated in the memory when the operating voltage of the memory is 1000 mV and when it is 700 mV,
FIG. 12 is a graph showing the effect that can be obtained through the control shown in FIGS. 8 and 9,
13 is a diagram for explaining a position where the error correction processing circuit shown in FIG. 3 can actually be applied on the H.264 circuit and the FFT processing circuit,
FIG. 14 is a graph showing an error correction processing circuit and a performance change when the method is applied to the H.264 circuit,
FIG. 15 is a graph for illustrating a change in performance when an error correction processing circuit and the method are applied to an FFT processing circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

3 is a block diagram showing the entire structure of an error correction processing circuit according to an embodiment of the present invention.

The error correction processing circuit 100 is a circuit for correcting and processing errors occurring in the memory and includes a protection range setting unit 110, an encoder 120, a recording unit 130, a communication unit 140, and a decoder 150 .

The error correction processing circuit 100 may be disposed between the processor 10 and the memory 20 to process and transmit data including encoded data and decoded data. However, the error correction processing circuit 100 shown in FIG. 3 is only one example that can be implemented. Therefore, the present invention is not limited thereto, and a separate circuit for performing the operation of each configuration or each configuration may be separated May be implemented and connected to each other.

Before describing each configuration included in the error correction processing circuit 100 in detail, the terms used in this specification will be described with reference to FIG. 4 is a diagram for explaining unit data, protection data, and unprotected data.

Data to be written in the memory 20 is referred to as unit data herein and may be data transferred from the processor 10 to the memory 20, and FIG. 4 shows an example of 8-bit unit data. 4, a plurality of errors such as a, b, and c may occur in the unit data according to the application state or environment, and such errors may be corrected and corrected by the error correction processing circuit 100 (For example, 2 bits or a predetermined bit value). In this case, it is impossible to correct and process all errors generated in the unit data, and an error such as d may additionally occur as shown in the left drawing of FIG.

Therefore, in consideration of the range that can be corrected and processed by the error correction processing circuit 100 according to the embodiment of the present invention, the error generated in the unit data is corrected and processed. At this time, the range in which errors can be corrected and processed is set by a protection range setting unit 110 to be described later, and is referred to as a protection range. The protection range is closely related to the operating voltage and the variable data length structure. Further, in this specification, a range other than the above-mentioned protection range is referred to as an unprotected range. As shown in the right drawing of Fig. 4, data corresponding to the protection range of the unit data can be referred to as protected data, and data corresponding to the unprotected range can be referred to as unprotected data. That is, the errors (a, b) generated in the protection data are corrected by the error correction processing circuit 100, but the error (c) generated in the unprotected data is not corrected by the error correction processing circuit 100. This is a result of intentionally reducing the length of data that can be corrected and processed by the error correction processing circuit 100, thereby greatly reducing the error occurrence probability.

Hereinafter, a specific operation of each configuration shown in FIG. 3 will be described.

The protection range setting unit 110 sets the protection range of the unit data to be written in the memory 20 according to the operating voltage of the memory 20. [ That is, when an error occurs in predetermined data, and the protection range set by the protection range setting unit 110 includes predetermined data, the error correction processing circuit 100 according to an embodiment of the present invention performs predetermined processing It is possible to surely correct and process errors generated in the data. The protection range set by the protection range setting unit 110 may vary depending on the operating voltage of the memory 20. [ For example, when the operating voltage of the memory 20 is 1000 mV, the protection range setting unit 110 sets the first protection range. When the operating voltage of the memory 20 is 700 mV, the protection range setting unit 110 sets The second protection range can be set, and the second protection range can be smaller than the first protection range.

The encoder 120 performs error correction encoding on the protection data corresponding to the protection range of the unit data, and generates parity data through error correction encoding. That is, the encoder 120 performs the error correction encoding on the protected data in the unit data, and does not perform the error correction encoding on the unprotected data. This may require error correction decoding to be described later only for the protection data for which error correction encoding has been performed, and errors generated in the protection data through error correction decoding can be corrected and processed.

Specifically, the encoder 120 may perform error correction encoding as illustrated in FIG. 5 is a view for explaining the operation of the encoder shown in FIG. In the conventional case, 128-bit unit data can be error-correction-encoded by the encoder 120, and 128-bit unit data and parity data in which error-correction encoding has been performed are generated as in (1). According to an embodiment of the present invention, a protection range is set according to the operating voltage of the memory 20. [ As a result, the protection range of 32 bits and the non-protection range of 6 bits are set out of the 128-bit unit data as shown by (2). The 32-bit protected data corresponding to the protection range is error-correction-encoded by the encoder 120, and the 96-bit unprotected data corresponding to the unprotected range is processed as zero through zero padding, Correction encoding can be performed. As a result, 32-bit protected data and parity data in which error correction encoding is performed are generated.

More specifically, the encoder 120 may generate a code word (codeword) including parity data and data in which error correction encoding is performed by multiplying input data by a generator matrix, as shown in FIG. FIG. 6 is a diagram for explaining the encoding process by the encoder of FIG. 5 in detail. At this time, the parity data may be changed according to the size of the input data and the number of bits that can be corrected. The generator matrix may be composed of an identity matrix for transmitting input data as it is and a parity matrix for generating parity data.

The recording unit 130 matches the unit data with the parity data generated in accordance with the error correction encoding and records the unit data in the memory 20. The manner in which the recording unit 130 records data in the memory 20 or the manner in which the unit data and the parity data are matched with each other can follow conventional methods and is not particularly limited.

The communication unit 140 receives a read signal from the processor 10 that transfers the unit data to the memory 20, and the read signal is a signal for reading or reading the unit data recorded in the memory 20. The communication unit 140 also receives information on the protection range from the protection range setting unit 110. [ At this time, the information on the protection range may be basic data for determining which data in the unit data corresponds to the protected data or the unprotected data, and may be transmitted to the decryptor 150.

The decoder 150 reads the parity data matched with the unit data corresponding to the read signal and the unit data corresponding to the read signal and performs error correction encoding on the basis of the read parity data and information on the protection range And performs error correction decoding on the protected data.

Specifically, the decoder 150 may check whether or not an error has occurred in the protection data in which the error correction encoding has been performed based on the read parity data. Since the parity data is matched with the unit data by the recording unit 130 and is recorded in the memory 20, the decoder 150 can read the unit data corresponding to the read signal and the parity data matched thereto. In addition, the decoder 150 can determine, based on the information on the protection range, which of the unit data corresponding to the read signal is the error-correction-encoded protection data, It is possible to check whether or not an error has occurred in the determined data based on the read parity data. At this time, if it is determined that an error occurs in the protection data on which the error correction encoding has been performed, the decoder 150 may perform an operation of correcting the generated error.

FIG. 7 is a view for explaining the detailed structure of the decoder shown in FIG. 3. FIG.

More specifically, the decoder 150 may include a syndrome generator 151, an error detector 152, an error corrector 153, a controller 154, and a first-in-first-out (FIFO) controller 155.

The syndrome generator 151 may generate syndromes from the unit data recorded in the memory 20 and the error detector 152 may use the generated syndromes and polynomials to generate errors in the error- The position of the bit can be detected. Bose-Chaudhuri-Hocquenghem (BCH) codes may be applied to the syndrome generator 151 and the error detector 152 and the error detector 152 may calculate the polynomial using the Berlekamp-Massey algorithm , And the position of the error bit can be detected using the Chien search algorithm. In addition, the error corrector 153 can correct the error bit by inverting the bit value of the error bit, and utilize the data transferred from the first-in first-out controller 155.

FIG. 8 is a view for explaining the detailed structure of the syndrome generator in the configuration shown in FIG. 7, and FIG. 9 is a view for explaining the detailed structure of the error detector in the configuration shown in FIG.

The syndrome generator 151 may generate the syndrome S from the protection data (a) in which the error correction encoding is performed among the unit data recorded in the memory 20 as shown in FIG. Also, the control unit 154 can control the syndrome generator 151 based on the information on the protection range so as to stop the operation of generating the syndrome for the unprotected data (b). At this time, the unprotected data b may mean data other than the protected data in which the error correction encoding is performed among the unit data recorded in the memory 20. [ For example, the syndrome generator 151 can process a maximum of 128 bits, and the control unit 154 controls the syndrome generator 151 according to how much the protection range for the unit data is 32/64/96/128 bits. Can be controlled. If the protection range is set such that 32 bits in the MSB (Most Significant Bit) are included in the protection data as shown in FIG. 8, the control unit 154 turns off the configuration for the unprotected data b in the syndrome generator 151, And the syndrome generator 151 can transmit a control signal to process the unprotected data b at all times. Accordingly, the error correction processing circuit 100 according to the embodiment of the present invention can minimize the power consumption and the calculation result error.

In addition, the error detector 152 can detect the position of the error bit in the protection data (a) in which the error correction encoding has been performed through the CHN search algorithm of the BCH code as shown in Fig. In addition, the control unit 154 can control the error detector 152 based on the information on the protection range so as to stop the operation of detecting the position of the error bit with respect to the unprotected data (b). At this time, the unprotected data b may mean data other than the protected data in which the error correction encoding is performed among the unit data recorded in the memory 20. [ For example, the error detector 152 may process a maximum of 128 bits, and the controller 154 may control the error detector 152 according to how much the protection range for the unit data is 32/64/96/128 bits. Can be controlled. If the protection range is set so that 32 bits in the MSB (Most Significant Bit) are included in the protection data as shown in FIG. 9, the control unit 154 turns off the configuration for the unprotected data b in the error detector 152, Off, and the error detector 152 can transmit a control signal to process the unprotected data b at all times. Accordingly, the error correction processing circuit 100 according to the embodiment of the present invention can minimize the power consumption and the calculation result error.

The error correction processing method according to each embodiment of the present invention will be described with reference to FIGS. 10 to 12. FIG.

10 is a flowchart for explaining an error correction processing method according to an embodiment of the present invention.

In order to correct and process an error occurring in the memory, the error correction processing circuit 100 or a predetermined circuit capable of performing the same operation sets a protection range of unit data to be written in the memory 20 (S1010). At this time, the set protection range is dependent on the operating voltage of the memory 20 and can be proportional to the operating voltage of the memory 20. That is, in the setting step S1010, the lower the operating voltage, the smaller the protection range can be. In addition, the setting step (S1010) may set the protection range such that the MSB (Most Significant Bit) is included in the protection data.

Subsequently, the error correction processing circuit 100 or a predetermined circuit capable of performing the same operation performs error correction encoding on the protection data corresponding to the protection range of the unit data (S1020). Specifically, the step of performing (S1020) may perform error correction encoding by setting the unprotected data, which is data other than the protected data, to 0 in the unit data. Errors generated in the data within the protection range among the errors generated in the unit data by the zero padding scheme can be corrected absolutely, and errors generated in the data in the unprotected range can be ignored. Since the protection range can be set so that the MSB is included in the protection data as described above, the zero padding scheme can contribute to prevention of a relatively fatal error / error occurrence.

Subsequently, the above-described circuit matches the unit data with the parity data generated according to the error correction encoding and records the unit data in the memory 20 (S1030). Unit data (protection data) and parity data on which error correction encoding has been performed may be referred to as a codeword.

The process of reading the unit data recorded in the memory 20 will be described below. The processes to be described later may be performed after the recording step S1030 described above with reference to FIG.

When reading the unit data recorded in the memory 20, the error correction processing circuit 100 or a predetermined circuit capable of performing the same operation performs error correction decoding on the protection data on which the error correction encoding has been performed . Such error correction decoding is performed based on parity data matched to the unit data to be read and information on the protection range.

In particular, the error correction decoding can be performed by the decoder 150 of the error correction processing circuit 100 described above, in which the error correction processing circuit 100 performs error correction decoding The control unit 154 can transmit information on the protection range. In addition, the read signal including the information on the unit data to be read may be transmitted from the processor 10.

In performing error correction decoding, the above-described circuit can be performed through the following process. First, it is checked whether an error has occurred in the protection data on which error correction encoding has been performed based on the parity data. At this time, if an error occurs in the protection data in which the error correction encoding has been performed, the generated error is corrected.

Specifically, a syndrome is generated from the unit data recorded in the memory 20, the position of the error bit in the protection data subjected to the error correction encoding is detected using the generated syndrome, and the bit value of the error bit Can be inverted to correct the error bit. The error correction decoding can be performed on the error corrected data through the process of correcting the error bit. Then, the above-mentioned circuit to the processor 10 that transfers the unit data to the memory 20 stores the result data of the error correction decoding and the unit data recorded in the memory 20 as unprotected data, which is data other than the protection data on which error- Data can be transmitted.

The error correction processing method according to an embodiment of the present invention will be described with reference to a concrete example shown in FIG. 11 is a diagram for explaining a process of correcting and processing errors generated in the memory when the operating voltage of the memory is 1000 mV and when the operating voltage is 700 mV, respectively.

11 shows a process of correcting and processing an error generated in the unit data in which the conventional circuit has one word data length of 64 bits when the operating voltage of the memory 20 is 1000 mV. The encoder 120 encodes all the 64-bit unit data, and the recording unit 130 records the code words including the encoded unit data and the parity data in the memory 20. Thereafter, the decoder 150 reads the recorded codeword on the basis of the read signal, and performs a decoding process to obtain unit data. However, the error (a) in the code word can occur, and the conventional method can not guarantee correction and processing for the generated error (a), and the unit data finally obtained due to the generated error (a) You may have an error.

11 shows a process of correcting and processing errors generated in the unit data after the error correction processing circuit 100 sets the protection range of the unit data when the operating voltage of the memory 20 is 700 mV. The protection range setting unit 110 sets 32 bits of the 64-bit unit data to the protection range, and the encoder 120 processes the remaining 32 bits corresponding to the unprotected range to zero (zero padding). The encoder 120 error-corrects only 32-bit protected data. Also, the recording unit 130 records the protection word and the codeword including the parity data and the unprotected data in the memory 20, respectively, in which the error correction encoding has been performed. Thereafter, the decoder 150 reads out the recorded codeword and unprotected data based on the read signal, performs a decoding process based on the parity data matched to the read unit data and the information on the protection range, and performs error correction decoding And obtains the resultant data and the unprotected data. At this time, the resultant data of the error correction decoding and the unprotected data are substantially the same as the initial unit data. The error (a) generated in the code word is reliably corrected by the error correction processing circuit 100. The error (b) generated in the unprotected data can not be corrected by the error correction processing circuit 100, but the error correction processing circuit 100 can prevent a fatal error because the bit is relatively less important than the corrected bit .

Meanwhile, each of the components shown in FIG. 3 may be configured as a 'module'. The term 'module' refers to a hardware component such as software or a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and the module performs certain roles. However, a module is not limited to software or hardware. A module may be configured to reside on an addressable storage medium and may be configured to execute one or more processors. The functionality provided by the components and modules may be combined into a smaller number of components and modules or further separated into additional components and modules.

In addition, the memory 20 described above with reference to FIG. 3 may be implemented as a cache, a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Erasable Programmable ROM), an EEPROM (Electrically Erasable Programmable ROM) But is not limited to, a volatile memory device such as a nonvolatile memory device or a random access memory (RAM), or a storage medium such as a hard disk drive (HDD) and a CD-ROM.

Hereinafter, an example in which the error correction processing circuit and the error correction processing method according to the embodiment of the present invention are actually applied will be described.

FIG. 12 is a graph showing the effect that can be obtained through the control as shown in FIGS. 8 and 9. FIG.

The control unit 154 turns off the configuration for the unprotected data b in the syndrome generator 151 as shown in Figure 8 so that the syndrome generator 151 always treats the unprotected data b as 0 A control signal can be transmitted. 9, the control unit 154 turns off the configuration for the unprotected data b in the error detector 152 and outputs a control signal to the error detector 152 so that it always treats the unprotected data b as 0 Can be transmitted. As a result, the power consumption of the decoder 150 can be reduced according to the data length of turning off the power as shown in FIG.

Fig. 13 is a diagram for explaining a position where the error correction processing circuit shown in Fig. 3 can be actually applied on the H.264 circuit and the FFT processing circuit. The block diagram shown in FIG. 13 briefly shows the structure of the H.264 circuit, and the error correction processing circuit 100 proposed in the present invention can be actually applied to a Residual Frame Buffer SRAM, a DCT Buffer, a Quantization Buffer, and the like. The block diagram shown below in FIG. 13 is a simplified illustration of the structure of the FFT processing circuit, and the error correction processing circuit 100 proposed in the present invention can be actually applied to an 8K embedded SRAM or the like. The example shown in Fig. 13 is merely an example that can be applied, and is not limited to this embodiment.

FIG. 14 is a graph for showing a performance change when an error correction processing circuit and the method are applied to the H.264 circuit. Since the H.264 circuit or module performs the image compression operation, the operation quality can be determined through the maximum signal-to-noise ratio (PSNR) of the resultant image. It can be seen that the performance when the method proposed by the present invention (VL-ECC) is applied is superior to the performance when the conventional BCH (Bose-Chaudhuri-Hocquenghem) code scheme (conventional ECC) is applied. It can be seen that the more the operating voltage is applied, the more prominent it is.

FIG. 15 is a graph for illustrating a change in performance when an error correction processing circuit and the method are applied to an FFT processing circuit. The output quality is measured using the Signal to Quantization Noise Ratio (SQNR) while varying the data length in the FFT processing circuit in which 24 bits are one word. It can be seen that the performance of the part corresponding to 24 bits is much higher when the method (VL-ECC) proposed in the present invention is applied than the performance when the conventional BCH code method (conventional ECC) is applied.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: processor 20: memory
100: Error correction processing circuit 110: Protection range setting section
120: Encoder 130:
140: Communication unit 150: Decoder

Claims (16)

In an error correction processing method in a memory,
Adaptively setting a protection range corresponding to an error correction range of unit data to be written in the memory according to an operating voltage of the memory;
Performing error correction encoding on protection data corresponding to the protection range of the unit data and including an MSB (Most Significant Bit); And
And recording the unit data in the memory by matching the unit data with the parity data generated according to the error correction encoding,
Wherein the setting step sets the protection range to be narrower as the operating voltage of the memory decreases.
delete delete The method according to claim 1,
Wherein the performing of the error correcting encoding comprises setting the non-protected data, which is data other than the protected data, to zero among the unit data, and performing the error correcting encoding.
The method according to claim 1,
And transmitting information on the protection range to a control unit of a decoder that performs error correction decoding on the protection data on which the error correction encoding has been performed.
The method according to claim 1,
When reading the unit data recorded in the memory, error correction decoding is performed on the protection data on which the error correction encoding has been performed based on the parity data matched to the read unit data and the information on the protection range Further comprising the steps of:
7. The method of claim 6, wherein performing the error correction decoding comprises:
Checking whether an error has occurred in the protection data in which the error correction encoding is performed based on the parity data;
And correcting the error if an error occurs in the protection data on which the error correction encoding has been performed.
8. The method of claim 7, wherein the correcting step
Generating syndromes from unit data recorded in the memory;
Detecting a position of an error bit in the protection data in which the error correction encoding is performed using the generated syndrome; And
And correcting the error bit by inverting the bit value of the error bit.
8. The method of claim 7,
Performing the error correction decoding on the error corrected data in the correcting step; And
And transmitting unprotected data, which is data other than the protection data on which the error correction encoding is performed, out of the result data of the error correction decoding and the unit data recorded in the memory, to the processor that has transmitted the unit data to the memory. Error correction processing method.
In an error correction processing circuit in a memory,
A protection range setting unit for adaptively setting a protection range corresponding to an error correction range of unit data to be written in the memory according to an operation voltage of the memory;
An encoder for performing error correction encoding on protection data corresponding to the protection range of the unit data and including an MSB (Most Significant Bit); And
And a recording unit for recording the unit data in the memory by matching the unit data with the parity data generated according to the error correction encoding,
And the protection range setting unit sets the protection range to be narrower as the operating voltage of the memory decreases.
11. The method of claim 10,
A communication unit for receiving a read signal for reading unit data recorded in the memory from a processor that has transmitted the unit data to the memory and receiving information about the protection range from the protection range setting unit;
The unit data corresponding to the read signal and the parity data matched to the unit data corresponding to the read signal are read out and the error correction encoding performed on the basis of the read parity data and the information on the protection range And a decoder for performing error correction decoding on the error correction signal.
12. The apparatus of claim 11, wherein the decoder is configured to check whether an error has occurred in the protection data in which the error correction encoding has been performed based on the read parity data, and to correct the error if the error occurs, Circuit.
13. The apparatus of claim 12, wherein the decoder
A syndrome generator to which a BCH (Bose-Chaudhuri-Hocquenghem) code is applied and which generates syndromes from unit data recorded in the memory;
An error detector to which the BCH code is applied and detects a position of an error bit in the protection data in which the error correction encoding is performed using the generated syndrome; And
And an error corrector for inverting the bit value of the error bit to correct the error bit.
14. The method of claim 13,
Wherein the syndrome generator generates the syndrome from the protection data in which the error correction encoding is performed among unit data recorded in the memory,
Further comprising a control unit for controlling the syndrome generator based on the information on the protection range so as to stop the operation of generating the syndrome for unprotected data which is data other than the protection data on which the error correction encoding has been performed, Circuit.
14. The error correction processing circuit according to claim 13, wherein the error detector is implemented using a Berlekamp-Massey algorithm and a Chien search algorithm.
16. The apparatus of claim 15, wherein the error detector detects the location of the error bit in the protection data in which the error correction encoding was performed via the search algorithm of the BCH code,
The error detector may be configured to stop the operation of detecting the position of the error bit with respect to unprotected data, which is data other than the protection data on which the error correction encoding is performed, among unit data recorded in the memory, The error correction processing circuit comprising:

Images