KR101411566B1 - Memory system with multiple striping of raid groups and method for performing the same - Google Patents

Abstract

A data memory system is described which may have asymmetry in the time required to write or erase data and the time required to read the data. Data can be stored using RAID data storage means, and read, write, and erase operations on the module can be arranged such that erase and write operations can be performed without significant delay in performing the read operation. Discloses a method for recovering data of a failed module that can be selected according to a policy that may be associated with minimizing degradation of nonrecoverable data loss probability or delay performance when a memory module failure occurs in a memory system.

Description

[0001] MEMORY SYSTEM WITH MULTIPLE STRIPING OF RAID GROUPS AND METHOD FOR PERFORMING THE SAME [0002]

This application is a continuation-in-part of US application Ser. No. 12 / 079,364, filed March 26, 2008, which is a continuation-in-part of US Provisional Application No. 60 / 920,737, filed on March 29, 2007, 61 / 250,216, each of which is incorporated herein by reference.

The present invention relates to a computer memory system and a method of using the same.

The computer memory system may be of a persistent or non-persistent type. Examples of persistent memory types are magnetic cores, disk drivers, tape drivers, and semiconductor FLASH memory. The non-persistent memory type may be a semiconductor memory such as DRAM. Non-persistent memory types typically have fast access times for both reading and writing of data and are used as computer main memory or cache memory. Data is held in this memory by means that require power, and information stored in memory can be lost if power is lost. Non-persistent memory systems typically have a backup power source that can be a short-lived, dedicated capacitive storage device, or a backup power source using batteries, generators, etc., for long-term data retention.

Persistent storage devices, such as disk, tape, or FLASH memory, are often used to back up long-term data storage that is costly or unreliable, which retains stored data and provides non-persistent data storage devices and continued power even when power is removed from the device. Additionally, because larger amounts of data are stored in persistent data storage devices, the technologies developed have been directed toward cost savings per bit of storage rather than access speed. Thus, many computing systems use different memory types to perform other storage functions where the necessary data is immediately stored in non-persistent storage, can be backed up to a persistent storage device during less frequent data connections, .

Distributed data systems, such as computer database systems, or data centers, or Internet and related storage devices, can store vast amounts of data. Certain aspects of this architecture are now referred to as "cloud" computing. Today, these data storage requirements can exceed 1000 terabytes (1000TB) and are expected to continue to grow. Most of these datasets are substantially larger than the non-persistent storage capacity to be accessed immediately, and when servicing requests from client computers, the response times of servers in the data center can become a serious bottleneck in system performance. Many of these limitations result from the data access time delay of the persistent storage medium. For tape systems, the linear tape must be moved so that the portion of data to be read or written is located at the read or write head. Similarly, for a disk, the head should be positioned so that it is on a data track where a given sector of data is located, and then the disk controller waits until the sector is rotated below the headers where the sector is located. Either of these operations is substantially slower than reading or writing to a non-persistent memory device. These limitations are particularly severe if data single memory locations with random locations in the database need to be read, written or altered.

The time between data request stored in memory and data retrieval from memory can be referred to as latency. Of the persistent memory technologies currently in use, Flash memory has a lower latency than mechanical devices like disks, but has a much larger latency than the currently used non-persistent memory types. The price of flash memory and similar solid state techniques have traditionally been governed by the principle known as Moore's Law, which expresses the general tendency that the capacity of a device during a 18 month cycle is half the doubled price. Thus, it is expected that the unit cost of storing data in the flash memory rather than the disk will soon reach parity.

Although the delay is considerably lower than disk devices, flash memory is still limited in connection time by the way and design of the currently available memory modules. Flash memory is a general term, and various types of solid state devices can be considered as flash memory. There are other developments known in the art, such as NOR-FLASH, NAND-FLASH and so on, followed by Electronically Erasable Programmable Read Only Memory (EEPROM). Each technique has different design, configuration, and other properties for reading and writing data. That is, there may be a limitation on the minimum size of a data block (e.g., a data word, page, or data sector) that can be read or written, or there may be a time difference required to read and write data. In many cases, the time for reading or writing data is not fixed but can vary over a wide range. The memory controller or other such devices must keep track of outstanding requests until they are executed and this requirement makes the data latency variable amounts that can slow down the overall system and reduce the complexity of the hardware and software used to manage the memory . Also, the lifetime of a flash memory device is considered to be subjected to a wear process and is measured in read and write (referred to as "program" in the case of a flash memory) or in an erase cycle. In this specification, the term "write" is used to refer to a "program" when a flash memory is used.

The life cycle of the individual components of the large memory formed from the flash device is sufficiently short in both actual and possible pathological situations so that the wear of the memory is evenly distributed and the error Significant effort may be required, such as performing detection and correction, and displaying bad data blocks.

The concept of RAID (Redundant Arrays of Independent, or Inexpensive, Disks) is at least in 1988 by David Patterson, Gas Gibson, and Randy H.. It goes back to the article written by Cats. RAID allows the disk memory system to be arranged to protect the data contained therein from loss by adding redundancy. In a properly configured RAID structure, the loss of any single disk does not interfere with the ability to access or reconstruct the stored data, but other performance indications may be affected. The Mean Time Between Failure (MTBF) of a disk array without RAID is equal to the MTBF of an individual drive divided by the number of drives in the array because it loses data with some disk loss. As a result, the MTBF of the disk drive array may be too low for many application requirements. However, the disk array can be prevented from failing by redundantly storing information in various ways.

For example, RAID-3, RAID-4, and RAID-5 are variations on the subject. The subject is parity-based RAID. Instead of keeping a full copy of the data as in RAID-1, data is spread across multiple disks with additional disks added. The data for the additional disk may be computed (using Boolean XORs) based on the data for the other disks. If any single disk in the disk set is lost, the data stored on the disk can be recovered through calculations performed on the data on the remaining disk. These runs are less expensive than RAID-1 (mirroring) because they do not require the 100% disk space overhead required by RAID-1. However, since the data on the disk is restored by calculation, there is a performance implication for recovering the data after writing the data and losing the disk. Many commercial means of parity RAID use cache memory to mitigate performance problems.

In a RAID-4 disk array, there is usually a set of four or five data disks plus one extra disk that is used to store parity for data on the other disks. Because the parity disk is updated with all writes, the disk can be a performance bottleneck that slows down all write activity to the entire array.

The principle of RAID is "stripping" in which multiple drives (memory units) are cascaded to one logical storage unit. Stripping involves partitioning the storage space of each drive into "stripes ", which may be as small as one sector (e.g., 512 bytes) or as large as several megabytes or more. These stripes are then interleaved so that the combined storage space consists of stripes from each drive in the stripe. The application environment, I / O, or data intensive type may be a design consideration to determine whether large or small stripes are used.

RAID-5 can be implemented using the same hardware configuration as RAID-4. In the case of RAID-4, the parity block is stored on the same disk for each stripe, so it can be called a parity disk. In the case of RAID-5, the parity blocks for each stripe are stored on a disk that is part of the stripe, but the parity blocks are distributed such that they are distributed essentially evenly across the plurality of disks constituting the storage system. RAID-6 is another enhancement to data protection that involves the calculation of parity across multiple stripes using, for example, columns of stripes as the basis for calculating parity.

The performance of RAID 3 or RAID 4 arrays (equivalent to level 0) can be advantageous for reading. However, writing requires that the parity data be updated each time. This is especially true for large write or sequential writes, which is quite fast, but slows down small random writes. Because only one drive in an array stores redundant data, the unit price per megabyte of a RAID 4 array can be quite low. The distribution of data across multiple disks can be managed by dedicated hardware or software. In addition, there are hybrid RAID architectures that are partially software and partially hardware-based.

Conceptually, the organization of data and error correction parity data is shown in FIG. 1, where in one block (A) data is striped across three disks as data sets A1, A2, A3, Ap is on the fourth disk and the parity data set Ap is generally calculated as the exclusive OR (XOR) of the data sets A1, A2, A3. Then, as is known to those skilled in the art, one of the data sets A1, A2, A3 or Ap may be reconstructed into another three data sets. Thus, errors in any one of the data sets representing, for example, a failure of one of the disks may be corrected by use of other data sets.

The error correcting code (ECC) is generally an automatic detection or correction of the departure from this calculation in the received or recovered signal indicating an error since each data signal is an algorithm that complies with certain calculation rules. ECC is used for computer data storage, such as dynamic RAM, FLASH memory, etc., and for data transfer. Examples of ECC include Hamming codes, BCH codes, Reed-Solomon codes, Reed-Muller codes, binary Golay codes, convolutional codes, and turbo codes. The simplest error correction code can correct single bit errors and detect double bit errors. Other codes may detect or correct multi-bit errors. ECC memory provides greater data accuracy and system updates by protecting against errors in computer memory. Each data set A1, A2, A3, Ap of the strip data may have an associated error correcting code (ECC) data set attached thereto and generally stored on the same disk. When data is read from the disk, the integrity of the data is verified by the ECC and one or more errors can be detected and corrected, depending on the ECC used. In general, the detection and correction of various errors is a function of the ECC used, and the selection of the ECC depends on the requested data integrity level, processing time and other costs.

A memory system including a plurality of memory modules each having a data writing and reading capability is disclosed. The module group of the plurality of modules is configured so that the data stored in the module group can be read without blocking related to writing or erasing of data from any one of the modules of the module group.

In yet another aspect, a memory system includes a plurality of memory modules each having data writing and reading capabilities. One module group including the plurality of memory modules stores user data and parity data for the user data. Wherein the write or erase operation of the module group is configured such that at least one of at least one of all user data or sufficient parity data for reconstructing the requested user data is requested at the time of a read request, Is less than the time interval in which one of the module groups is in a write or erase state.

In yet another aspect, a memory system has a plurality of memory modules each having data writing and reading capabilities. Wherein a group of modules comprising the plurality of memory modules stores user data and parity data for the user data, and the write or erase operation of the module group includes at least all user data or all user data and for reconstructing user data At least one of the sufficient parity data is read without encountering a time delay due to erase or write operations performed on the module group. Data allocation to the module includes allocating address groups for a memory module to a RAID stripe according to a pattern of occurrences in the logical address space.

In yet another aspect, a memory system has a plurality of memory modules each having data writing and reading capabilities. A module group including a plurality of modules is configured such that a write operation performed on the module group is limited to be performed in a time interval in which a plurality of write operations overlap.

Wherein the group of the plurality of memory modules is controllable to operate to perform a write or erase operation at only one of the memory modules at any time; A memory module including parity data of user data so that it can be read by one of reading all user data from a memory module not performing an operation, or reading less than all user data from a memory module not performing a write or erase operation And storing the user data file for the group of the parity data, wherein the memory module storing the parity data does not perform a write or erase operation.

In another aspect, there is provided a method comprising: providing a plurality of memory modules, the group of memory modules being controllable to operate to perform a write or erase operation at only one of the memory modules at any time; To read all user data from a memory module that does not perform the write or erase operation, or to read all user data from a memory module that does not perform a write or erase operation, And storing a user data file for a group of memory modules including the parity data, wherein the memory module for storing parity data stores data in a memory system that does not perform a write or erase operation.

Are included in the scope of the present invention.

Figure 1 illustrates a RAID 4 data storage system for a plurality of disk drives (prior art).
Figure 2 shows a plurality of memory modules arranged in a matrix storage array.
3 is an example of a data structure for array A stored in a plurality of memory modules.
Figure 4a shows an arrangement of memory modules arranged in three architectures, in which the memory modules are located on the ribs at the end of the branch.
FIG. 4B illustrates an arrangement of memory modules as in FIG. 4A, where memory modules are located in a branch in a logical data stripe.
5 is a schematic arrangement of data in a RAID memory.
6A shows a time sequence of a write operation for a RAID stripe.
FIG. 6B shows the relationship between the write and read operations for the sequential time intervals of FIG. 6A.
7 is a block diagram of a memory module.
FIG. 8 shows a group of memory modules in which each module belongs to one or more RAID groups, and the RAID group is striped in various ways across the modules.
Figure 9 illustrates a RAID array in which an intra-group address sequence can not be contiguous.
Figure 10 shows a stripe of length 5 oriented with a logical address space of dimensions 5x5 and a slope of 0 (rows per column).
Figure 11 shows a stripe of length 5 oriented with a logic address space of dimension 5x5 and -1 slope.
Figure 12 shows a stripe of length 5 oriented with a logical address space of dimensions 5x5 and a +1 slope.
Figure 13 shows a stripe of length 5 oriented with a +2 slope and a logical address space of dimension 5x9.
Figure 14 shows a stripe of length 5 oriented with a logical address space of dimension 5x9 and a -2 slope.
Figure 15 shows a stripe of length 5 oriented in line with a column with a logical address space of dimension 5x5.
Figure 16 shows a stripe of length 5 oriented with a -2 slope, shown as wrapping a stripe at the array boundary, with a logical address space of dimension 5x5.
Figure 17 shows a stripe of length 5 oriented at a +2 slope, shown as wrapping a stripe at the array boundary, with a logical address space of dimension 5x5.
Figure 18 shows a stripe of length 5 with a stripe of 0, +/- 1, +/- 2 through a logical address space of dimension 5x5 and (3, 3).
Figure 19 shows a stripe of length 5 with a stripe of 0, +/- 1, +/- 2 passing vertically through the logical address space of dimension 5x5 and (3, 3).
Figure 20 shows a stripe of length 5 with a stripe of 0, +/- 1, +/- 2 passing vertically through a logical address space of dimension 5x5 and (3, 3) with stripe patterns having different widths .
Figure 21 shows a stripe of length 5 with a logical address space of dimension 5x3 and a stripe of -1 slope.
Figure 22 shows a stripe of length 5 with a logical address space of dimension 5x7 and a stripe of +2 inclination.
Figure 23 shows a logical address space of dimension 5x5 where the generation function of Figure 18 is located in each row of column 3.
Figure 24 shows a logical address space of dimension 5x5 where the generation function of Figure 18 is located at (1,3).
Figure 25 illustrates a logical 5x5 logical address space using another example of generation function.
Figure 26 shows a logical address space of dimension 5x5 according to the generation function of Figure 25 located at (1,3).
Figure 27 shows a logical address space of dimension 5x5 according to the generation function of Figure 18 located in each matrix of the array.
Figure 28 shows a logical address space of dimension 7x7 according to the generation function of dimension 5x7.
Figure 29 shows a logical address space of size 7x9 according to the generation function of dimension 5x9.
Figure 30 shows a logical 5 × 7 logical address space where stripes are assigned to Application AF to be a specific data loss pattern.
Figure 31 shows a logical address space of size 7x7 with left diagonal striping.
Figure 32 shows a logical address space of size 7x7 and the last generated wrap-around pattern in which the logical address ranges of the stripes are incremented by two columns between address ranges.
Figure 33 illustrates a logical address space of size 7x7 and the last occurring wraparound pattern in which the logical address ranges of the stripes are incremented by two columns between address ranges.
Fig. 34 illustrates the striping pattern of Figs. 31-33, where a larger increase is used to generate the total stripes.
Figure 35 shows the distribution of the stripes common to the logical address space (1, 4) of the array address of size 7x7.
Fig. 36 shows the striping pattern of Fig. 31 as a pattern of occurrence for a total of 48 stripes.
FIG. 37 shows the distribution of the stripes passing through (1,1) in FIG.
38 is a view similar to FIG. 36 with an address range increase in stripe 5.
FIG. 39 shows the distribution of the stripes passing through (1,1) in FIG.
Figure 40 illustrates the use of many other striping patterns to more widely distribute the stripes passing through the module over the logical address space.
Figure 41 shows a 6x10 logical address space with stripes of 0, left diagonal, right diagonal slope.

While the illustrative embodiments are better understood with reference to the drawings, these embodiments are not intended to be limiting in nature. Elements of the same number in the same or different figures perform equivalent functions. Elements may be represented by numbers, acronyms, or both, and the choice between representations is merely for clarity, and numerical elements and the same elements represented by double letters or alphanumeric identifiers should not be distinguished on this basis.

It is understood that the above-described methods and apparatus illustrated in the figures may be constructed or implemented with machine-executable instructions, e.g., software or hardware, or a combination of both. The machine-executable instructions may be used to cause a general-purpose computer operating on the instructions, a special-purpose processor such as a DPS, or an array processor, to perform the functions described herein. Alternatively, the operations may be performed by special hardware components that may have hardwired logic or firmware instructions to perform the described operations, or by any of the programmed computer components and custom hardware components that may include analog circuitry Can be performed by a combination.

The methods may be provided as a computer program product that may include, at least in part, a non-volatile machine-readable medium having stored thereon instructions that can be used to program a computer (or other electronic device) to perform the methods. For the purposes of this description, the term "machine-readable medium" may refer to any device capable of storing or encoding a data or instruction sequence for execution by a computing device or special purpose hardware, But should be construed as including any medium capable of performing one. Thus, the term "machine-readable medium" should be interpreted to include, but is not limited to, solid state memories, optical and magnetic disks, magnetic memories, and optical memories as well as any equivalent devices that may be developed for this purpose do.

For example, and not by way of limitation, the machine-readable medium may comprise read only memory (ROM), any type of RAM (e.g., S-RAM, D-RAM, P-RAM), PROM, EPROM, magnetic random access memory, magnetic disk storage media, A flash memory, a memory resistor, or an electrical, optical, acoustic data storage medium, etc., which may be configured. A volatile memory device, such as a DRAM, may be used to determine a computer program product if the volatile memory device is part of a system having a power source, and the power source or battery is configured to power the circuit for a period of time during which the computer program product is stored in the volatile memory device. .

Often, data is managed in the form of logical arrays as data structures. However, the same logical array may be associated with a physical memory array having the same or different configurations. The operation of many examples is described herein as if it is a direct match between the logical data structure and the physical device, but it can not be an actual arrangement, and assigning data to a memory location may be used to determine the structure of the memory system, Missing memory locations, wear-leveling considerations, and the like. This allocation of data to physical locations can be accomplished using a PCMCIA Flash Translation Layer (FTL) or Linux Journaling FLASH File System version 2 (JFFS2), Aleph One Yet Another FLASH File System (YAFFS), or Sun ZFS (Sun Microsystems) , And other file systems known to those skilled in the art, or may be developed to perform similar or equivalent functions.

 The relationship between logical and physical addresses in the interpretation of the embodiments described herein can be assumed. The choice of one or the other for discussion is a matter of convenience and is not limited unless specifically stated. As such, the data stripes of the RAID-configuration memory may be mapped to any of the actual memory locations in the memory system. Thus, the constraints on erase, write and read operation timing must be interpreted for data in one stripe whenever such a stripe is located in the memory system. That is, the terms memory module, memory location, data block, and the like can generally be used interchangeably and effectively. The structure or method of interconnecting memory elements is not intended to be limited by the present disclosure. Moreover, the physical memory may be implemented as a plurality of modules, a single module, or a single substrate, for example.

Further, in the art, software is typically said to operate or produce results in one form or another (e.g., a program, procedure, process, application, module, algorithm or logic). These expressions are a convenient way of telling a processor of a computer or equivalent device to perform an operation or to produce an outcome by simply executing the instructions of the software by a computer or equivalent device, as is well known to those skilled in the art.

In describing a particular example, the example may include a particular feature, structure, or characteristic, but not necessarily all examples should include a particular feature, structure, or characteristic. This should not be construed as an offer or intention that the features, structures, or characteristics of the two or more examples should not be combined or combined, except when the combination is expressly excluded. Where a particular feature, structure, or characteristic is described in connection with the example, those skilled in the art, whether expressly described or not, may implement such feature, structure, or characteristic in conjunction with other examples.

The memory array may be comprised of memory elements different from the disk drives. For example, the memory array may be formed of a plurality of flash memory modules or other semiconductor memory devices, which may be volatile or non-volatile memory devices. In the present specification, examples using flash memory circuits as memory devices of a memory system are provided, but they may be developed for the same or similar functions, either alone or in combination in the design or configuration of a memory system as described above or below But is not intended to exclude the use of any form of such persistence or non-persistent memory.

As a first example, a RAID 4 structure that does not imply that other RAID structures are excluded is used. Indeed, the number of RAIDs (3, 5, 6, etc.) is a useful simple way of describing a storage system, but they are neither precise nor distinguishable for such systems. A RAID 4 system with only two storage components is also a RAID 1 system. A RAID 4 system with a common stripe size is a RAID 3 system. A RAID 3 system does not exclude the use of rotational parity of a RAID 5 system. In addition, any RAID system may have additional attributes such as parity or delta logging that do not match the RAID number. Others, such as RAID 6, indicate that more than one bit of parity can be used, but do not indicate as many as many parity executions are intended. Thus, it should be appreciated that the use of RAID numerology herein is purely exemplary and should not be construed as limiting the applicability of the described techniques. The choice of RAID structure is an engineering and economic judgment based on criteria such as cost, reliability, read or write latency, power consumption, and data recovery rate. Those skilled in the art will appreciate that the systems and methods shown in this example may be employed to improve the performance of a RAID system in one or more of the following operations (including erasing data) or data writing operations in response to a user request or housekeeping operation .

Flash memory has a finite lifetime. Failure of the flash memory can be broadly divided into conventional failure modes associated with defects in configurations that are potentially or over time manifested and representative electronic components and wear mechanisms are considered. In general, depending on the particular technique, the read or write may be a wear mechanism, but the wear mechanism is associated with the number of times the flash memory module is connected for erase operations. As is known for electronic failure mechanisms and the number of miles the vehicle is driven, this can be considered as a more representative mechanical failure mechanism. Both mechanisms may need to be considered in system design, and the abuse of a particular memory location may need to be prevented by hardware or software management of system operations.

When a flash memory is used, the wear-time failure mechanism may be a single bit error in the data array. This single bit error can be detected and corrected by an error correction code (ECC) associated with the data set in a particular memory module. The calibrated data is then transmitted to the memory controller and combined with the data read from the other stripes to form the requested data set (A). The data retrieved from the stored data subset (A1, A2, A3) has no errors or the errors are corrected by the ECC, thus duplicating data from the data set Ap. The data set Ap needs to correct the data of the data set A only when one of the data sets A1, A2, A3 is detected, for example, due to a memory module failure, but has an uncorrectable error. These multi-bit errors need to be reconfigured if, for example, the memory module itself fails and the data of the data set A is reconstructed using the remaining three data sets (the other three of the data sets A1, A2, A3, Ap) Will occur. For the sake of design, the occurrence of this type of error can be regarded as being characterized by an electronic mean time between failure (MTBF) between a single memory module or disk. In general, only data in stripes A1, A2, A3 are used and parity stripes Ap are retrieved and used only for data reconstruction when a failure occurs.

In one aspect, in a flash memory system, when a single bit error is reported in data stored in a memory module, the flash memory module may be considered unreliable, and the memory controller may be configured such that, Quot; mark " or the position of the memory module can be recorded. Alternatively, a predetermined number of single-bit or multi-bit errors may be allowed to accumulate before a memory module or memory circuit is deemed unavailable and a repair operation may be performed.

Some of the features of some flash memory technologies may make the writing and reading of small blocks of data somewhat impractical, and the size of the block to be written may be smaller than the minimum block size that the memory system can write or erase Can occur. For example, a software system may split files into block sizes of 512 bytes; However, the minimum actual erase size for the memory system is 128 Kbytes.

The four 512 byte data elements may be considered to constitute a 2K byte page together. Referring to the flash memory using an analogy to the disk structure, such a group of contiguous memory locations may be referred to as a "sector" even though no rotating medium is included at all. In general, the term "block" when referring to any type of data is used to refer to a group of data that may be associated with a particular description, rather than intended to mean a particular size in bytes or any other unit.

When a RAID 4 system is used, a sector of a 2K data page containing 512 bytes may be striped across four memory modules while a fifth memory module is used for parity data. In this example, it is assumed that a 512-byte sector size, the use of 5 memory modules to store aspects of page and parity data, and a minimum erase size of 128K bytes for each memory module, It should be understood that this does not imply any particular limitation of the method.

2 illustrates a memory system including a plurality of memory modules, wherein the memory modules are connected to the memory controller via a bus. Each bus has a plurality of memory modules connected in a serial bus configuration and has a configuration which can be regarded as equivalent to the configuration of the disk of the disk array of Fig. In addition to representing the physical arrangement of memory modules, this arrangement may be regarded as a logical address space for memory modules having different physical configurations.

Fig. 3 shows the configuration of the memory locations corresponding to the data array A, wherein the data array size can be considered to be a multiple of the sector size that can be created in the memory device. Each memory module is composed of a plurality of 512-byte memory sectors and has an Amn-designed erase block size of 128 Kbytes, where m is a memory bus where the memory module is located and n is a 512-byte sector ≪ / RTI > In this example, there are 256 sectors of 512 bytes in each 128K byte erase block of the memory module. The memory module may comprise a plurality of erase blocks.

Thus, a 512-byte data block can be written to the sectors A11, A21, A31, A41 and the parity sector Ap can be updated by calculating the exclusive OR in the data arrays A1, A2, A3, and A4. When data is written to the sectors A11, A21, A31 and A41, for example, data included in the sectors A12-A1n of the memory module 0 may also be written. This may require that the data in array Al change to sector A11 or be erased before writing new data. An example of this operation is to read the data array A1 in the non-persistent memory device, to erase the memory associated with the data array A1 in the memory module 0, and to delete the data array A1 in the memory module 0 Writing data in array A1 to memory module 0 from non-persistent memory, and then modifying the data in sector A11. This shows an example of an operation that can be performed in the process of changing data stored in the flash memory. Housekeeping operations of the flash memory system will not be described herein. Such housekeeping operations may include checking for bad blocks, wear leveling, data merging to regenerate memory locations ("garbage collection"), error detection and correction, This behavior can be viewed as overhead, reducing the capacity or system bandwidth for writing or reading and also increasing latency. In the examples herein, the operation of the flash memory is described at the macroscopic level, and any internal operation that is substantially transparent to the user is presumed to occur without any further explanation. However, if a limitation of the read or write operation of the memory is claimed, the housekeeping operation may generally be subject to restrictions on external reads or writes, but if necessary, execution may be given priority over the allowed time intervals . Internal operations such as "read" or "write" that may need to accomplish an external command may be performed during a period assigned to read and write, although these operations may be a combination of read and write internal operations. This should not be construed as excluding housekeeping operations performed at any time, and preferably housekeeping operations may be stopped to achieve the user's requirements. In one aspect, a housekeeping operation that requires reading data may be performed on a memory circuit in which external read operations are temporarily suppressed.

In one example using currently available single level cell (SLC) NAND flash memory components, data transfer into a 2K byte flash chip between the flash memory and an internal data register may take approximately 25 microseconds for a read operation. The transfer of 512 bytes from the internal register to the device controlling the flash can take about 20 μs at a rate of 25 MB / s on the bus used to connect to the flash chip by the controller on the memory module, It takes. However, the time to perform the erasure of the 128 KB erase block of flash to allow new data to be written can take from about 1 msec to about 2 msec, which is about 20 to 40 times the time to perform the read operation. Performing the program (write) operation of the flash may take about 20 μs to transfer 512 bytes of data on the bus to the internal registers of the flash chip and about 700 μs to about 200 μs to program the data into sectors of the flash memory , Which is about 5 to 15 times the time it takes to perform the read operation. It may take from about 13 ms to about 42 ms to erase the 128K block and to program the 128K block, or about 200 to 800 times the time to perform the read operation. During a period of time in which the memory module is involved in an erase or programming (write) operation, the memory module can not perform other functions, such as reading any of the other sectors A12 through A1n. The data desired to be read is in the same device of the erased or programmed module. Thus, during a time period, read operations, which may be irrelevant data stored in the same memory array block A1, may be excluded (inhibited) when a write (program) operation or an erase operation is in progress when a read request is received have. In many database systems, such delays as delays are undesirable and unacceptable. The time delay can be compared to the time delay encountered on the disk storage medium.

The example for SLC uses a specific time period for execution of various instructions. These are now common production devices and are expected to evolve faster or slower depending on development goals. For example, multi-level cell (MLC) flash technology generally has a longer time period for executing instructions while providing a larger spatial memory density.

In the situation where the asymmetry between the read operation time and the write operation time for the data sector is intended to be faster for the data write than for the data read operation, the operation of writing the 2K byte block striped across the four memory modules and the parity module The read operation in which data up to 30K can be read during the write operation cycle may be blocked. Likewise, an erase operation can block a 160K read operation at about 80K of data.

This situation can be mitigated by the operation of the memory controller and memory module so that the data is written sequentially to one or more sectors of 512 bytes in each memory module (Al, A2, A3, A4 and Ap) rather than simultaneously. Thus, a write operation to array A1 is allowed to complete before beginning a write operation to A2, and similarly, a write operation to A2 is allowed to complete before beginning a write operation to A3. This continues until all memory modules are finished in the stripe (A), including calculation and writing of the parity to the module (Ap). During the time each module of the modules including the data arrays Al, A2, A3, and Ap is written, the particular data array associated with the module can not be read. However, in this example, only one of the modules Al, A2, A3, A4 and Ap can perform a write operation at any one time.

For example, if a read command is issued for 512 bytes of data stored in modules Al1, A21, A31, A41, and Ap, each memory module may receive a read request. The memory modules may be in a state where the read request is immediately processed and the data can be returned to the memory controller. However, when the write (or erase) command is processed by the memory module, the data can not be read immediately from the memory module and thus one of the responses from the data arrays Al, A2, A3, A4 and Ap is substantially delayed . In the situation where the module Ap is used only for data recovery, the module Ap can not be read unless there is a memory failure. Since the general memory management hardware or software is expected to have a response from all appropriate memory modules A1-A4, if one or more of the memory modules are written due to either an external command or housekeeping operation, Can be delayed.

However, in the situation where there are four memory modules including data and one memory module including parity data, it may be necessary to return data so that only four of the five modules can recover certain data. That is, one of the data modules may fail, report an unrecoverable error, or be interrupted by a write or erase operation. For example, if the data module that does not return the data is A2, the remaining data modules may be Al, A3, A4 and Ap, in which case a predetermined 512 bytes may be searched. If data from one of the modules Al, A2, A3, and A4 is lost, data from the module Ap that is parity data may be used to recover the data of the lost or delayed response module.

When the data stored in the memory module A1 is read, for example, the data can be verified using an error correcting code, and the data ECC1 can be stored in the same module as the data. Once the read data is corrected, no action need be taken. If an error is detected, the error can be corrected and the number of errors that can be detected or corrected is a characteristic of the particular error correction code (ECC) used. As it is returned to the memory controller, the read data is corrected or corrected by the ECC, or if the ECC can detect the error (s) but can not correct the error, it is marked as erroneous.

Generally, in a flash memory system, a single fault is caused by a wear phenomenon, or a memory module has a large number of failures of a type that can be detected by the memory controller. The memory module may not be operated.

In the event that a single error is reported but an error is not detected by the ECC, the occurrence of the error may be reported to the memory controller, including on-chip memory management, or other hardware or software used to manage the flash memory system, A particular chip or data block may be marked as defective or may be monitored for other correctable errors. The memory management algorithm can determine that the memory module or chip can no longer be used for data storage. The data currently stored in the memory module or chip is moved to another memory location that is not marked as defective.

Alternatively, if the entire memory module is defective due to, for example, a large hardware failure, it is determined that data from the data arrays Al, A2, A3, and A4 is missing or has an error. The data from Ap can be used to reconstruct the data of the fault module and the reconstructed data can be stored in the module where the fault is not indicated. Alternatively, if Ap is in error, the data from the data arrays Al, A2, A3, and A4 may be used to reconstruct Ap. Therefore, data integrity is maintained even when a large-scale hardware failure occurs.

If the data is known to have been corrected or the error has been corrected by the ECC, the predetermined data may be stored in the memory controller < RTI ID = 0.0 > ≪ / RTI > For example, data may be received from the memory modules Al, A2, A3, and A4. Then, the data from the module including Ap is redundant because it is not necessary to determine the accuracy of the data in the predetermined data or it is necessary to correct the error. In a situation where either one of the modules with data arrays Al, A2, A3 and A4 returns no data, returns data known to be incorrect, or the data is delayed, Can be used to reconstruct lost data using parity data and the remaining three data arrays. If the term "no data returned" is used, the criterion may be that no data is returned within a certain time period, for example, which is a general read operation. The longer time to recover the data may be due to an interference write or erase operation or a hardware failure. Data from the "no data returning" module may be allowed to be returned later or may be a read operation to an erased module. In any case, the time to retrieve data from a data stripe by a module that fails to return data within a reasonable time frame may not be extended accordingly.

Thus, in an array of memory modules, if one of the memory modules is used for redundant data (e.g., parity data), then all memory modules need to return valid data before the requested data becomes available or the data is reconstructed none. That is, for example, when the data is read from the modules Al, A2, A3, and Ap, the requested data becomes available. Data from A4 may not be needed.

Data from A4 may not be available or may not be available in a timely manner because the data is being written to some sector of A4 which may delay reading data from the written block or erase the block, Is impeded by the connection feature of the memory device. Data from four of the five memory modules is made available at one time after receipt of a read request characteristic of the read time. Data from the fifth module can be made available in a timely manner if the data from the fifth module can be ignored without a write operation in progress, except in the case of an incorrect error. If the data is substantially delayed, the delayed data is redundant and can be ignored in routine processing of data in the memory controller.

In one aspect of a five module configuration in which at least one module has parity data for the stripes stored in the other four modules, only four memory modules (locations) known to be able to read data immediately Can be lowered. The fifth read command may be omitted. However, there are situations where the fifth read command is issued even if the data from the fifth module is not to be used under normal circumstances. These commands can be explicitly canceled or canceled at any level in the memory system when the time-out interval is exceeded. This pending read command can prevent data from being erased during the interval between determining that the previously received data is erroneous and the time when the request for the fifth data block used for reconstruction can be effected.

In one aspect, the read command may only be issued to a memory module known to be capable of immediately reading data due to sequential write or erase constraints or some other constraints. Other read commands may be omitted. However, there are situations in which data from other modules can be placed into a save order if they are not to be used under normal circumstances instead of another read command issued. Such an instruction can be explicitly canceled or canceled at any level in the memory system when the time-out interval is exceeded. This pending command can prevent data from being erased during the interval between determining that the previously received data is erroneous and the time at which the request for another data that can be used for reconstruction can be applied. The retention command may be used to prevent erasure or loss of data by any of a number of methods.

When a continuous write is commanded to an address that is the target of the save command, the module can read the existing data before writing new data. In one aspect, the module can track the location of the old data before writing the new data to the new location, thus having the ability to read the old data if necessary. The write command is delayed at the same address until the retention command is canceled or time-out by the retention command. To retrieve data protected by a save command, a special read command may be used to retrieve the old save data for a given address, as opposed to the most recently written address value. There may be a number of prominent retention commands for a single address and some of the preserved data may be read and written to consecutive series of writes to an address that may be stored in volatile memory that has not yet been sent to non-volatile storage.

Thus, for example, since the reading of four of the five memory modules is not corrupted by the write operation to four of the five memory modules read, the data from any four of the five memory modules in the stripe has a low delay Can be used to read the data stored in the stripe in time.

The process of managing memory in a memory system in which the read and write times are asymmetric and the write time is substantially longer than the read time may involve writing data to the plurality of memory modules and the memory modules are configured in a logically stripe pattern . Each memory module may have an error correction code for the data in the memory module, and the additional memory module may have an error correction code (e.g., XOR parity) for the data in the plurality of modules. Write or erase operations may be performed, for example, by sequentially reading or erasing data to each of the memory modules, and a write or erase operation to each successive module is delayed until the write operation to the previous memory module is completed. When the write or erase operation is completed for each memory module, the redundant data in the additional module is updated so that data integrity is maintained. Thus, only a single memory module can be in a write state at a time. Alternatively, the redundant data may be updated to non-persistent storage until the writing or erasing of the modules containing the data is complete, and then the data is written to the additional module. Non-persistent storage can be local to the module or more global.

Write or erase operations are sequentially performed on the memory modules in the stripe, only one of the memory modules in the stripe is immediately blocked from the data journal in response to the read request, in this example at least four of the five memory modules Immediately returns the data to the memory controller. This is sufficient to complete the read operation using parity data, if appropriate. Thus, since only one module associated with a stripe can be in a write or erase state at a time, the overall speed of a write or erase operation may be reduced depending on the mix of timeline loading and operation, but the read operation may be a write or erase operation . The non-overlapping period of time to actually write data to the memory module minimizes the conflict between read and write operations to the data stripe.

The memory controller may wait for a period of time to complete the read operation and then use at least four of the five responses to assemble the requested data sectors, either data or reconstruction data. If all five of the data blocks are returned, one data block may be ignored, or the redundant data may be used as an additional error detection step depending on the data reliability level desired at design time.

The term memory module is used in a general sense, and a physical memory module may have a plurality of memory devices, such as a flash chip, each one of which may have the characteristics of a "memory module ". Thus, even if these memory devices are in a higher level memory module, the sequential operation of the memory device to perform the write operation is performed.

The description herein generally uses five memory modules as examples, four of which store data and a fifth memory module stores parity. However, more or less than four memory modules may be used for data storage, and one or more memos may be used as storage for parity data where the module is connected to other memory modules. Whether the memory module contains data or not, the parity data, or a combination of both, is not intended to be a constraint.

The writing of data may be prioritized, for example, in an initial population of data in a previously unused memory system, the data may be written to a plurality of memory modules at the same time in a stripe, and the reading of data may be delayed But this may be acceptable when initializing large arrays or moving blocks of data. In this example, the data write speed is about 20 percent of the maximum write speed as each of the five memory modules is written sequentially, while the read speed is a single It is not longer than the expected read speed for the module. Write blocking can be managed as the write load increases.

In another example, the configuration of the memory array may be different from the matrix matrix as in the previous example. The matrix representation of the above-described data can be understood as a logical address mapped to, for example, a logical address and a physical address. In the memory structure of FIG. 4, the memory module consists of a tree taught by the inventor in U. S. Patent Application Serial No. 11 / 405,083, filed April 17, 2006, entitled " Interconnection System " It is incorporated by reference. In the arrangement of this example, the tree-like structures may be interconnected and may have external connections to one or more memory controllers. The attributes of the tree system as shown in FIG. 4A are such that if one of the memory modules fails completely, either one of the physical links is ruptured, or one of the memory controllers fails, (shown as a square box) One of the memory modules may be connected by at least one of the memory controllers. As such, the individual memory modules M can be assigned to the data array A regardless of the details of the physical location of the memory modules in the system. (In this example, the memory module indication M is replaced with the associated data array indication A for simplicity). The tree structure may be formed to include a large number of memory modules and each module may be relatively close to the root in terms of the distance a signal may travel as compared to a linear structure having a similar number of memory modules and memory controllers Can be.

By way of example, the data array A is shown as an example of the allocation of the memory system of Fig. 4A to a physical module, which is one of many possible allocations. The allocation of the data array to the memory module may be changed taking into account the failure of one or more memory modules without significantly affecting the delay time or other performance measures. An attribute of a tree memory system having a redundant interconnect structure is that individual memory modules can be replaced while the memory system is in operation. This can be referred to as "hot swapping ".

Figure 4B shows another possible allocation of data arrays A1, A2, A3, and Ap to other physical memory modules in the memory structure of Figure 4a. Here, the modules are selected close to each other using some of the same data paths or data paths between the memory modules and one of the memory controllers. If one of the memory controllers or memory modules fails, other paths (some of which are shown as dashed lines) may be used to connect the memory module to the original controller or other controller. As such, the combination of the logical representation of the data array A with the physical module is flexible. Redirecting any part of the data array A for a location in the memory system is a change to the logical-to-physical mapping and data routing, But mainly by the validity of the physical memory module.

If a memory module needs to be replaced or eventually replaced, there is a possibility that a second failure may occur during a single failure time period. The failure mode of the memory module can be divided into a wear mode and a conventional electronic circuit mode. The electronic circuit method depends on the total operating time, and the wear method depends on the use of the memory module. A wear-out fault is gradual with a single-bit fault correctable as an internal fault. In such a case, the first module may be replaced and the second module failure probability may be evaluated to be the inverse order of the MTBF of the memory system divided by the number of times required to replace the fault memory. Likewise, if the cause is electricity, the wear failure is unlikely to cause a failure for a short period of time to replace the fault memory module, and the likelihood of second failure is likewise small. Because the system described above is RAID 4, data loss occurs if the two memory modules of the time overlapping failure among the five memory modules, including the data and the parity array, occur before repair or modification of the RAID stripe.

The erroneous state of the flash memory causes an erroneous state. Wear patterns can vary between different types of flash memories and manufacturing techniques used by individual manufacturers. However, various strategies have been developed to manage the wear of the flash memory, since the wear of the flash memory causes the equipment to fail, the system to crash, and the data integrity to be lost. As the number of write or erase cycles of each block of data is often recorded and the number of write cycles increases, the data may be transferred from the high use area to the low use area to increase the life of the memory module. The specific failure mode of the flash memory module due to wear is that a single bit is in an error state. The bit tends to remain an error in repeated read operations until the second bit also indicates an error. Since the error correction code (ECC) that can be used has the ability to detect and correct a single error, and the ability to detect and correct, for example, double errors, the memory module can continue to be used until a two bit error occurs . If a two bit error is encountered, redundant parity data is required to reconstruct certain data. Therefore, other system management policies may be used.

With a first policy, the memory module may be marked as unused when encountering a single bit error. Since a single bit error is corrected by the ECC associated with the memory module, redundant data associated with the stripe (e.g., parity data) need not be used. Since only four of the five modules in the previous example may suffice to represent the given data, the read operation is not delayed by waiting for the write operation to complete. Alternatively, the memory module may continue to be used until a second bit error is detected in the data array of the memory module. In this situation, redundant (parity) data may be used to reconstruct the data if a memory module other than the memory module containing the redundant data fails.

Compared to a disk system using multiple disks, a solid state memory system can connect to a data array stored in a plurality of memory modules, substantially free of interference between read and write or erase operations, or between various operations of the same type.

In another example shown in Fig. 5, management of a two-dimensional data array is shown. If a RAID-4 system is operated so that only one of the five memory modules (A1-Ap) is allowed to be in write mode at any time, the remaining four memory modules will have a delay of less than 20 percent write operation Immediately return data to avoid damage. This situation contrasts with a system that does not have this constraint on the order of write operations, and the interference between read and write operations starts with a very low write load.

However, there may be situations where it is desirable that the write load be greater than 20 percent of the time line, but it is still desirable that the read delay be as small as possible to accommodate this situation. This can be accommodated by management of write operations on the stripe groups.

In describing the operation of these and other examples, the loading and response times of the memory modules and system are varied to illustrate the principles of operation. For convenience, the time spread of the read and write requests is assumed to be uniform over time and corresponds to the read or write load at average speed. Also, even over a short period of time, loading is considered a steady state value to simplify the description. Limitations such as bus bandwidth are also neglected, as the delay and response time of a memory module is generally quite longer than the delay associated with bus transit time. Moreover, because the various data areas in the memory system may experience different read and write loads due to the stored data type, application accessing the data, virtualization, etc. among other factors, loading may change in other stripes in the memory system And the above described situations may be viewed as representing a local loading value rather than a global loading value. As such, memory management applications can be for a local base rather than a global base. If necessary, motion adjustments may be accomplished by global or local timing algorithms, passing of tokens, polling, signaling, or other methods of coordinating transient operations in a computer or memory system.

5 is shown as consisting of stripes, and the zeroth stripe 410 is a memory module 310 (or chip, for example) (A0, B, C, D and P) B0, CO, DO and PO). The remaining stripes 2-9 of the system are similar to form a memory system of 50 modules.

For illustrative purposes, the timing circuit for each memory module may be considered to be initialized simultaneously to another memory circuit, for example, at a time interval of 1 msec, which is sufficient time to complete at least one write or erase operation . This write or erase operation is performed one column at a time in successive time intervals. Figure 6a is a simplified showing a column 514 of memory modules that can be enabled for write operations in successive time intervals _{(t 1, t 2, ...} , t 10), which repeats (modulo) 10 as a module . As shown in FIG. 6B, where the time history of stripe 0 is shown, a single memory module can be seen to be enabled for write operations at any time period. This satisfies the criteria that four of the five memory modules in the stripe become available for a read operation at any time. This is a delay that can only follow the read delay without any effect of the write load.

If the write load exceeds 20 percent, this strategy can not keep up with the amount of data or erase requirements required to be written. Additional write cycles may need to be allocated. One or more memory modules of the stripe may be in a write state upon a read request, to the extent that they are allocated as needed. Thus, four of the five memory modules can not immediately respond to a read request, and the read delay increases from a very small value to at least about 1 msec corresponding to a write or erase state period.

When discussing delays with a uniform request arrival rate, the actual average delay is half of the containment period due to the write state (for simplicity, the terms "write state" and "erase state" It should be understood that it represents the time period of occlusion and the two terms are not repeatedly used in combination to simplify the discussion). In general, the duration of the write state is used, which corresponds to the maximum delay.

As the write load increases, the number of memory modules in the stripe in the write state at any time may increase and the delay may rise to approximately 4 msec up to the sum of the delays associated with the write state of the stripe.

However, if all of the memory modules in the stripe 410 are caused to be in a write state at the same time, the maximum value of the write state under a large write load may be limited to 1 msec. For example, in this example, if the write load is greater than 20% but less than 28%, then each stripe may also be enabled for a write operation every ten time intervals. Thus, in addition to the column (p in Fig. 5), the stripe 410 (stripe 0) may be enabled for a period of the first time interval. In this strategy, because all stripes are written at the same time, the total write time blockage is limited to 1 msec. As the write load increases, additional time intervals may be allocated for stripe writes. In particular, the strategy is to allow for striped writes as far in time as possible. That is, the next increment may utilize both the first and fifth time intervals of the modulo 10 iterations.

The write load on the memory module in the stripe may be expected to be approximately the same for any moment since at least pages can be written to all memory modules in the stripe as a write to one memory module if written. Nonetheless, there is a difference in write load, which may be due to less than one page of write or housekeeping activity on a particular memory chip (due to bad blocks, etc.).

As shown in FIG. 7, the memory module 310 includes a persistent memory 320, which may be, for example, a flash memory, such as a buffer memory 330, which may be a DRAM, May include a controller / bus interface 340 or other bus interface, which may be a configurable switching element (CSE) as described in U.S. Serial No. 11 / 405,083. The memory module can buffer the ingress and egress data and instructions so that the memory module can maintain a queue of pending operations.

Operations that conflict with low latency read operations may be limited to specified time intervals for write operations. If a memory module timing slot allows write operations, many write or erase operations that may be performed during the slot time period may be performed by de-queuing from the controller 340 or other maintained queue. However, if there are no pending write or erase operations, the pending read operation may be performed by being decoded from the controller 340 or a queue in the module, for example.

Alternatively, write or erase operations may remain. When additional write operations remain in accordance with the programmed operating policy, this is interpreted as an indication that the write load exceeds 20% and an additional write cycle needs to be allocated. The main memory controller may be notified to prevent write operations to the stripe, or additional time slots may be allocated to write operations until the queue is reduced to the nominal level, so that the number of pending operations may be zero or less. On a global allocation basis, write operations may be directed to a memory module that does not currently have a high write load. When assigning time slots in the write process, the time slots are spaced during the -10 iterations of the pattern module for the example described. As the write load increases and more write slots are required, they stay closer together, but the slots are between as many writes as possible. In this way, the total length of any write block for a read request is minimized as the write load increases, and for less than 50% write load, the maximum block can be only one write cycle. The timeline available for reading is also reduced accordingly; However, high read loads and high write loads for the same stripe are naturally temporary and can have a small impact on overall system response time.

The policy of allocating additional write time blocks according to local queues allows adaptation of the behavior of each strip for read and write imposed by the dynamic behavior of the system.

In another aspect, when individual modules in a stripe communicate with each other using, for example, a token passing configuration, the token may indicate a permission to perform the write interval. The token may be passed between the memory modules A-P of the stripe (e.g., stripe 1) sequentially. If the token is held by A1, a write interval of 1 msec is allowed for one write interval in this example. If there is a write operation in the queue, these write operations that may be completed within the interval are executed. The token is then sent to B1, where processing is repeated; If a token is sent consecutively and the PI has a token passed to A1, then a round robin is performed.

 If the write operation is pending after completion of the write interval, this is an indication that the current write load has exceeded the 20% value of the write delay, which is transparent to the write. If there are no other means of limiting the write load, the pending writes may have to be executed in the near future to prevent buffer memory 330 from overflowing. In this situation, another write operation is performed after the token has passed, which may allow at least one time interval between write intervals. Thus, the number of write intervals used during any round robin may vary with the write load, but the number of consecutive write intervals may be unique until the write load becomes very high.

The assignment of the time periods in which the memory modules can perform the erase or program (write) operation can be performed in any manner, for example, by the transfer of control messages from the global controller to the modules, May be done with a time base assignment for the global reference time to operate in accordance with the local determination of the time period by a common bus or wire, among others. Access combinations may be used; For example, when a given programming data rate is greater than can be satisfied by having a single column of RAID group execution programming at a time and there are multiple RAID groups, one or several of the RAID groups may be assigned to some of the RAID groups At the same time, one or more or all of the modules may be programmed or erased at the same time as they are programmed or erased as shown in FIG. In such a system, for example, a column that can perform an erase or program may be determined by a fixed allocation of time periods, while a determination of when an entire row or a RAID group can perform an erase or program operation may be determined by the next RAID May be determined by one of the modules in the RAID group that sends a command to the next RAID group indicating that the group can start the form of token passing, and the module continues until all modules in the RAID group have been processed, It can be determined that the program or erase operation has been completed by the use of a "pull down" wire in which all modules are held, a common bus in which other modules are used to indicate what has been done, or similar methods or configurations.

If all the time periods do not overlap, the delay effect of the scrambling or program operation may be completely obscured; If the time periods do not substantially overlap, the delay of the scrambling or program operation can be observed up to the overlap time period. As long as the amount of time overlap is less than 100%, the connection time delay can be reduced compared to the erase and program operations still completely overlapping with the apparatus and method.

As shown in FIG. 5, when several RAID groups perform a program or erase operation to one or more modules or all the modules in the group, the non-overlap time may be determined from one module in the RAID group to the next It is the non-overlapping time of one RAID group for a RAID group.

It should be noted here that the delay enhancement is not an improvement in a single read access, but only if, for example, there is a read access to all RAID groups, the delay is increased only for those connections to the RAID group in which one or more modules are programmed or erased, The connections to these RAID groups that only program or erase will not experience such an increase. As a result, the average delay for all read connections can be improved.

Access to flash memories of other configurations which may be removable or fixed may be applied. The approach described herein may be done within the module itself if the module has a sufficient number of flash devices. Thus, the approach may be applied to various levels within a memory structure, such as disk access protocols, such as SATA, SCSI, Fiber Channel, or other types of factors, or currently used standard hard- It can be used regardless of solid state disks (SSD) in the drive's form factor. The correspondence between the RAID group and the modules can not be a one-to-one correspondence of the modules and "columns" of the RAID group. For example, a "column" of a RAID group may spread across more than one module, or due to RAID reconfiguration, data on the module may be in the process of moving to a replacement module, Column ".

In another aspect, a RAID-6 configuration may be overlaid on RAID-4/5, where another parity calculation is performed on the columns of the data array. Alternatively, additional parity computation may be performed on columns of the data array that are considered physical configurations. That is, regardless of whether a memory module is assigned to a stripe, the data in the column of the linear array of modules can be XORed to compute the parity data. This can also be done in the case of a binary tree as shown in FIG. 4A or FIG. 4B. For example, data from the two memory modules in the tree may be XOR'ed to create the first parity data. Similarly, this parity block can be XORed with the data in the receiving module to create a new parity block. Since this is a binary tree, two new parity blocks can be sent from each node to the next higher physical node in the tree where processing of the XOR can be performed again, to the root of the tree, or some other higher level node is reached. This parity data can likewise be used similarly to the column parity of a RAID-6 system, providing additional parity data if one or more of the modules fails. Propagation of XOR parity data may be performed with computations associated with the computation of XOR parity that is limited to the amount of data required for the data block itself at any level of the tree and distributed substantially uniformly across the memory modules without significant bus loading .

When the term memory module is used, the memory module may be, for example, a pluggable circuit card having a plurality of memory circuits, or the memory module may be a memory circuit on a circuit card or a respective one of what is known as a solid state disk (SSD) Be a group; SSDs come in many form factors with packages that can fit the size and type of current standardized machine disk drives that can be substituted from individual cards. The scale size of the logical address range that may be associated with the memory module or storage location is not intended to be limited to the description herein, and thus the memory module may include both larger or smaller storage devices or data structures.

By way of example, FIG. 8 illustrates a group of modules where each module belongs to more than one RAID group, and RAID groups are stripped in various ways across the modules. For example, a RAID group (A, B, C, D) is stripped horizontally, each strip containing an X address, strip A has X-1 at address 0, B has 2X- E, F, G, H, I are stripped diagonally, and each group also includes an X address. 9 shows that the number of in-group addresses is continuous or not to be the same as another group. In this example, addressing follows the last address in group I, starting with group A having 10X-1 addresses at X-1 and 9X at zero.

While Figures 8 and 9 illustrate a uniform and regular layout, RAID stripes need not be regular or uniform, and as an example, a ZFS file system can be used for all data pieces in any To be written to its own RAID stripe that can be placed in the module set.

In an aspect, the data of the RAID stripe may be divided into a plurality of data groups. The parity pattern is calculated by an exclusive OR (XOR) of a plurality of data groups. Data and parity groups are created as RAID stripes. The parity data may be distributed among the memory modules of the RAID stripe or may be written to the memory strip of the RAID stripe which is separate from the data. If a RAID stripe is read and the RAID stripe has an M memory module, data from the first M-1 memory module received by the memory controller can be used to determine the data stored in the read RAID stripe. If the memory strips of the RAID stripes are managed so that write or erase operations can only be performed on only one of the modules at a time, a read operation sufficient to restore the stored data can be performed without waiting for the completion of any write or erase operations.

In another aspect, the arrangement of the stripes in the memory system may be selected according to a policy that optimizes one or more aspects of the performance of the system, such as delay, read or write speed, fault tolerance, and the like. The following examples describe the allocation of logical address ranges for a physical memory module to create a plurality of different stripe characteristics. The assignment of a logical address to a physical address in a memory module may be performed by a policy that emphasizes other aspects of system performance, such as garbage collection, error correction, and the like. However, in establishing these policies, the configuration of the memory circuit may mimic the configuration of the upper memory module of the system to achieve a similar purpose. Again, the level of hierarchy in which logical to physical addressing transitions occur is not limited to this discussion.

The assignment of a stripe to a logical address range from the appearance of a stripe in a logical address array may be indicated by a matrix approach as shown in FIG. This arrangement may be convenient for explanation purposes, but is not intended to be confined. Various assignment algorithms can be used. The transformation used to describe the location is (row, column). In some instances, a row or column may have less than all data from the stripe in conjunction with parity for the stripe to recover the data without the delay associated with the write / erase cycle described above (and at least to some level of write bandwidth) May be related to use. It should be appreciated that the array of address ranges in the matrix format is only one of many possible arrangements and that the matrix representation is selected for use in the example as being most readily understood when describing multiple examples.

The term "erase-hide" can be used to generally describe the concepts described above, and it is understood that the effect of writing to or erasing the memory does not appear to affect the process of reading data from memory. It can be used to recover data. "Erase Hide" may be fully effective under a given system load or partially effective when the system load continues to increase.

For a particular application, such as a program running in a virtual system, the location of data in memory may be selected to highlight, for example, delay minimization, transfer bandwidth, data recovery rate, data loss probability, To understand the storage of data in such a system, the concepts of logical array space and physical memory space are used to simplify the description. The mapping of logical array space to physical memory may be limited in some cases by the requirements imposed by erasure hiding. Data can be spread in the logical address space using data stripes. The data stripe may have associated parity data. Single parity, dual parity, or some other error correction technique may be applied to the data of the stripe and stored in a stripe or elsewhere, such as when a matrix parity is used.

In the array of address spaces, Fig. 10 shows a stripe "0" in the third row of the array, for example. The stripes have a length of 5, and both address ranges may be associated with the data. Alternatively, one or more of the address ranges may be associated with the calculated parity for the remaining data. By way of limitation, the address range may be the smallest address range that can be written to the particular storage medium being used. This can be a page, a sector, or the like. More than one page may be associated with each storage area of stripe "0 ". In this example, the logical address range of stripe "0" with length L = 5 is specified as 0.1 to 0.5.

The stripes may be arranged to traverse some or all of the columns of the logic array. The address range of the stripe may occupy different rows of the logical array for each column, as shown in Fig. Here, a second stripe "1" of length 5 is shown, and the row number is reduced by one for every column increment. In Fig. 12, another stripe, e.g., stripe "2" may be similar to stripe "1 ", but the number of rows can be arranged to increase by one for every column increment.

The increment value of the number of rows can be greater than one, which increases the number of rows by two for every column increment, as shown in FIG. In this figure, the size of the array was expanded from 5x5 to 5x9 to simply represent the stripe. FIG. 14 illustrates having two row reductions. The stripes can also be arranged vertically, occupying heat as shown for stripe "5 " in Fig. The stripe "5" corresponding to the column may be unsuitable for use in memory applications where erase hiding is used, and erase hiding is configured such that erasing is performed on physical memory modules corresponding to columns during a common time period. In this situation, data may become insufficient to reconstruct the stripe when the physical memory response is corrupted by an erase cycle that conflicts with a user data request. However, if the erase period is configured on a row basis, stripe "0" may be encountered with erasure hiding containment while stripe "5" may prevent erasure hiding. To simplify the representation, it is generally considered that the column is erased during the common erase cycle. However, it will be apparent to those skilled in the art that the rows may also be handled similarly and the locations of the physical memory modules associated with these operations may be controlled by an allocation table that conforms to the physical attributes of the memory array, and may not appear in a matrix configuration. This may be evident, for example, in FIG. Individual modules may be organized into erase time groups and each erase time group may correspond to a logical row.

Alternatively, the physical modules may be configured to have separate addressable "even" and "odd" memory locations, and even and odd memory locations may be assigned to different erase hide periods, . This configuration may be useful if the internal bandwidth of the memory module is limited by the data transfer rate.

If the range of the stripe in the row or column exceeds the boundaries of the logical array, then the stripe may wrap around on a modular arithmetic basis as shown in Figure 16, which corresponds to the stripe in Figure 14 when used in a 5x5 matrix do. The array of FIG. 16 is sized to allow the stripes to wrap around in both columns 1 and 5, but in large arrays the wraparound may occur for the stripes of stripes extending beyond the boundaries of the array in a particular direction. Fig. 17 shows a similar situation with respect to the stripe direction in Fig.

In general, the directions of the stripe in this example can be visualized as the lines having a slope are generalized to lines with 0, 占 1, and 占 line / column tilt. Larger step sizes may also be used.

The range of logical addresses including a specific stripe may be different for each stripe. As shown in FIG. 18, a part of a plurality of stripes may be stored in the same matrix. Here, the stripe directions shown previously in Figs. 10, 11, 12, 16, and 17 are overlapped so that the logical address range 3 of each stripe is found in (3, 3) of the logical array. The vertical stripe in Fig. 15 can also be used as shown in Fig. All the stripes are found in the central array position 3, 3, and each stripe is also found in a separate array position.

This stripe pattern can be called a stripe cluster and has a data dispersion effect that can be used in various ways to control the performance of the memory system. In large arrays and large stripe lengths (L), other stripe tilt and patterns may be used as part of the stripe cluster, such as +/- 3, < RTI ID = 0.0 >

In Fig. 18, each stripe may appear to have the same amount of data. That is, as shown, there is no indication characterizing the storage capability of each address range group. Each stripe has a width W _s . The total amount of memory in the stripes allocated to the physical memory module is determined by considering the percentage of total physical memory in the memory module available to the user considering the housekeeping requirements, such as total physical memory and garbage collection of the module, maximum predetermined timeline loading, Lt; / RTI > In this example, the housekeeping function is ignored and the physical memory can be completely allocated to the stripe. The sum of W _s for the stripes assigned to the module may be equal to the total physical memory.

In Fig. 18, if position (3, 3) corresponds to a physical memory module, all stripes of the stripe cluster may be accommodated in the module if the sum of the widths W of the stripes is less than or equal to the available physical memory . Figure 20 is a view of an array in which the stripes may have different widths. In this example, stripe " 20 "with a stripe of -3 slope is replicated to stripes 21 to 23, while stripe 10 with a slope of -1 is not replicated. Thus, if each stripe address range X.3 represents the amount of memory M, stripe-3 can be seen to include 3M memory space while stripe direction-1 includes the memory space of M Can be seen as doing. Other arrangements are also possible, and the memory space of the stripe may be allocated to a particular application program or a plurality of allocation programs.

For example, rather than limiting, if each of the stripes contains one parity computed from four data elements and a data element of the stripe, even if there is a resource conflict in (3,3) without any performance penalty, Any one of the stripes may be connected. This is due to the use of parity to replace any address range of the stripe that can be a delay in reading due to hardware conflicts or restrictions. An array or similar arrangement as shown in Fig. 18 may be used, for example, in the allocation of data to physical memory in each memory module of a larger memory system. Figures 21 and 22 illustrate module wrapping in different sized arrays.

The resulting stripe patterns can use policies or methods that can be understood with reference to the following macros running on Microsoft Excel, for example, and those operations can be understood by those skilled in the art:

// code for FIG. 23

For i = 0 To 4

Call make_stripe (5, 5, 5, 0, i, 5 * i + 0, 0, 2)

Call make_stripe (5, 5, 5, 0, i, 5 * i + 1, 1, 2)

Call make_stripe (5, 5, 5, 0, i, 5 * i + 2, 2, 2)

Call make_stripe (5, 5, 5, 0, i, 5 * i + 3, 3, 2)

Call make_stripe (5, 5, 5, 0, i, 5 * i + 4, 4, 2)

Next i

// code for FIG. 34

For i = 0 To 9

Call make_stripe (7, 7, 5, (i * 5), 0, i, 6, 0)

Next i

For i = 10 To 19

Call make_stripe (7, 7, 5, (i * 10), 0, i, 7, 0)

Next i

For i = 20 To 29

Call make_stripe (7, 7, 5, (i * 15), 0, i, 8, 0)

Next i

For i = 30 To 39

Call make_stripe (7, 7, 5, (i * 20), 0, i, 9, 0)

Next i

For i = 40 To 49

Call make_stripe (7, 7, 5, (i * 25), 0, i, 10, 0)

Next i

// helper functions

Sub make_stripe (width As Integer, height As Integer, ssize As Integer, x As Integer, y As Integer, addr As Integer, stype As Integer, pivot As Integer)

Dim i As Integer

Dim j As Integer

Dim 1 As Integer

For 1 = 0 To (ssize - 1)

j = stripe_x (ssize, stype, pivot, 1)

i = stripe_y (addr, stype, pivot, 1, j + x, width)

j = ((j + x + width) Mod width) + 1) * 2

i = (((i + y + height) Mod height) + 1) * 2

Cells (i, j) .Value = Cells (i, j) .Value & "" & addr & "." & (1 + 1)

Cells (i, j) .Select

Call make_border

Next l

End Sub

Function stripe_x (ssize As Integer, stype As Integer, pivot As Integer, pos As Integer)

Select Case stype

Case -1

stripe_x = 0

Case 7

stripe_x = pos * 2

Case 8

stripe_x = pos * 3

Case 9

stripe_x = pos * 4

Case 10

stripe_x = pos * 5

Case Else

stripe_x = pos

End Select

End Function

Function stripe_y (n As Integer, stype As Integer, pivot As Integer, pos As Integer, x As Integer, w As Integer)

Dim q As Integer

Dim p As Integer

Select Case stype

Case -1

stripe_y = pos

Case O

'horizontal line

stripe_y = 0

Case 1

'forward slash

stripe_y = pivot - pos

Case 2

'backward slash

stripe_y = pos - pivot

Case 3

stripe_y = 2 * (pivot - pos)

Case 4

stripe_y = 2 * (pos - pivot)

Case 5

q = (pos + (n \ pivot)) Mod 8

'q = pos

  p = n + pos

   Select Case q

Case O

      stripe_y = p * 101

Case 1

stripe_y = p * 79

Case 2

stripe_y = p * 41

Case 3

stripe_y = p * 223

Case 4

stripe_y = p * 467

Case 5

stripe_y = p * 373

Case 6

stripe_y = p * 157

Case 7

stripe_y = p * 191

End Select

Case 6

stripe_y = 0 + (x \ w)

Case 7

stripe_y = 0 + (x \ w)

Case 8

stripe_y = 0 + (x \ w)

Case 9

stripe_y = 0 + (x \ w)

Case 10

stripe_y = 0 + (x \ w)

Case Else

stripe y = 0

End Select

A similar algorithm is used to generate the other figures used to illustrate the examples. Moreover, this algorithm or the like may be used to calculate the allocation of locations and address ranges in an actual system, which algorithm is part of a computer software product. Therefore, the selection can be made between the association calculations, the pre-computed look-up tables, or a combination of the above techniques as needed.

So far, the examples have shown a stripe cluster concentrated in a single memory module. From the above, however, arithmetic stripes clusters may be concentrated on each memory module in the array columns, for example, as shown in Figure 23, with the appropriate modules for which wrapping is desired. Here, stripes of length 5 and tilts 0, +/- 1, and +/- 2 may be used as generation functions. The generation function may be used, for example, to generate stripes 0-4 at (3,1) and then stripe 5 through 9 at (3,2), and so on down to (3,5) . Here, it is assumed that five stripes in each module occupy the total memory space of the associated physical memory module.

Regardless of where the center crossing of the stripe is located, it can be observed that the remaining data of the stripe is distributed so that only one of the crossed stripes at (1,3) is passed through any of the other modules, as in FIG. . This arrangement may be useful in facilitating recovery due to module failure. (1, 3) fails, the remaining data in the stripe with the data to be recovered may need to be used to recover the data in the faulty module. By doing this, the load of the system involved in reading the remaining data is spread widely across modules with distributed data, so that each module, which can be the environment of the array of Figure 5, is less affected, and the stripes are all zero slopes. In the arrangement of FIG. 5, all of the data needed to recover the data of the faulty module is located in four modules, while in the situation represented by FIGS. 23 and 24, the data may spread over 20 modules. Another similar example is shown in Fig. 25 and Fig.

The properties of the memory array, which may be considerably larger than that shown in the example, can be understood by considering a stripe cluster as the generation function. Each of the stripes that may be different for each stripe may have a width W, but it becomes easier to visualize the situation if each strip has a width W such as the minimum allowable write range, for example, a page. Indeed, if memory circuits have a capacity measured in MB or GB for a single device package, the width W for each stripe may be significantly larger than the page. In one aspect, the width W may be measured in a block that may be 128 KB or 256 KB, or in a die having a plurality of blocks in which a plurality of dies are included in a memory circuit.

One or more stripe clusters of different lengths L and different stripe gradients may be defined. For example, a stripe of length 7 may also be used, such as the stripe of length 5 described above. A stripe of length 7 may have a different number of data and parity units. For example, there may be five pages of data and two pages of parity. Which may represent different lengths L with different numbers of data and parity pages depending on application requirements. If the memory modules of the array are not filled with the first stripe cluster pattern, the second stripe cluster pattern may also be used as a generation function to interleave the data from the two patterns.

Since the first program in the visualization system and the second program in the visualization system have other optimization requirements such as delay, input / output operation, transmission bandwidth, recovery rate, unrecoverable data loss probability, etc., the stripping pattern (including parity) It can be chosen to best meet.

If each stripe is written as a plurality of pages, the parity can be calculated for the created stripe, and the memory is created at the same time as the data. In this way, reading data from memory is not necessary for the calculation of parity. The data is read at the previous time and is recorded with the currently changed data, or the data is new data that has not been previously stored.

Figure 27 shows an example of a memory system in which the physical memory module has a capacity equal to 25 stripe widths of width 1; The striping pattern for this example occurs similar to the pattern of FIG. 25 except that the occurrence pattern is centered on the matrix of each logical address range. The generated pattern may be widely dispersed and may have the property of spreading the load of the write and read of a plurality of applications to reduce the occurrence of "hot spots ". Hot spots occur when a user application program or visualization space references a logical address range that is repeatedly mapped to a memory module. This can cause performance problems, such as increased latency and faster memory wear.

Then, consider the situation where the address range (1, 3) corresponds to the memory module in which the failure occurred. It is then desirable to reconstruct the data using four of the five elements in each of the strips. To do this, the four pages of the strip can be used to reconstruct the parity if the parity is lost data due to the failure module; Or if the data page is recovered data that was lost due to a faulty module and is stored in an operable memory location (which may contain recovered parity data), then three of the four data pages and a parity page Can be used.

If the data is recovered, the recovered data is stored in an operational memory module having available storage space. The location selection of this data storage is discussed elsewhere. In an aspect, in order to preserve the erase hiding in the system, the recovered data may be stored in a memory module associated with an erase hiding interval such as a fault memory module. The spare memory module can be synchronized with the erase hiding interval of the fault memory module and the recovered data is stored either directly to the spare memory module or after the intermediate storage operation. Individual recovered data blocks may be written to any stripe that does not cross the fault module. As each recovered page is written to the stripe, the parity of the stripe can be updated by XOR calculation, and the recovered data is protected against subsequent failures as they are recovered. Alternatively, the recovered data is assembled into a stripe having an associated parity and thus recorded.

In one aspect, the spare module can be used to receive recovered data. The memory structure of Figures 4A and 4B may be compatible with hot sparing of recovered data for the memory module. The spare memory module may be synchronized with the erase cycle of the failure module and the recovered data recorded in the spare module. Since the memory capacity of the spare module can be the same as the fault module, the data can be completely restored to the spare module.

However, since it may be desirable to limit the write time of the data to the erase interval period of the column so that the response time of the memory system to the read request of the data in the recovering stripe is not compromised, writing of data to the spare module Speed can be limited by the speed at which data can be stored. In one aspect, writing of the recovered data to the spare module may be limited to less than the maximum bandwidth. Since the spare module is filled with recovered data, the timeline loading state is getting closer to the state of the module with this data before it fails. That is, due to the user program accessing the module and housekeeping activities such as garbage collection and wear leveling, the read and write load on the module is increased. If the write speed of the recovered data in the spare module is not adequate, the response time of the spare module to the user request may be impaired.

An intermediate recovery step can be introduced. For example, recovered data may be written to an operable memory module having spare space. Such a spare space may be preserved especially for recovered data, or may be the result of a garbage collection strategy. For example, there may be some spare space in each module that may be used as a temporary basis for the persistent garbage collection strategy described in U.S. Provisional Application 61 / 186,626, filed June 12, 2009, which is incorporated herein by reference.

During normal operation, performing garbage collection reduces the average write bandwidth of the module as the amount of total memory space in use increases, consuming some of the available read and write bandwidth as overhead. If there is sufficient free memory space in the module in use and / or one or more spare modules, more bandwidth is lost by altering, reducing, or stopping the processing of garbage collection during data rebuilding. In addition to reading the rebuild data for the module, And may be allowed to be available for both write operations for storing.

If the recovered data being temporarily written to the memory module during reconstruction is identified by a local decision based on, for example, a special command option, the use of a tag for the data, a special address range or address or some other metadata, The location of the temporarily stored data may be selected to reduce or eliminate the need for garbage collection of the blocks used for storage.

For example, temporary reconstruction of the available space of a plurality of memory modules may be performed. As long as memory space is available, routine garbage collection processing can be slowed down or stopped. Blocks containing reconstructed data may typically be only a few predetermined ratios of data that are not temporarily stored in the memory module. Little or no garbage collection may be performed on data blocks that contain temporary data, primarily or entirely.

If the transient data representing the reconstructed (recovered) data is passed to the replacement memory module, the blocks used for storage of such data, primarily or entirely, are only likely to be erased and can be efficiently garbage collected. The time to replicate the reconstructed data to the replacement module as well as the space that may be needed from a particular module to temporarily store the reconstruction data, the average or maximum write bandwidth of the user data, the available spare memory space, and the time to perform the reconstruction , The garbage collection process may be slowed, changed, or interrupted to accommodate the failure event. Thus, a failure event can be regarded as an exceptional case for the routine operation of a memory system, and the recovery effect from a failure can be spread both physically and temporally throughout the system to mitigate the impact on most users do.

In another aspect, the degree to which garbage collection processing may be slowed, altered, or aborted may affect the time to perform the reconstruction, and the computation may need to be performed more than once to converge the answer. Temporary reconstruction data allocated to the module, based on the amount of free memory space for a given module if the free memory space is located in the module, as to whether the memory is free and available for creation, or whether it should be garbage collected before it can be used, Amount or characteristic of the material can be changed.

For example, more temporary data may be allocated than another module that has no free space to allow free memory in a module with free space or that has free space that requires a significant garbage collection effort. A considerable amount of temporary reconfiguration data may be allocated, rather than from an address that has significant free memory space but is later recovered at the time of the reconfiguration process and needs to be reallocated to a module that requires little or no proper garbage collection to be available.

The garbage collection policies and / or parameters used during the reorganization may not be the same for each module in the system and may be policies and / or parameters that are deemed undesirable under normal operating conditions. However, the particular policy selected is for use during the repair cycle if the repair operation no longer includes a particular module and may return to routine operation.

If there is such a spare memory space, the recovered data can be written to the modules in the same column as the fault module. This data is immediately in an erase-hide manner. However, it may be desirable to distribute the recovered data more widely. Effectively, all the remaining modules can be used, except for the modules containing the recovered stripes. The recovered data may be in a column having rows containing the striped data, and the striped pages may be in the erase interval. An increase in latency can occur because two data reads may be required rather than one data read. This can be prevented when the written data to a column that is not the same as the column of parity of the fault module, the same data or data, is also written to the spare area of another column. This can be viewed as mirroring the recovered data. While this uses more space temporarily, the data spreads more widely across the memory by this distribution and by reducing any performance penalty. When the authored data in such a temporary column is read, all of the storage locations are read, the first one of the two identical data pages is used, or, considering timing, the data from one of the two memory modules Is read.

At the latest, after all data has been restored to persistent memory, the recovered data can be moved to the current spare module so that mirror data is no longer needed. The spare module is a replacement for the fault module and its location is thus mapped to the logical address space.

Since the data used for recovery can be distributed over 20 of the 25 memory modules in the illustrated example, the reading of this data can basically proceed in parallel. In order to reconstruct the normal operation of the memory system, the read effect of the data is spread throughout the entire memory system. Likewise, the effect of normal operation of the read memory system of the requested data can be spread more evenly.

This can be compared to the arrangement in Figure 5 where data is written to stripe "0" to store data in row "0 " Here, all data and parity used to recover data from the fault memory module are stored only in the remaining four memory modules of the stripe. Thus, for example, data is read from the modules (B, 0), (C, 0), (D, 0) and (P, 0) to achieve data reading for reconstruction of the fault module (A, . To store data in the same time period as the arrangement of Figure 20, the data must be read from the memory modules in Figure 5 at about four times the data rate. Likewise, if writing the recovered data to the operable memory module is performed according to the same stripping strategy, the writing speed of the recovered data to the module is again about four times as high as in the example of FIG.

The description of the arrangement of FIGS. 10-27 and the restoration of data after a module failure does not specifically mention the erasure hiding, which may place restrictions on the location of data in physical memory, and the subject of reconstructed data in the case of a memory module failure .

For example, consider the 5 x 5 address range of Fig. 25 having a failure in the module including the address range of (1,3) as shown in Fig. The address range of the arrangement of FIG. 25 may be associated with a memory module of a physical memory system, for example, similar to that described above in FIGS. 4A and 4B. If the erase hiding is for design purposes at a particular level of system architecture, due to the timing of each erase (and write) interval for each physical memory module, which may be a module, sub-module, etc., only one of the modules associated with the stripe Writing or erasing may be performed during the interval. To the extent that the intervals are only partially overlapping, the erase-hide sun may be less effective.

When the memory module is composed of a plurality of memory circuits, each memory circuit may be written to or erased from another memory circuit in the memory module. For a flash memory, this attribute may be at a die level with a plurality of die in each memory circuit. Presently, such memory circuits may be associated with a package device having a pin or ball grid array or other interface such that the memory circuit can be assembled to the memory module. However, it should be understood that the memory circuits and packaging technology are being developed in succession and that the terms described herein are conceptual rather than limiting.

When the memory module is composed of a plurality of memory circuits, not all memory circuits have a pending erase when the erase interval occurs for the memory module. Those memory circuits that do not have pending erasures can perform pending write operations or write operations that arrive during the erase interval. Pending read operations can be performed to such an extent that neither erasing nor writing is performed on the memory circuit of the memory module. Thus, even during the erase interval for the module, read operations can be performed on some of the memory circuits of the memory module. A read and write request to be executed based on available timelines during the erase interval may be decoded for execution based on a policy that can prioritize requests from particular users, services, and the like.

However, if a read operation is received for a memory circuit in which an erase operation is in progress, the erase-hide mechanism described herein prevents delays associated with the completion of the erase interval. This can be significant in situations such as multi-level flash (MLC), which seems to be a trend for longer write and read times.

17, in which non-overlapping attributes can be obtained by sequentially permitting the address range columns 1-5 of FIG. 17 to be allocated to the memory modules so that all of the rows in column 1 are in the erase interval at the same time, . After the completion of the erase interval for column 1, the erase interval for column 2 may occur, and so on.

As before, since the individual addresses of the stripes, such as stripe "0 ", are distributed across all columns regardless of which row is considered and all rows in the column are assigned to memory modules associated with the same erase interval, Four of the five address windows are always available for immediate reading. Thus, the arrangement of FIG. 17 can be compatible with the erase-hide scheme while distributing the data over physical memory extensively. Only one address range of the stripe is associated with each erase time.

The allocation of data loss to users can be managed through policies when allocating stripes to a user in consideration of mapping of stripes to memory modules. This can be visualized in the logical address space, and each row / column designation is associated with a plurality of stripes. For simplicity, FIG. 30 illustrates this concept with row / column logical address ranges having sufficient space for two stripe widths. Stripes 0, 1 and 2 are assigned to user A, stripes 10, 11 and 12 are assigned to user B, stripes 20, 21 and 22 are assigned to user C, Suppose that the stripes 30, 31, 32 are assigned to user D, the stripes 40, 41, 42 are assigned to user E, and the stripes 50, 51, Again, for simplicity, the depicted stripes are for stripe tilt 0.

The first row contains data for users A and D, the second row contains data for users A and E, the third row contains data for users A and E, the ninth row contains data for users A and E, C and D, and so on.

The multiple failure effects of the modules on the data loss pattern can be understood by considering the influence of the two failure modules in the memory system, for example on the integrity of the stored data in the memory system. That is, the second module may fail before completing the recovery of data associated with the first failure module. If a single parity is used, data is lost if a second failure occurs in the same row as the first failure. For example, if (1, 2) fails and (3, 2) fails, the data in row 2 is lost. This affects users A and E. If a second failure occurs in any other row, each of the users will have only a single fault and the data can be recovered. Therefore, if the data is scattered by the stripe, the second failure is only a small chance of causing irrecoverable data loss. This suggests that, for example, thermal parity, where parity is computed for a row as protection against a double fault, can be used. Although recovery of data using thermal parity is slower than the use of a single parity, this is a useful strategy due to the low probability of failure combinations in a particular module.

If each stripe is protected by double parity, the same general considerations can be applied if the third module fails before recovery of the data from the failure module.

Many exemplary patterns of striping are depicted to illustrate the striping of data in a logical array where the length of the stripes and the number of columns do not fit. Some of the resulting arrays may not appear optimal, especially for a small number of stripes. However, the car becomes less important for very many stripes and allows for selection of array width, stripe length, striped stepping, and the like to achieve other system objectives.

Fig. 31 shows a logical array of 7 x 7 dimensions with a stripe length of 5. As in other examples, the number of data addresses and the number of parity data addresses in a stripe may be selected based on system performance requirements. For example, five stripe lengths may have four address ranges, one parity address range, three data address ranges, and two parity address ranges. The first stripe (0, 0) occupies the array position (1-5), and the second stripe occupies the arbitrary positions (6, 1) to (3, 2). That is, the stripes wrap around the right array boundary in increments of one row. In a disk array, this is sometimes referred to as left diagonal striping. In a typical disk system, a row of disks is configured and a wraparound follows on disk groups corresponding to row zero in this example. In this example, the address ranges of the stripes may be assigned to logical array locations that in turn may be mapped to a memory module and, in turn, may be mapped to a memory module. The term "left diagonal" means that the line through a group of address ranges is understood by considering the first element (e.g., 0.1, 1.1, 2.1, 3.1, ...) in each stripe from upper right to lower left, .

The array positions 6,6 to 7,7 are shown by dotted lines. They represent address ranges that can be filled by some of the eight stripes and the nine stripes, and the remainder of the ninth stripes are wraparound to the first row. Alternatively, the array may not be filled with the system with a different number of memory modules and with the rows that may occur after the array locations 7, 5, depending on the lapping.

32, a first stripe of length 5 (stripe "10") can be started at (3,1), and the next logical address range is (5,1) And is incremented by 2 and so on until (4,2). The next stripe (stripe "11") begins at (6,2) until the address range 14.4 is located at (7,7), and the stripe continues at the start of the array Lt; / RTI > The highest numbered stripe shown is stripe "17 ". However, it is clear that the array is not yet filled and additional stripes "18" and "19" fill the array for the first time and start wraparound.

Figure 33 shows an arrangement similar to the arrangement of Figure 32 except that the column increments between the address ranges in the stripe are incremented by three.

FIG. 34 illustrates the stripping pattern of FIG. 31 in which the stripping pattern and the high order address range step patterns of FIGS. 31-33 are chained together to assign a total of 47 stripes to a logical address range. The effect of stripe and non-commensurate length of the array has little effect on uniformity filling the address space. In large memory systems where there may be hundreds to tens of thousands of strips, the non-optimality of the distribution is generally not taken into consideration.

Figure 35 shows the distribution of the stripes crossing at (1,4) for the array pattern of Figure 34; Five stripes cross in the module and the data associated with the stripes is scattered throughout the array such that the other data of the stripes is found in 17 array locations (which may correspond to 17 memory modules). Thus, if there is a failure in the memory module associated with (1,4), the data is recovered from the 17 modules. Depending on the thermal increment in the stripe, the length of the stripe, and the total number of stripes, the data is written over the non-faulting modules so that the read and write loads for each of the non-faulting modules are evenly distributed across the system for reconfiguration of the faulty module It is widely distributed.

36 is an allocation pattern using the arrangement of FIG. 31 as the occurrence pattern repeated 48 times. Referring to the results of FIG. 36, FIG. 37 shows the relationship of the stripes passing through (1,1) indicating the failure module. The stripes are distributed over eight modules and some of the modules have four stripes passing through them. This shows that the data of the memory module may be more or less distributed over the memory system in accordance with the striping pattern that is less optimal than the situation of FIG.

Figs. 38 and 39 illustrate a situation similar to that of Figs. 36 and 37, but the sequential address range of the stripe in the stripping pattern is increased by 5 in the column direction. This results in a different set of memory modules that store data from which the data of the faulty module can be recovered.

If many other stripping patterns are combined to fill the array, the data spreads across many memory modules as can be seen in FIG. Here, the data is not uniform but spread over 26 modules.

The fault impact of a memory module upon recovery of data for other parity accesses can be better understood with reference to FIG. The stripes are 6 in length and the matrix is a 6 x 10 logic array. Here, the stripes " 0 "to " 9" are created with a slope "0 ", the stripes 10 to 19 are created with a left diagonal pattern, and the stripes 20 to 29 are created with a right diagonal pattern . There are 29 stripe patterns. Of course additional stripe patterns can be created, but the example is simplified to follow the reader in the figure. Patterns are generated by the algorithm, and the association of the matrix of stripe address ranges with the matrix may actually be determined by an arithmetic calculation or a look-up table.

(1, 1) has failed. That is, it is necessary that the address ranges (0.1, 18.1 and 22.1) are lost and recovered. A stripe "1" is also found in (1, 2), (3, 1), (4, 1), (5, 1) and (6, 1). The stripe "18" is also found in (2, 10), (3, 9), (4, 8), (5, 7) and (6, 6). The stripe "22" is also found in (2, 2), (3, 3), (4, 4), (5, 5) and (6, 6). In this example, each stripe is of length L = 6, with five data address ranges and one parity address range. Therefore, the data of the array location (1, 1) is recovered as described above for the spare module which can eventually be assigned to the array location (1,1), and the recovery process is completed.

However, there is always a concern that the second module in the memory system may fail before the stripes are fully recovered. The characteristics of data loss in terms of both the number of affected stripes, the probability of data loss, and the pattern of data loss are of interest.

Consider the use of stripes with five data logical address ranges and one parity address range. For example, assume that the parity is in the address range (X, 6), i.e., the sixth column. The data to be recovered is found in 14 of the 60 modules of the memory system.

For simplicity, consider a scenario where the second module fails immediately after the first failure. This situation can be considered unlikely to be a statistical basis, not a real one, because it can inevitably remove an inaccurate module that the technician thinks is a failure module, or it can cause failure by some other action. If the second fault is in the same row as the first fault, the array is configured such that the stripe with the address range at (1,1) does not have an address range in any other modules in column (1, Y) There is no loss of data at all, where Y is the row number. Either one of the nine modules in column 1 can fail without data loss. That is, nine of the remaining 50 modules may fail without any effect. These can be restored as described above. Of the other modules, 14 are used to recover the stripes of the first fault module. The data necessary to reconstruct the stripes of the first faulty module in one fault in any of the other 36 modules is not lost. In summary, any one of the 45 out of the 60 modules can fail without causing a loss of data that can not be retrieved using a single parity.

The effect of the second failure in one of the fourteen modules used in recovery resulting in the loss of two address ranges may lead to a loss of irrecoverable data for one stripe in a single parity case. All other stripes can be recovered. The failure of a particular module may be more damage to data integrity, as can be seen by considering the case of logical array locations 6,6 with data from stripes "18" and "22 " . Therefore, the data for the two stripes can be lost if the failed second module is a module 6,6. This can occur in about one out of 49 double faults. Knowing this probability can give priority to recovery of data from a module that needs to recover data for one or more fault stripes.

From another viewpoint, a failure of any one of the remaining thirteen modules of the recovery group may result in data loss in a single stripe. Depending on the width of the stripe (i. E. The amount of data in the logical address range), data loss can generally be limited to one stripe of data storage, and if stripes are associated with applications or virtual users, It can be limited to only one of the users.

Depending on the predetermined performance, one stripe or a plurality of stripes can be assigned to one user, so that the data loss pattern for the user can be managed. For example, if each logical address range is small (in the logical matrix), a plurality of stripes may be assigned to the user, which may be a chain string, and spread widely if data loss occurs. Alternatively, if the stripe width can be widened and data loss occurs, the data may be a contiguous block of data for the user. The choice may depend on the nature of the data and the storage structure backup type used.

If the parity is assumed to be at (X, 6), the parity may be in any one of the logical address ranges in the stripe. That is, the lost "data" may be parity data or parity computed data.

Stripes of length L = 6 may also be configured with dual parity, so that two modules containing data of the stripe may fail before the data can not be recovered using parity. Data loss may require three special modules to fail before the data is restored. It is possible to identify the modules in which one or more data stripes to be restored are located and restore these stripes first so that the possibility of data loss due to the third failure is reduced.

In general, the examples described above use the term physical memory circuit, which may be a single address location or may be distributed over a physical or logical location range, or a module to denote a logical or physical address range. The memory circuits for the physical memory module can be grouped to be part of different RAID stripes and have different time periods while read, write and erase can occur. As such, the use of the term module is a matter of convenience and is not intended to suggest or require a particular arrangement. Likewise, it is understood that suboptimal throughput configurations may be selected for other reasons, and may be mixed with the configurations described herein if desired. Memory modules may be purely memory-based storage, hybrid flash / disk storage, mixed memory configurations such as DRAM / flash, SLC flash / MLC flash, MEMS, phase change memory,

For simplicity of presentation, memory modules are contemplated to have controllers, temporary data storage, and non-volatile storage devices. However, not all of these aspects can be realized and implemented for a particular physical purpose. Alternatively, the capabilities of one or more memory modules may be found for a particular physical purpose. The choice of implementation is application-specific, and the more dense and more functional circuits can evolve over time as they are designed and produced.

The term memory module failure is used to denote a function of a memory module or an environment in which any memory circuit is degraded at the point at which a recovery operation is performed to reconstruct data given a particular system reference. However, if fault characteristics are allowed, such reconstruction of the data can be performed without replacement of the memory module. For example, consider a memory module having a plurality of installed semiconductor memory packages. One or more of the plurality of installed semiconductor memory packages may be faulted irrespective of the remaining operation of the module. Depending on the amount of spare memory space left, the data in the faulty package can be restored and stored elsewhere in the module. Thus, the entire process can be performed with one or more system architecture levels according to the required reliability, recovery rate, or other system performance criteria.

In another aspect, the memory usage efficiency of the module may be enhanced by a policy operating in conjunction with or independent of the module level erase-hide configuration. These strategies may not preclude the use of intra-module erase-hide configurations involving multiple circuit packages. The package itself may include a plurality of dies. Presently, in a certain level of system memory area, it is assumed that a die is limited such that a read operation can not be performed when an erase or write (program) operation is performed. At the level of the structure, at least other policies can be used to improve the overall performance of the memory system. By describing the policy at the level of such a structure, it should not be assumed that the policies can not be imposed at a higher level of the memory system structure if the hardware or software design can be driven by using the policies.

If erase or write operations of a plurality of chips are performed without synchronizing operations at a particular time or without other means of sequential in-stripe operations to rule out erase-blocking of the read operation, the time between erase operations on the chip Can be scheduled at an average rate sufficient to perform an erase operation without a queue of significant requests appearing. However, the time between erase operations may be selected as a bounded random variable. This policy tends to prevent periodic read blockage in RAID groups.

Another policy can be used to change the garbage collection rate. The number of write operations to the chip may be monitored and a predetermined number of write operations may be performed between erase operations, such that the performance rate or initialization of garbage collection may be subordinate. For example, after a lot of write operations are performed that are proportional to or equal to the erase block size on the chip, the erase operation can be decoded. Again, in order to prevent the occurrence of synchronous patterns, the actual number of write operations used as a threshold for this process may be selected as a random random number. Likewise, the garbage collection process can be initiated based on a similar threshold for the number of writes to the chip. This tends to keep the average amount of spare blocks within design limits.

In another aspect, some users may read large blocks of continuous data. Non-limiting examples may be image processing systems, video servers, and the like. In this situation, the total amount of data that can be read from the chip or package may be limited to the local bus bandwidth. The memory modules of the package having the local RAM buffer memory can buffer the data temporarily so that they can not be transferred at this rate but the reading can be performed at full speed. If the data remaining in the buffer memory exceeds the amount of data that can be transferred from the buffer memory at the maximum bus bandwidth in the same time interval as the erase operation or the write operation, the erase operation of the write operation may perform an erase or write operation Lt; / RTI > from the queue of pending requests for < RTI ID = 0.0 > In this way, the total number of write or erase operations can be increased by including the performance of a write or erase operation at the time when the read bus bandwidth is fully occupied.

Because the write request and data can be passed to the module while the read data is being retrieved from the module, it is possible to reduce the write load that can be accommodated before the write load has exceeded the threshold at which the overall performance of the erase- . These measurements are automatically performed by default from the upper level control structure.

Other measurements may be used when MLC flash memory or other memory technology is used where the upper level bits can be read or written at a different rate than the lower level bits. For example, each request may be stored by chip and address (high, low) and a queue may be formed for each chip. The total response time for the package and each chip can be calculated based on the expected read time, and the total response time for the package can be calculated for each chip. If the response time to the chip, including erase or write operations, is not longer than a particular read delay, write or erase operations may be performed, if appropriate, by decryption.

Some of the low-level techniques described above may be characterized by maintaining a track of outstanding write and erase cues and may be characterized in that the read operation is sufficient to buffer the data so that a particular read delay can be achieved even when performing at least one write or erase operation. A pending write or erase operation may be performed.

In some database systems, a "re-do" is maintained, and the log is basically a sequential enumeration of data elements sent to each and every command and memory. Periodically, this log is check-pointed to the backup storage device to be provided for long term data security as known to those skilled in the art. If a failure occurs in the database, it can be processed to reconstruct the database from the last valid image of the database, which can be retrieved from the backup storage again. Damage to the module due to a storage module failure can not be tolerated because the integrity of the database depends on having an effective rewrite log.

Often, the duplication of logs is maintained for additional security. By appropriately allocating the redo log and the stripe address space in which the replica is stored, the number of device failures that may occur before data loss can be increased, and recovery and backup of the log data can be facilitated again after a failure. By doing so, one of the patterns continues to maintain the erase-hide attribute.

As described above, a plurality of stripes may be configured based on a stripe cluster concentrated in a module in a logical space. One or more stripes with stripe patterns may be superimposed on the module. If the number of modules in the stripe is N, the parity redundancy is M, and the L modules of the memory contain data from two stripes, the probability of data loss due to failure is expressed as P = (LM) / (NM) . That is, if the order of parity is more than modules having overlapping data, data is not lost due to a module failure. For example, if a single parity is used, the first failure does not cause data loss in a configuration as long as one module in the data does not overlap at all. Two module faults in a group of modules where the data of the stripes are stored may be required. (2-1) / (6-2) = 1/2, where another module failure can result in irrecoverable data loss, for a stripe of length 5 and a sequence of parity 1, There will be one opportunity with four.

Then, in general, if highly reliable basic data storage is desired, the ordering of the parity in the module and the overlapping of the stripes should be managed so that this dual data loss does not occur. When a module failure occurs, there is a lot of storage that can be applied to recover data. The lost data can be recovered to an available data area as described above. Alternatively, a replicate stripe may be read for the lost data location and inserted in place of the lost data in the original stripe. Alternatively, data from the replica stripe may be used to verify data recovered from the parity of the first log stripe. In another aspect, the replicated data log can be checkpointed to back up the storage in the event of a failure in the first data log, thereby preserving the data. Various combinations of the above methods may be contemplated, and one consideration may be to restore the data with minimal impact to the performance of other operations of the memory system or to recover lost data within the earliest possible time, or from a combination of two logs And minimizing the probability of loss of data. For example, a policy may be a policy that holds an erase hide for at least one log. The choice of policy or combination of policies may vary according to user expectations, and the user may be one of a plurality of users of the memory system.

Including the selection of RAID stripes or striped clusters over which one or more users, data, data fidelity, data reliability, data encryption, or other characteristics may have common attributes, to manage the selection and execution of various policies. "Can be defined. These attributes may also include response time, read latency, write bandwidth, block size, I / O operations per second, and so on. A particular example may be a logical unit number (LUN), a partition, or any other management or performance grouping of data, but the stripe group is not intended to be limited to configurations that are commonly understood to be LUNs. However, the stripe group may include predefined or extensible (logical or physical) memory regions that can be mapped to physical memory regions used to manipulate data, whether stored or not.

One or more users may share this stripe group, or a stripe group may be assigned to each user, and the user may be a customer of the memory system operator, an operating program in a suite of software, and so on. In the case of a module failure, address ranges may be combined with a particular stripe group and associated attributes. Based on the attributes, a policy may be selected to maintain the performance of the stripe group according to certain attributes or to restore performance to the pre-failure state. This policy may be different for each stripe group and may be modified to accommodate the requirements of other stripe groups.

Although the present invention has been described with reference to the above examples, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the following claims, including all equivalents, are intended to define the spirit and scope of the present invention.

Claims (17)

A plurality of memory modules each having a data writing and reading capability,
Wherein one module group of the plurality of modules stores user data and parity data for the user data,
The write or erase operation of the module group is configured to provide all the user data at the time of the read request or the user data requested by the parity data less than all the user data at the time of the read request, Is less than the time interval in which one of the module groups is in the erased state. The method according to claim 1,
The module further comprises a controller configured to issue a read command to the modules of the module group, and the read command received by the module as long as the module is in the write or erase state, after the delay time or after the successive command to cancel the read command Canceled memory system. The method according to claim 1,
If the read command is pending in the module, the data received in the read command is protected from erasure until the read command is executed or canceled. delete The method according to claim 1,
Wherein the data allocation to the module group comprises assigning groups of user data addresses and parity data addresses to a memory stripe of the RAID stripes according to a generation pattern in the logical address space. 6. The method of claim 5,
Wherein two of the plurality of RAID stripes share a single memory module. 6. The method of claim 5,
Wherein the two stripes of the plurality of RAID stripes share many memory modules below the parity order for the corresponding RAID stripes. Providing a plurality of memory modules each having an ability to write and read data;
Storing data and parity data for the data in one module group of the plurality of memory modules;
The erase operation of the module group is performed so that the user data is provided in response to the read request by either reading all the user data at the time of the read request or reading the user data and the parity data for the user data smaller than all the user data at the time of the read request Comprising:
Wherein all user data, or less user data, and less user data and parity data for user data are read in a time period that is less than a time interval during which one of the module groups is in an erased state. 9. The method of claim 8,
Receiving a read command from the control unit to modules of the module group; And
Further comprising canceling a read command received by the module after the delay time or after the receipt of a subsequent command to cancel the read command and in the erase state. 9. The method of claim 8,
Further comprising the step of protecting the data that has been read from the erase until the read command is executed or canceled. 9. The method of claim 8,
Storing user data and parity data comprises:
Further comprising assigning groups of user data addresses and parity data addresses to a memory stripe memory module in accordance with a generation pattern in the logical address space. 12. The method of claim 11,
Wherein two of the plurality of RAID stripes share a single memory module. 12. The method of claim 11,
Wherein the two stripes of the plurality of RAID stripes share many memory modules below the parity order for the corresponding RAID stripes. delete delete delete delete

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