KR101409645B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device capable of removing an afterimage to improve image quality is disclosed.

A liquid crystal display according to the present invention includes a gate driver for driving a liquid crystal panel, a power supply for generating a driving voltage for driving the liquid crystal panel and the gate driver, a normal mode / On / off control signal in accordance with a sleep mode signal, and a controller for switching a driving voltage to be supplied to the liquid crystal panel and the gate driver from the power supply unit in accordance with a power-on / off control signal from the timing controller And a discharge unit driving the gate driver to discharge the voltage stored in the pixels in the liquid crystal panel for a predetermined period of time when the liquid crystal display panel is driven to enter either the sleep mode or the power- .

EDID voltage, input voltage (Vcc)

Description

[0001] Liquid crystal display device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality by eliminating afterimage.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell can actively control the switching device This is advantageous for video implementation. Such a liquid crystal display device is largely composed of a liquid crystal panel for displaying an image and a driving part for driving the liquid crystal panel. The liquid crystal panel includes a plurality of pixels as shown in FIG.

1, each pixel includes a gate line GL, a data line DL arranged to cross the gate line GL, and a portion where the gate line GL intersects with the data line DL And a pixel electrode (not shown) electrically connected to the thin film transistor (TFT). Specifically, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode thereof is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc, (Cst). The storage capacitor Cst charges the data voltage applied from the data line DL when the thin film transistor TFT is turned on to maintain the voltage of the liquid crystal cell Clc constant .

When a gate scan signal is applied to the gate line GL, the thin film transistor TFT is turned on to form a channel between the source electrode and the drain electrode, To the pixel electrode of the liquid crystal cell Clc. At this time, the liquid crystal molecules of the liquid crystal cell Clc are changed in arrangement by the electric field between the pixel electrode and the common electrode to modulate the incident light.

A state in which pixels are driven, that is, a state in which the liquid crystal display device is turned on, can be divided into a normal mode and a sleep mode. The normal mode means a state in which both the timing controller of the liquid crystal display device and the liquid crystal panel and the driving portion driving the liquid crystal panel are driven, and the sleep mode means that only the timing controller of the liquid crystal display device is driven. Exactly, the sleep mode means a state in which the liquid crystal display device is not used for a predetermined period of time when the liquid crystal display device is in the normal mode, or a state in which the power applied to the liquid crystal display device is turned off.

When the liquid crystal display device is changed from the normal mode to the sleep mode, the power applied to the liquid crystal display device is turned off, so that the thin film transistor TFT of the liquid crystal display device in which the pixels are driven turns- off. When the thin film transistor TFT is turned off, the voltage stored in the storage capacitor Cst flows through the data line DL through the thin film transistor TFT, A discharging loop, which is a loop that is disjoint to ground, is not formed. In this case, the voltage stored in the storage capacitor Cst of each pixel is displayed as a residual image on the liquid crystal panel.

As a result, when the liquid crystal display device enters the sleep mode in the normal mode, the voltage stored in the pixel in the normal mode is displayed as a residual image on the liquid crystal panel, thereby causing a problem such as deterioration of image quality.

An object of the present invention is to provide a liquid crystal display device capable of sufficiently securing a discharge time upon entering a sleep mode in a normal mode.

An object of the present invention is to provide a liquid crystal display device capable of removing afterimage.

An object of the present invention is to provide a liquid crystal display device capable of improving image quality.

According to an aspect of the present invention, there is provided a liquid crystal display including a gate driver for driving a liquid crystal panel, a power supply for generating a driving voltage for driving the liquid crystal panel and the gate driver, On / off control signal in accordance with a normal mode / sleep mode signal from the system, and a controller for controlling the power supply to the liquid crystal panel and the gate driver from the power supply unit in accordance with a power- A driving voltage switching unit for switching a driving voltage to be supplied and an external power source to drive the gate driver when entering either a sleep mode or a power-off mode, so that a voltage stored in the pixels in the liquid crystal panel And a discharging part for discharging for a predetermined period.

The liquid crystal display according to the present invention is driven by the EDID voltage (V-EDID) which maintains the high level when the external system is on regardless of the sleep mode and the power-off mode The voltage stored in the pixel can be sufficiently discharged when the mode is changed to the sleep mode or the power-off mode in the normal mode. This makes it possible to prevent a residual image from being generated when the liquid crystal display device is changed from the normal mode to the sleep mode or the power-off mode.

Further, the liquid crystal display device according to the present invention can prevent afterimage and improve image quality.

Other objects, other features, and other advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

Best Mode for Carrying Out the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view showing a liquid crystal display device according to the present invention.

2, the liquid crystal display according to the present invention includes a liquid crystal panel 102 displaying a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm arranged to display an image, A gate driver 104 for driving the plurality of gate lines GL1 to GLn; a data driver 106 for driving the plurality of data lines DL1 to DLm; A timing controller 108 for controlling the LCD 106, and an EDID IC 110 storing the overall operation program and basic information of a liquid crystal display for displaying an image.

In addition, when the liquid crystal display according to the present invention is changed to the sleep mode or the power-off mode, the EDID (Extended Display Identification Data) is supplied from an external system to discharge the voltage charged in the pixels of the liquid crystal panel 102, A discharging unit 114 driven by an EDID voltage V-EDID input to the IC 110 and a DC generating unit 110 for generating an input voltage Vcc for driving the timing controller 108 and the discharging unit 114. [ Which supplies the input voltage Vcc to the discharge unit 114, the gate and data drivers 104 and 106, and the liquid crystal panel 102 under the control of the DC / DC converter 112 and the timing controller 108, And a voltage switching unit 113.

The liquid crystal panel 102 includes pixels formed in regions divided by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. Each of these pixels includes a thin film transistor TFT formed at an intersection between a corresponding gate line GL and a corresponding data line DL and a thin film transistor TFT formed between the thin film transistor TFT and the common electrode Vcom, (Clc).

The thin film transistor TFT switches the pixel data voltage to be supplied to the corresponding liquid crystal cell Clc from the corresponding data line DL in response to the gate scan signal on the corresponding gate line GL. The liquid crystal cell Clc is composed of a common electrode facing the liquid crystal layer and a pixel electrode connected to the thin film transistor TFT. This liquid crystal cell Clc charges the pixel data voltage supplied via the corresponding thin film transistor (TFT). In addition, the voltage charged in the liquid crystal cell Clc is updated each time the corresponding thin film transistor TFT is turned on.

In addition, each of the pixels on the liquid crystal panel 102 has a storage capacitor Cst connected between the thin film transistor TFT and the previous gate line. The storage capacitor Cst minimizes the natural reduction of the voltage charged in the liquid crystal cell Clc.

The gate driver 104 sequentially supplies a plurality of gate scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signals GCS from the timing controller 110. [ The plurality of gate scan signals enable a plurality of gate lines GL1 to GLn to sequentially enable one horizontal sync signal interval. The gate driver 104 drives the plurality of gate lines GL1 to GLn by a high pulse supplied from the discharger 114 when the liquid crystal display device is switched to the sleep mode or the power- (on).

In response to the data control signals DCS from the timing controller 110, the data driver 106 outputs a plurality of pixel data voltages (hereinafter referred to as " pixel data voltages ") every time one of the plurality of gate lines DL1 to DLm is enabled And supplies them to the plurality of data lines DL1 to DLm on the liquid crystal panel 102, respectively. To this end, the data driver 106 inputs pixel data (Data) from an external system one line at a time, and supplies pixel data (Data) of one line inputted using a gamma voltage set to pixel data Voltages.

The timing controller 108 receives a data clock DCLK, a horizontal synchronizing signal Hsync, and a vertical synchronizing signal from an external system (for example, a graphics module of a computer system or a video demodulation module of a television receiving system) (GCS) and data control signals (DCS) using a data enable signal (Vsync) and a data enable signal (DE). The gate control signals GCS are supplied to the gate driver 104 and the data control signals DCS are supplied to the data driver 106.

The timing controller 108 controls the input voltage switching unit 113 according to a normal mode / sleep mode signal supplied from an external system. Specifically, the timing controller 108 supplies a power-on (ON) control signal to the input voltage switching unit 113 when a signal indicating normal mode is supplied from an external system. The input voltage switching unit 113 supplies the input voltage Vcc supplied from the DC / DC converter 112 to the discharging unit 114 and the gate and data driver 114 according to the power- (104, 106) and the liquid crystal panel (102), respectively. Further, when a signal indicative of a sleep mode is supplied from an external system, the timing controller 108 supplies a power-off (OFF) control signal to the input voltage switching unit 113. The input voltage switching unit 113 supplies the input voltage Vcc supplied from the DC / DC converter 112 to the discharge unit 113 and the gate and data driver (not shown) according to the power- 104, and 106 and the liquid crystal panel 102 are not supplied.

The EDID IC 110 stores an overall operation program and basic information of a liquid crystal display device for displaying an image in advance. At this time, the operating program and the basic information are written to the EDID IC 110 by a ROM writer (not shown). The basic information includes brightness, contrast, color temperature, and screen position of a displayed image, a power-up logo, an on-screen display time (OSD timeout, language, and DVI Enable menu items.

The external system sets a synchronization signal (Vsync, Hsync), a data enable (DE) signal, a clock signal (DCLK), etc. according to the operation program and basic information supplied from the EDID IC 110, To the timing controller (108). At this time, the EDID voltage (V-EDID) is a voltage supplied to the liquid crystal display device for the first time as soon as an external system is turned on.

The DC / DC converter 112 drives the driving unit (for example, the gate driver 104 and the data driver 106, the discharging unit 114, and the timing controller 108) for driving the liquid crystal panel 102 And generates an input voltage Vcc, which is a voltage. The input voltage Vcc generated by the DC / DC converter 112 is supplied to the timing controller 108 and the input voltage switching unit 113, respectively. The timing controller 108 is driven by the input voltage Vcc supplied to the timing controller 108. [ The input voltage Vcc supplied to the input voltage switching unit 113 is controlled by a power-on / off (ON / OFF) control signal supplied from the timing controller 108 as described above.

The input voltage switching unit 113 is controlled according to a power-on / off control signal supplied from the timing controller 108. The input voltage switching unit 113 supplies the input voltage Vcc supplied from the DC / DC converter 112 to the liquid crystal panel 102 when a power-on control signal is supplied from the timing controller 108. [ To the gate driver and the data driver (104, 106) for driving the liquid crystal panel (102). At the same time, the input voltage switching unit 113 also supplies the input voltage Vcc to the discharger 114. When the power control signal is supplied from the timing controller 108, the input voltage switching unit 113 switches the input voltage Vcc to the liquid crystal panel 102 and the liquid crystal panel 102 And is not supplied to the driving gate and data drivers 104 and 106. [ Similarly, the input voltage switching unit 113 does not supply the input voltage Vcc to the discharge unit 114 as well.

When the liquid crystal display according to the present invention is switched to the sleep mode or the power-off mode, the discharge unit 114 applies the EDID voltage (V-EDID) to discharge the voltage stored in the pixels in the liquid crystal panel 102 . As shown in FIG. 3, the discharger 114 detects the level of the input voltage Vcc supplied from the input voltage switching unit 113 and generates an input voltage Vcc to generate a comparison signal according to the detection result An inverter 118 for inverting and outputting a comparison signal supplied from the input voltage Vcc sensing unit 116 and a timing when a logic value of the signal output from the inverter 118 is changed And a monostable multivibrator 120 that generates a high pulse for a predetermined period as a reference.

The input voltage (Vcc) sensing unit 116 senses that the input voltage Vcc supplied from the input voltage switching unit 113 is reduced to a predetermined voltage (reference value) or less and outputs a signal having a different logic value And generates a comparison signal. Specifically, when the level of the input voltage Vcc supplied from the input voltage switching unit 113 is greater than the reference value, the input voltage Vcc sensing unit 116 outputs a logic level of a specific logic (for example, High) And generates a comparison signal. When the level of the input voltage Vcc supplied from the input voltage switching unit 113 is smaller than the reference value, the input voltage Vcc sensing unit 116 compares the level of the base logic (e.g., Low) Signal. When the level of the input voltage Vcc supplied from the input voltage switching unit 113 becomes smaller than the reference value, the liquid crystal display device enters the sleep mode or the power-off mode. Therefore, it is possible to determine whether the liquid crystal display device has entered the sleep mode or the power-off mode according to the logical value of the comparison signal generated by the input voltage (Vcc) The comparison signal generated by the input voltage (Vcc) sensing unit 116 is supplied to the inverter 118. At this time, the input voltage (Vcc) sensing unit 116 is driven by the EDID voltage (V-EDID).

The inverter 118 is driven by the EDID voltage V-EDID and inverts and outputs the base logic Low and specific logic High comparison signals supplied from the input voltage Vcc sensing unit 116 . Specifically, the inverter 118 inverts the comparison signal of the specific logic High to a low level when a comparison signal of a specific logic level is supplied from the input voltage Vcc sensing unit 116 And outputs the inverted low signal. The inverter 118 inverts the comparison signal of the base logic (Low) to a high state when a base comparative signal (Low) is supplied from the input voltage (Vcc) sensing unit 116, And outputs a high signal. The high or low signal output from the inverter 118 is supplied to the monostable multivibrator 120.

The monostable multivibrator 120 generates a high pulse for a predetermined period based on a time point at which a logical value of a signal output from the inverter 118 changes. More specifically, the monostable multivibrator 120 generates a monostable multivibrator 120 for a predetermined period of time based on a time point at which the signal output from the inverter 118 changes from a low state to a high state (for example, a rising edge) Generates a high pulse and supplies it to the gate driver (104 in Fig. 2) shown in Fig. In this case, the predetermined period means a time period during which the voltages charged in the pixels in the liquid crystal panel 102 can be sufficiently discharged when switching to the sleep mode or the power-off mode. For example, the predetermined period may be about 2 to 4 frames.

The high pulse generated from the monostable multivibrator 120 is extinguished when the certain period elapses, and the monostable multivibrator 120 becomes stable. The monostable multivibrator 120 maintains a stable state until a new input signal is input.

When a high pulse is supplied from the monostable multivibrator 120, the gate driver 104 supplies a high-level voltage corresponding to the high pulse to the gate driver 104 electrically (GL1 to GLn in FIG. 2) connected to the plurality of gate lines GL1 to GLn so that the plurality of gate lines GL1 to GLn are turned on. When the plurality of gate lines GL1 to GLn are turned on, the TFTs connected to the plurality of gate lines GL1 to GLn are turned on. The plurality of gate lines GL1 to GLn are turned on to turn on the thin film transistors TFT that are electrically connected to the plurality of gate lines GL1 to GLn.

The TFT is turned on at the moment when the liquid crystal display device is changed from the normal mode to the sleep mode or the power-off mode, so that the liquid crystal panel shown in Fig. 2 102 are discharged. The thin film transistor TFT is turned on so that a discharging loop from the thin film transistor TFT to the ground through the data line DL is formed, The voltage stored in the pixels is discharged through the discharging loop. The voltage stored in the pixels in the liquid crystal panel 102 when the liquid crystal display device is switched to the sleep mode or the power-off mode is sufficiently discharged by the discharge unit 114 driven by the EDID voltage (V-EDID) .

The discharge unit 114 is always connected to the EDID voltage (V-EDID) that maintains a high level at all times as long as the liquid crystal display device is turned on to the external system irrespective of the sleep mode or the power-off mode The voltage stored in the pixels in the liquid crystal panel 102 can be sufficiently discharged when the liquid crystal display device is switched to the sleep mode or the power-off mode.

Accordingly, the liquid crystal display according to the present invention can prevent the afterimage from occurring when the mode changes from the normal mode to the sleep mode or the power-off mode, thereby improving the image quality.

FIG. 4 is a waveform diagram showing a driving voltage when the liquid crystal display of FIG. 2 changes state from a normal mode to a sleep mode or a power-off mode.

As shown in FIGS. 2 to 4, when the liquid crystal display according to the present invention is in the normal mode, the EDID voltage V-EDID and the input voltage Vcc are maintained at a high level, The input voltage (Vcc) sensing unit (116 of FIG. 3) also outputs a comparison signal of a specific logic (High). The inverter (118 in FIG. 3) shown in FIG. 3 outputs the comparison signal of the specific logic High at a low level by the input voltage (Vcc) And outputs the inverted low signal.

The monostable multivibrator (120 in FIG. 3) shown in FIG. 3 does not generate any pulse in the normal mode state.

The EDID voltage V-EDID maintains a high level as in the normal mode when the liquid crystal display according to the present invention changes from the normal mode to the sleep mode or the power-off mode, while the input voltage Vcc Is gradually turned to a low level and turned off. The input voltage Vcc sensing unit 116 outputs a comparison signal according to the level change of the input voltage Vcc. When the level of the input voltage Vcc is higher than a predetermined voltage (for example, 2.3 V) And outputs a comparison signal of the base logic (Low) from the falling point.

The inverter 118 shown in FIG. 3 inverts the comparison signal of the base logic (Low) to a high state by outputting the comparison signal of the base logic (Low) by the input voltage (Vcc) And outputs the inverted high signal.

The monostable multivibrator 120 generates a high pulse for a predetermined period based on the instant when the signal output from the inverter 118 changes from low to high. The high pulse outputted from the monostable multivibrator 120 is supplied to the gate driver (104 in FIG. 2) shown in FIG. The gate driver 104 supplies a gate signal corresponding to the high pulse to the plurality of gate lines GL1 to GLn to turn on the plurality of gate lines GL1 to GLn. As the plurality of gate lines GL1 to GLn are turned on, the thin film transistors (TFTs) electrically connected to the plurality of gate lines GL1 to GLn are turned on.

The thin film transistor TFT is turned on so that a discharging loop from the thin film transistor TFT to the ground through the data line DL is formed, The voltage stored in the pixels is discharged through the discharging loop. At this time, a period for generating a high pulse in the monostable multivibrator 120 is a discharge period in which the voltage stored in the pixels in the liquid crystal panel 102 is discharged.

The external system is turned on regardless of the input voltage Vcc sensing portion 116 and the inverter 118 and the monostable multivibrator 120 irrespective of the sleep mode or the power-off mode of the liquid crystal display The voltage stored in the pixels in the liquid crystal panel 102 can be sufficiently discharged due to being driven by the EDID voltage (V-EDID) which always maintains a high level. Therefore, the liquid crystal display according to the present invention can prevent the afterimage from occurring when the mode is changed from the normal mode to the sleep mode or the power-off mode. The liquid crystal display device according to the present invention can improve the image quality as the afterimage is prevented.

In addition to the embodiment of the present invention, for example, in the embodiment, the input voltage sensing unit and the inverter are removed, and the monostable multivibrator is connected to the gate driver in response to the power ON / OFF control signal from the timing controller Discharge operation can be performed. Also in this case, since the monostable multivibrator is driven by the EDID voltage (V-EDID), the discharge operation can be performed sufficiently when the liquid crystal display device is changed to the sleep mode or the power-off mode.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, many variations and modifications may be made without departing from the spirit and scope of the invention. Accordingly, It will be apparent that modifications and other equivalent embodiments are possible.

1 is a structural view of a pixel constituting a general liquid crystal panel;

2 is a view showing a liquid crystal display device according to the present invention.

Fig. 3 is a detailed view of the discharge unit of Fig. 2; Fig.

FIG. 4 is a waveform diagram showing a driving voltage when the liquid crystal display of FIG. 2 is changed from a normal mode to a sleep mode or a power-off mode; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

102: liquid crystal panel 104: gate driver

106: Data driver 108: Timing controller

110: EDID IC 112: DC / DC converter

113: input voltage switching unit 114:

116: input voltage (Vcc) sensing unit 118: inverter

120: Monostable multivibrator

Claims (8)

A gate driver for driving the liquid crystal panel; A power supply unit for generating a driving voltage for driving the liquid crystal panel and the gate driver; A timing controller for controlling the gate driver and generating a power-on / off control signal in accordance with a normal mode / sleep mode signal from an external system; A driving voltage switching unit for switching a driving voltage to be supplied to the liquid crystal panel and the gate driver from the power supply unit according to a power-on / off control signal from the timing controller; And And a discharging unit driven by an external power source to discharge the voltage stored in the pixels in the liquid crystal panel by driving the gate driver when entering the sleep mode or the power supply off mode, Wherein the discharge unit determines the time of entry into the sleep mode or the power-off mode based on a change in the driving voltage output from the driving voltage switching unit, drives the gate driver, Discharges the voltage for a certain period of time, The power supply voltage sensing unit inverts the comparison signal supplied from the power supply voltage sensing unit and outputs the inverted signal to the discharging unit. And a monostable multivibrator for generating a specific pulse for a predetermined period based on a time point at which the driving voltage is cut off and supplying the specific pulse to the gate driver. The method according to claim 1, Wherein the external power source includes an EDID voltage. delete delete The method according to claim 1, The discharge unit determines the time of entering the sleep mode or the power-off mode in response to the power-on / off control signal from the timing controller, drives the gate driver, And discharges the voltage for a predetermined period of time. The method according to claim 1, Wherein the predetermined period of time is about 2 to 4 frames. The method according to claim 1, Wherein the external power source always has a high level when an external system is driven regardless of a sleep mode or a power-off mode of the liquid crystal display device. The liquid crystal display of claim 1, wherein in the normal mode state, the monostable multivibrator does not generate a pulse.

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