KR101408808B1 - A semiconductor device with have bridge shaped spacer structure in the gate electrode and method for manufacturing the same - Google Patents

Abstract

There is provided a method of forming a semiconductor device having a gate having a bridge type spacer inside a gate electrode and a gate thereof, and a semiconductor device and a system device using the semiconductor device formed thereby. As the width of the gate electrode narrows due to the reduction of the design rule, the leakage current (GIDL) of the source drain caused by the gate electrode is increasing. In order to solve such a problem, a bridge type spacer is formed in the gate electrode, and a gate electrode which blocks the leakage current (GIDL) of the source drain caused by the gate is formed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode having a bridge type spacer in a gate electrode, a semiconductor device using the gate electrode, and a method of manufacturing the same. 2. Description of the Related Art A semiconductor device having a bridge-

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming a gate electrode having a gate electrode shape having a bridge-shaped spacer inside a gate electrode, and a structure and a manufacturing method of a semiconductor device using the same. .

As the semiconductor device is highly integrated, the area occupied by the unit cells is decreasing, resulting in a short channel effect as the channel length decreases. Particularly, as the design rule is reduced, the leakage current increases due to the short channel effect and the increase of the ion implantation amount, and it becomes difficult to secure the refresh time.

Therefore, in order to secure a sufficient channel length, a recess channel array transistor (RCAT) has a structure in which a channel length is increased by forming a recess channel trench in a region to be a channel of a transistor .

The present invention relates to a transistor having the above-mentioned recess channel and a semiconductor device using the same. A transistor with a common recess channel forms an inner spacer at the gate sidewall to address the gate induced drain leakage (GIDL) problem.

RCAT, which has an inner spacer, also faces a problem that it can not catch the limit of process and GIDL problem fundamentally due to the reduction of design rule.

The present invention provides a semiconductor device having a bridge-type spacer inside a recessed transistor gate electrode to overcome this problem, and a method of manufacturing the same.

Recently, as the degree of integration of semiconductor memory products is accelerated, the unit cell area is greatly reduced, and the line width of the pattern and the interval between the patterns are remarkably narrowed. In order to solve this problem, the device is formed in a vertical structure, a stack structure, or a new material is used in order to reduce the unit cell area but maintain the electrical characteristics required by the device.

RCAT or SRCAT with a trench-type electrode gate with an increased effective channel length has been developed and used to meet this demand.

Figures 1 and 2 are cross-sectional and electron micrographs showing commonly used RCAT or SRCAT.

3 shows a cross-sectional view of the structure of a commonly used RCAT. The RCAT forms a trench in the substrate 10 to form a gate dielectric layer 20 in the trench and a spacer 50 on the outer sidewalls of the gate electrode 40. The inner spacer 30 is formed on the sidewall of the gate electrode 40 to prevent GIDL.

Referring to FIG. 4, it can be seen that as the depth of the spacer increases, the GIDL decreases with the depth of the inner spacer.

Referring to FIG. 5, the thicker the inner spacer is, the smaller the GIDL is.

In future DRAM devices require less than 4F ² (F: minimum feature size), it is difficult to use internal spacers in RCAT or SRCAT in existing form, and if the GIDL problem can not be solved, And the vertical pillar transistor (VPT) should be used.

The present invention overcomes the above-mentioned problems of the general RCAT or SRCAT and provides an improved RCAT and SRCAT structure with a bridge type internal spacer that can extend the life of the RCAT technology, I want to employ.

SUMMARY OF THE INVENTION An object of the present invention is to make a RCAT gate electrode structure and to make a spacer of a bridge structure inside a gate electrode to make a semiconductor device without GIDL (gate induced drain leakage) phenomenon.

It is another object of the present invention to make a SRCAT gate electrode structure and to form a spacer in a bridge structure inside a gate electrode to make a semiconductor device without GIDL (gate induced drain leakage) phenomenon.

It is another object of the present invention to provide a memory semiconductor device that makes a transistor without a gate induced drain leakage (GIDL) phenomenon by making a spacer having a bridge structure inside a gate electrode while forming an RCAT or SRCAT gate electrode structure.

According to an aspect of the present invention, there is provided a method of fabricating a gate electrode having a spacer having a bridge structure inside a gate electrode, the method including: forming an isolation layer on a semiconductor substrate; Forming a recessed hole in the active region, forming a sacrificial layer in the recessed hole, forming a bridge-shaped spacer material layer on the sacrificial layer, recessing a part of the side surface of the isolation layer, A sacrificial layer is removed using the connection hole, and a gate electrode integrally connected to the space where the sacrificial layer is removed and the upper portion of the connection hole and the spacer is formed.

According to another embodiment of the present invention, there is provided a method of manufacturing a gate electrode having a bridge structure inside a gate electrode, the method comprising: forming an isolation film on a semiconductor substrate; separating the active region from the inactive region; Forming a lower electrode material layer in the recess hole, forming a spacer material layer in the form of a bridge on the lower one-electrode material layer, recessing a part of the side surface of the isolation film, And an upper electrode layer which is integrally connected to the lower electrode layer is formed on the connection hole and the spacer.

A method of manufacturing a memory device having a gate electrode having a bridge structure spacer inside a gate electrode according to another embodiment of the present invention includes the steps of: forming an isolation film on a semiconductor substrate; separating the active region from the inactive region; Forming a lower electrode material layer in the recess hole, forming a spacer material layer in a bridge shape on the lower electrode material layer, and recessing a part of the side surface of the isolation film to form a recessed hole in the lower electrode material layer, Forming a connection hole to be connected to the material layer, forming an upper electrode layer integrally connected to the lower electrode layer on the connection hole and the spacer, forming a first interlayer insulating film on the integrated gate, Forming a DC hole, forming a bit line, forming a second interlayer insulating film on the bit line, forming a BC hole Forming an L-Sitting CONTEC pad, and, and a mold layer on the capacitor CONTEC pad forming a capacitor lower electrode is formed to form a capacitor dielectric film on the lower electrode, and forming a capacitor upper electrode on the capacitor dielectric film.

Although the present invention is described in detail with reference to the accompanying drawings, the present invention is not limited to the following embodiments, The present invention can be embodied in various forms without departing from the technical idea.

As described above, according to the present invention, when a spacer having a bridge-type structure is formed in the gate electrode, a semiconductor device without GIDL (gate induced drain leakage) phenomenon can be obtained.

In addition, if a spacer having a bridge type structure is formed in the gate electrode, a transistor having no gate induced drain leakage (GIDL) phenomenon can be fabricated and a memory semiconductor device using the transistor can be obtained. By suppressing the GIDL phenomenon and creating a DRAM, which is a memory device, it is possible to reduce the refresh and design the device cell to be minimized.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, And should not be construed as limited to the embodiments described in the foregoing description.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Method of forming an RCAT with a bridge type spacer inside the electrode Example 1

FIGS. 6A and 17B are process cross-sectional views illustrating a method of forming the RCAT in which the bridge type spacer of the present invention is inside the gate electrode.

A in each drawing shows a section taken along the X-axis (or bit line BL), and B shows a section taken along the Y-axis (or word line WL).

Referring to FIG. 6A, a pad oxide film 105 is formed on a semiconductor substrate 100. The pad oxide film 105 is formed by a thermal oxidation method and is formed to a thickness of about 50 to 150 ANGSTROM.

A first hard mask layer 110 is formed on the pad oxide layer 105. The first hard mask layer 110 is used as a material having an etching rate different from that of the semiconductor substrate 100 and the pad oxide layer 105. For example, it can be used as a silicon nitride film.

A device isolation layer 115 is formed on the semiconductor substrate 100 by forming a predetermined pattern using the first hard mask 110 as a mask to divide the substrate into an active region and a non-active region.

A shallow trench isolation (STI) process is used to form the device isolation film 115. The trench is formed by forming a slight thermal oxide film after the formation of the trench and forming a liner with a nitride film as necessary. Then, the trench is filled through the CVD or HDP process Planarize.

Referring to FIG. 6B, the cross section formed in FIG. 6A is cut along the Y-axis direction, and all processes are the same as in FIG. 6A.

The semiconductor substrate 100 is divided into an active region and an inactive region by an isolation film 115. A portion where the device isolation film 115 is present is an inactive region, and a portion where the device isolation film 115 is not present is an active region and a portion where a transistor is to be formed.

Referring to FIG. 7A, the first hard mask 110 is removed, and the upper portion of the device isolation film 115 is planarized. Then, a second hard mask 120 layer is formed again. The second hard mask 120 layer uses the same material as the first mask layer. The pad oxide film 105 is removed and then grown and used in the same manner.

Referring to FIG. 7B, the cross section formed in FIG. 7A is cut in the Y-axis direction, and all processes are the same as in FIG. 7A.

Referring to FIG. 8A, on the second hard mask layer, a gate mask layer (not shown) is formed of a plurality of material layers, though it is not illustrated in the drawing. The lower layer was formed with a plasma CVD oxide film at a thickness of 2000 angstroms to 3000 angstroms thick and the intermediate layer was formed with an amorphous carbon layer (ACL) layer with 2000 angstroms to 3000 angstroms thick as an organic film, layer is formed to a thickness of about 500 angstroms. A predetermined pattern is formed on the second hard mask layer 120 using the gate mask layer as a mask pattern and a recess hole 125 is formed in the active region as a mask with the second hard mask layer 120 after the removal of the gate mask layer do.

The recess hole 125 may be formed as a space in which the gate electrode is to be formed and may have a rounded bottom to increase the surface area. However, the first embodiment of the present invention focuses on the features of the present invention, and such a process and a description thereof will be omitted.

Although not shown in the figure, a slight thermal oxide film can be formed in the recess hole 125 to cope with the following process and the situation such as the etching rate of the substrate. Such a thermal oxide film is formed to form a sacrificial layer under the recess hole 125 and prevent the substrate from being etched when removed.

Referring to FIG. 8B, the cross section formed in FIG. 8A is cut along the Y-axis direction, and all processes are the same as in FIG. 8A.

Referring to FIG. 9A, a sacrificial layer 130 is formed on the recess 125 and the second hard mask 120. Silicon germanium (SiGe) is used as the sacrificial film 130 material. Silicon germanium (SiGe) can be used as an excellent sacrificial layer since the etching rate can be different from that of the semiconductor substrate 100, the element isolation film 115 and the nitride film.

The sacrificial layer 130 can be formed of the composite films and other materials having an excellent etch selectivity.

Referring to FIG. 9B, the cross section formed in FIG. 9A is cut in the Y-axis direction, and all processes are the same as those in FIG. 9A.

Referring to FIG. 10A, the sacrificial layer 130 is etched back to the bottom of the recess hole. The upper portion of the remaining sacrificial layer 133 is a space in which the spacer is to be formed. As shown in FIG. 4, the spacer forming depth has a GIDL effect on the device, and the height of the remaining sacrificial layer 133 is well calculated. In the present invention, the sacrificial film is removed with a thickness of 500 to 1000 Å.

Referring to FIG. 10B, the cross section formed in FIG. 10A is cut in the Y-axis direction, and all processes are the same as those in FIG. 10A.

Referring to FIG. 11A, a spacer 135 layer is formed on the remaining sacrificial layer 133 and the second hard mask 120 layer to be used as a spacer. As the layer material of the spacer 135, a nitride film or an oxide film is used.

Referring to FIG. 11B, the cross section formed in FIG. 11A is cut in the Y-axis direction, and all processes are the same as in FIG. 11A.

Referring to FIG. 12A, the spacer 135 is etched back to form a bridge-type spacer 138. The bridge type spacer 138 is a bridge structure connected to an active region to be a source drain. Therefore, if the upper surface of the bridge spacer is formed below the surface of the substrate 100, the GIDL can not be sufficiently blocked. Therefore, at least the upper surface of the bridge spacer should be formed to coincide with or slightly higher than the surface of the substrate 100.

It should be considered that the bottom surface of the bridge spacer 138 can be formed below the source drain junction in forming the remaining sacrificial film 133, although the bottom depth is also already determined.

Referring to FIG. 12B, the cross section formed in FIG. 12A is cut in the Y-axis direction, and all steps are the same as those in FIG. 12A.

Referring to FIG. 13A, the bridge spacer 138 and the second hard mask layer 120 are covered with the photoresist mask 140.

Referring to FIG. 13B, the photoresist mask 140 is formed in an open state at a boundary between an active region and an inactive region. Using the photoresist mask 140 as a mask, the open region at the boundary between the active region and the inactive region is etched to form a connection hole 145. The formed connection hole 145 becomes a passage through which the etchant passes when the remaining sacrificial film 133 is removed and a source gas through which the necessary source gas is to pass when forming the gate electrode again after the removal of the remaining sacrificial film 133.

Therefore, the connection hole 145 is not formed in the X-axis direction 13A in the X-axis direction active area and the inactive area boundary.

Referring to FIG. 14A, the wet etchant is removed through the connection hole 145 (not seen from the X-axis) to remove the remaining sacrificial layer 133. The remaining sacrificial layer 133 is a silicon germanium (SiGe) layer, and the silicon nitride layer and the oxide layer are not etched but only silicon germanium (SiGe) is etched.

Referring to FIG. 14B, the wet etching solution is supplied through the connection hole 145 to remove the remaining sacrificial layer 133. The remaining sacrificial layer 133 is a silicon germanium (SiGe) layer, and the silicon nitride layer and the oxide layer are not etched but only silicon germanium (SiGe) is etched.

When the remaining sacrificial film 133 is removed, the bridge spacer 138 is in the form of being attached to the bridge pier in the X-axis direction (in contact with both sides of the active region), and the Y- A space is formed and a bridge-type structure is formed.

Referring to FIG. 15A, the photoresist mask 140 and the second hard mask 120 are removed. The gate dielectric layer 150 is formed on the substrate 100 and the space where the remaining sacrificial layer 133 is removed after the substrate on which the photosensitive mask 140 and the second hard mask 120 are removed is cleaned.

The gate dielectric layer 150 forms a silicon oxide layer (SiO 2), a hafnium oxide layer (HFO 2), a tantalum oxide layer (TA 2 O 5), or an ONO (oxide / nitride / oxide) layer.

Referring to FIG. 15B, the photoresist mask 140 and the second hard mask 120 are removed. The gate dielectric layer 150 is formed on the bridge spacer 138 and the remaining sacrificial layer removing space after the substrate on which the photoresist mask 140 and the second hard mask 120 are removed is cleaned.

The gate dielectric layer 150 is formed to be narrower than the bridge spacer 138 and slightly thickened at a portion where the gate dielectric layer 150 is in contact with the substrate 100.

Referring to FIG. 16A, a gate electrode layer 155 is formed on the substrate 100 on which the gate dielectric layer 150 is formed and in the remaining sacrificial layer removal space. Although not shown in the X axis of the figure, the gate electrode layer 155 is formed through the connection hole 145 formed between the active region and the inactive region shown on the Y axis, The upper portion is integrated.

At this time, the bridge spacer 138 is surrounded by the gate electrode 155 (shaded), and is present inside and is not visible on the X axis.

Although the upper portion 155 of the electrode is shown as a single layer in the drawing, the upper portion may form a metal silicide layer in consideration of the resistance of the electrode. In order to form the metal silicide, an electrode layer may be formed in the sacrificial only removal region and the connection hole, and then the polysilicon layer and the metal silicide layer may be formed again after planarization, and then a gate electrode pattern may be formed.

Referring to FIG. 16B, the process of FIG. 16A is cut along the Y-axis. In FIG. 16A, the sacrificial sidewall space and the upper electrode are integrated with each other through the connection hole, When integrated into a memory device, it can be used as a wally line (WL).

And a bridge spacer 138 may be formed in the gate electrode 155.

17A and 17B, a low concentration impurity is formed on the substrate after forming the gate electrode 155, a spacer 160 is formed on the sidewall of the gate electrode 155, and a high concentration impurity is removed by using the sidewall spacer 160 as a mask Thereby forming a source drain 165.

The gate electrode transistor having the final completed bridge type internal spacer has a structure in which the spacer 138 contacts the interface with the source drain 165 formed in the semiconductor substrate 100 and forms a bridge, The lower part of the electrode is formed in the space where the substrate is recessed. The electrodes are integrated with each other through the electrode upper part 155 formed on the substrate and the connection hole 145, bridge type spacers 138 are formed to reliably prevent drain leakage (GIDL) excited by the gate electrode.

The GIDL can be sufficiently suppressed due to the fact that the space existing in the gate electrode is filled with the spacer existing only on the inner side wall of the existing gate. Due to the strong nature of these features, a transistor that can operate the device with much smaller designs can be formed.

Method of forming RCAT and SRCAT in which bridge type spacer is inside electrode Example 2

18A and 25C are cross-sectional views showing another method of forming RCAT and SRCAT of a bridge type spacer of the present invention in an electrode.

Embodiment 2 of the present invention realizes the concept of RCAT in which the bridge type spacer of Embodiment 1 is located inside the electrode. In Embodiment 1, the lower portion of the electrode is formed through the formation and removal of the sacrificial film, A method of directly forming a lower electrode and forming a bridge type spacer on the lower electrode and integrating the upper electrode on the spacer with a connection hole without using a sacrificial film forming and removing process.

In each figure, a is a cross-sectional view in the X direction (bit line BL) at the time of forming the RCAT.

The angle b is a cross-sectional view in the X direction (bit line BL) in the SRCAT formation.

In each figure, c is a cross-sectional view in the Y direction (word line (WL)) when RCAT and SRCAT are formed. For the sake of simplicity, the Y-axis cross section of RCAT and SRCAT appears in the same shape. Therefore, c in each figure is a diagram showing RCAT and SRCAT in common. And the section in the Y-axis direction is generated almost like the X-axis.

In addition, the difference in formation of RCAT and SRCAT is that after the formation of the recess hole, there is only a difference in expanding the lower portion of the recess hole to a circular shape. The characteristic portions describe angles a and b, but in the same process, b The process is shown in the drawing only.

18A, 18B, and 18C, a pad oxide film 205 is formed on the semiconductor substrate 200. [ The pad oxide film 205 is formed by a thermal oxidation method and is formed to a thickness of about 50 to 150 ANGSTROM.

A first hard mask film (not shown) is formed on the pad oxide film 205. The first hard mask film (not shown) is used as a material having an etching rate different from that of the semiconductor substrate 100 and the pad oxide film 105. For example, it can be used as a silicon nitride film.

A device isolation film 115 is formed on the semiconductor substrate 100 by forming a predetermined pattern using the first hard mask (not shown) as a mask to divide the substrate into an active region and a non-active region.

The remaining general description and the process Y-axis related diagrams c are the same as those of the first embodiment, and thus are omitted.

Referring to FIG. 19A, the first hard mask (not shown) is removed and the upper portion of the device isolation film 215 is planarized. Then, a second hard mask 220 layer is formed again. The second hard mask 220 layer uses the same material as the first hard mask layer. A buffer oxide film 210 is formed before the second hard mask 220 is formed.

Although not shown for convenience in the figure on the second hard mask layer, a gate mask layer (not shown) is formed of a plurality of material layers. The lower layer was formed with a plasma CVD oxide film at a thickness of 2000 angstroms to 3000 angstroms thick and the intermediate layer was formed with an amorphous carbon layer (ACL) layer with 2000 angstroms to 3000 angstroms thick as an organic film, layer is formed to a thickness of about 500 angstroms. A predetermined pattern is formed on the second hard mask layer 220 using the gate mask layer as a mask pattern, and a recess hole 225 is formed in the active region as a mask with the second hard mask layer 220 after removing the gate mask layer do.

Referring to FIG. 19B, after the process of FIG. 19A is performed, a nitride layer is formed to a thickness of 200 A on the recess hole 225 by an etch stopping layer (not shown). Thereafter, only the side wall of the recess hole 225 is etched by an etchback process, and the etch stop layer is removed and the underlying portion is removed.

The lower end of the recess hole is expanded by isotropic etching using the etch stopping layer (not shown) as a mask to form a recessed space 227 having an enlarged space. After forming the enlarged recess hole 227, the etch stopping film is removed.

Then, the SRCAT hole 227 in which the lower portion of the recess hole is enlarged is completed.

19C is the same as the description of the first embodiment.

Referring to FIGS. 20A and 20B, a gate dielectric layer 230 is formed on the recessed hole. The gate dielectric layer 230 may be formed using the characteristics required by the selection device, such as a silicon oxide layer (SiO 2), a hafnium oxide layer (HFO 2), a tantalum oxide layer (TA 2 O 5), or an ONO (oxide / nitride / oxide) layer.

Referring to FIGS. 21A, 21B and 21C, a lower electrode film 235 is formed on the recess hole 225 and the second hard mask 220. The lower electrode film 235 is made of polysilicon. The polysilicon is etched back to the bottom of the recess hole. The upper portion of the lower electrode film 235 is a space where the spacer is to be formed. As shown in FIG. 4, the height of the lower electrode film 235 is affected by the GIDL of the device. In the present invention, the lower electrode film 235 is formed to have a thickness of 500 ANGSTROM to 1000 ANGSTROM.

In particular, in order to form the lower electrode in the process of FIG. 21B, voids may be formed in the lower part of the recess, which is larger than the upper part. In order to solve this problem, a silicon layer having a high doping concentration is first formed, a silicon layer having a second low doping concentration is formed, a void formation is prevented, and heat treatment is performed to adjust the overall doping concentration.

Referring to FIGS. 22A, 22B and 22C, a bridge type spacer layer 240 is formed on the lower electrode 235 and planarized together with the second hard mask layer 220. Then, the semiconductor substrate 200 is formed with the gate dielectric layer 230 and the lower electrode 235 bridge spacer 240 stacked in the recess hole.

Referring to FIGS. 23A and 23B, the semiconductor substrate 200 is covered with the photoresist mask 250. In the present invention, the X axis is covered by the photoresist mask 250 and there is no change, and the photoresist mask 250 is opened only at the Y-axis active region and the inactive region boundary, and only a part of the upper portion of the device isolation film 215 is removed.

Referring to FIG. 23C, the photoresist mask 250 is formed to be opened only in the active region and the inactive region boundary. A connection hole 253 is formed using an open mask. The formed space is a space in which a septum electrode layer capable of matching the upper and lower electrode layers can be formed. After the formation of the connection hole 253, a heat treatment may be performed to heal the damaged gate dielectric film when necessary.

Referring to FIGS. 24A and 24B, an upper gate electrode layer 255 is formed on the bridge spacer 240. The upper gate electrode layer 255 is integrated with the lower electrode layer 230 through the connection hole 253 formed between the active region and the inactive region, not shown in the X-axis direction, as shown in the Y-axis diagram.

At this time, the bridge spacer 240 exists inside the upper gate electrode 255 while being audited (shaded), and is invisible in the X axis. And a gate dielectric layer 230 is formed between the sidewall drain in a subsequent process in the form of a bridge having only a side surface.

Although the upper portion of the electrode is shown as a single layer in the drawing, a metal silicide layer is formed on the upper portion in consideration of the resistance of the electrode.

Referring to FIG. 24C, an upper gate electrode layer 255 is formed on the connection hole 253 and the bridge spacer 240. Then, the lower electrode layer 230 and the upper gate electrode layer 255 are integrated to form a gate electrode. In addition, it is integrated with neighboring electrodes and can be used as a wally line (WL) when used in a memory device.

Unlike Embodiment 1, a gate dielectric film is not formed around the bridge spacer 240. This is because the gate dielectric film is formed not only before the formation of the connection hole but also before the bridge spacer formation.

25A, 25B and 25C, a low concentration impurity is formed on the substrate after forming the upper gate electrode 255, a spacer 260 is formed on the sidewall of the upper gate electrode 255, Concentration impurity is implanted into the source drain 265 to form the source drain 265.

The gate electrode transistor having the final completed bridge type internal spacer is in contact with the gate dielectric layer at the interface with the source drain 165 formed in the semiconductor substrate 200 to form a bridge The lower electrode 235 is formed in a space where the substrate is recessed. The entire electrode is integrated through the upper electrode 255 formed on the substrate and the connection hole, The bridge type spacer 240 is formed to securely block the drain leaky GIDL excited by the gate electrode.

The GIDL can be sufficiently suppressed due to the fact that the space inside the gate electrode is filled with the spacer existing only on the sidewall of the inner side of the conventional gate. Due to the strong characteristics of the gate, a transistor capable of operating the device can be formed can do.

Method of Forming a Memory Semiconductor Employing SRCAT with a Bridge Type Spacer in the Electrode Example 3

26 and 42 are cross-sectional views illustrating a method of forming a memory semiconductor DRAM employing SRCAT in which the bridge type spacer of the present invention is within the electrode.

Embodiment 3 of the present invention provides a method of forming a DRAM cell by forming a transistor realizing the concept of SRCAT in which the bridge type spacer of Embodiment 2 is located inside the electrode and forming a capacitor element in the formed SRCAT.

Each drawing is a cross-sectional view in which a surface represented by an X-direction (bit line BL) is cut off when SRCAT is formed. For the sake of convenience, the cross section of the SRCAT in the Y-axis direction appears as shown in the figure, so that each figure is constructed with the X side as the center, and only the Y side portion which is formed differently will be described.

26 is a diagram showing the layout of the DRAM of the present invention. The gate direction is B-B 'and the bit line direction is A-A' direction. In the drawings, a cross section is drawn on the basis of the cutting in the direction A-A ', and only the portions which are not shown in the A-A' portion and can not be explained are cut off in the B-B 'direction as necessary.

Referring to FIG. 27, an isolation layer 305 is formed on a semiconductor substrate 300, and a substrate is divided into an active region and an inactive region.

A shallow trench isolation (STI) process is used to form the device isolation film 305. The trench is formed by forming a slight thermal oxide film after the formation of the trench and forming a liner with a nitride film if necessary. Then, the trench is filled through the CVD or HDP process Planarize.

A buffer oxide film 310 is formed on the semiconductor substrate 300. The buffer oxide film 310 is formed by a thermal oxidation method and is formed to a thickness of about 50 to 150 ANGSTROM.

A hard mask film 315 is formed on the buffer oxide film 310. The hard mask layer 315 is formed of a material having a different etching rate from the semiconductor substrate 300 and the buffer oxide layer 310. For example, it can be used as a silicon nitride film.

Although not shown for convenience in the figure on the hard mask layer, a gate mask layer (not shown) is formed of a plurality of material layers. The lower layer was formed with a plasma CVD oxide film at a thickness of 2000 angstroms to 3000 angstroms thick and the intermediate layer was formed with an amorphous carbon layer (ACL) layer with 2000 angstroms to 3000 angstroms thick as an organic film, layer is formed to a thickness of about 500 angstroms. The gate mask layer is used as a mask pattern to form a predetermined pattern of the hard mask 315 layer.

Referring to FIG. 28, a first recessed hole is formed in the active region as a mask with a hard mask 315 layer. And a 200 Å thick nitride film layer is formed on the recessed hole by an etch stopping film (not shown). Thereafter, etchback process is performed to remove etch stopping film only on the side wall of the recessed hole and to remove the base portion.

The lower end of the recess hole is expanded by isotropic etching using the etch stopping layer (not shown) as a mask to form a recessed hole 320 having a larger space. After forming the enlarged recess hole 320, the etch stopping film is removed.

Then, the recess hole 320 is completed with the lower enlarged SRCAT recess hole 320 than the upper portion.

Referring to FIG. 29, a gate dielectric layer 325 is formed on the recess hole 320. The gate dielectric layer 325 forms a silicon oxide layer (SiO 2), a hafnium oxide layer (HFO 2), a tantalum oxide layer (TA 2 O 5), or an ONO (oxide / nitride / oxide) layer.

Referring to FIG. 30, a lower electrode film 330 is formed on the recess hole 320 and the hard mask 315. The lower electrode film 330 is made of polysilicon. The polysilicon is etched back to the bottom of the recess hole. As shown in FIG. 4, the spacer formation depth is a GIDL effect of the device, and the height of the lower electrode film 330 is well calculated and applied to the space above the lower electrode film 330. In the present invention, the lower electrode film 330 is formed to a thickness of 500 ANGSTROM to 1000 ANGSTROM.

In particular, voids may be formed inside the lower recessed hole, which is larger than the upper recessed hole. In order to solve this problem, a silicon layer having a high doping concentration is first formed, a silicon layer having a second low doping concentration is formed, a void formation is prevented, and heat treatment is performed to adjust the overall doping concentration.

Referring to FIG. 31, a bridge type spacer layer 340 is formed on the lower electrode 330 and planarized together with the hard mask layer 315. Then, the semiconductor substrate 300 is formed with a gate dielectric layer 325, a lower electrode 330, and a bridge spacer 340 stacked in the recess hole.

Referring to FIG. 32, there is no change in the direction A-A ', but a cross-section in the direction of the line B-B' after the step 31 although the change is only in the direction B-B '.

A photoresist mask (not shown) is formed open only at the active and inactive area boundaries. A connection hole 345 is formed using an open mask. The formed space is a space in which a nodal electrode layer, in which the upper electrode layer and the lower electrode layer can be matched with each other, is formed. After the formation of the connection hole 345, the mask may be removed and, if necessary, heat treatment may be performed to heal the damaged gate dielectric layer during etching.

Referring to FIG. 33A, an upper gate electrode layer 350 is formed on the bridge spacer 340. The upper gate electrode layer 350 is integrated with the lower electrode layer 330 through a connection hole 345 formed between the active region and the inactive region, not shown in the drawing but shown in the B-B 'direction.

At this time, the bridge spacer 340 is surrounded by the upper gate electrode 350 (shaded) and exists inside and is not seen in the A-A 'direction. And a gate dielectric layer 325 is formed between the sidewall drain in a later process in the form of a bridge on the side.

Although the upper portion of the electrode is shown as a single layer in the drawing, the metal silicide layer is formed on the upper portion in consideration of the resistance of the electrode.

And a layer of gate hard mask 355 is formed on the top gate. The gate hardmask layer 355 protects the gate electrode during subsequent processing.

Referring to FIG. 33B, this figure is a cross-sectional view taken along the line B-B 'in the process of FIG.

An upper electrode layer 350 is formed on the connection hole 345 and the bridge spacer 340. Then, the lower electrode layer 330 and the upper electrode layer 350 are integrated to form a gate electrode. In addition, it is integrated with neighboring electrodes and can be sufficiently used as a wedd line (WL).

34, a low concentration impurity is formed on the substrate after the formation of the upper gate electrode 350, a spacer 360 is formed on the sidewall of the upper gate electrode 350, and a high concentration impurity is removed using the sidewall spacer 360 as a mask Thereby forming the source drain 365.

A gate electrode transistor having a completed bridge type internal spacer is formed in the form of a bridge in contact with the gate dielectric film at the interface with the source drain 365 formed in the semiconductor substrate 300 therebetween, A lower electrode 330 is formed in a space where the substrate 300 is recessed and the entire electrode is integrated through the upper electrode 350 formed on the substrate 300 and the connection hole , The bridge type spacer 340 is formed inside the integrated electrode to reliably block the drain leakage (GIDL) excited at the gate electrode.

Referring to FIG. 35, a first interlayer insulating layer 370 is formed on the entire surface of the semiconductor substrate 300 while covering the gate hard mask electrode 355. The first interlayer insulating film 370 is formed of BPSG, PSG, PE-TEOS, or HDP-CVD oxide through a chemical vapor deposition process or a high density plasma process.

After forming the first interlayer insulating layer 370, a photoresist mask 375 is formed and the first interlayer insulating layer 370 is etched using the photoresist mask 375 as a mask to form a source drain impurity layer 365 are exposed. The contact holes are regions where a contact to be formed with the capacitor contact plug and a bit line plug connected to the bit line are to be formed.

Referring to FIG. 36, the photoresist mask 375 is removed and a side wall spacer 380 is formed on the side walls of the contact hole. The sidewall spacer 380 is a nitride film and is formed by an etchback process after formation of a film by CVD as in a conventional spacer forming process.

After forming the sidewall spacers 380, a contact plug 385 is formed in the con- tact hole. The contact plug 385 is a capacitor plug connected to a capacitor and a bit line plug connected to a bit line. The contact plug material may be formed of a polysilicon layer doped with a high concentration impurity, a metal, or a conductive metallic nitride.

Referring to FIG. 37, an etch stopping layer 390 and a second interlayer insulating layer 395 are formed on the contact plug 385 and the first interlayer insulating layer 370. The etch stopping film 390 is a silicon nitride film and proceeds to a CVD process. The second interlayer insulating film 395 is formed of BPSG, PSG, PE-TEOS, or HDP-CVD oxide by a chemical vapor deposition process or a high density plasma process.

A bit line contact mask (not shown) is formed on the second interlayer insulating film 395, and a bit line contact hole 400 connected to the bit line plug is formed.

Referring to FIG. 38, a bit line 405 is formed on the bit line contact hole 400 and the second interlayer insulating film 395.

After the bit line 405 is formed, a third interlayer insulating film 410 is formed on the bit line 405. The third interlayer insulating layer 410 is formed of BPSG, PSG, PE-TEOS, or HDP-CVD oxide by a chemical vapor deposition process or a high density plasma process.

A photoresist mask (not shown) is formed on the third interlayer insulating film 410 to form a hole through which the capacitor contact pad connected with the capacitor plug penetrates through the second interlayer insulating film 395 and the third interlayer insulating film 410 do.

After forming the capacitor contact pad hole, a capacitor contact pad 415 is formed. The capacitor contact pad 415 is formed of a polysilicon layer doped with a high concentration impurity.

Referring to FIG. 39, an etch stopping layer 420 is formed on the third interlayer insulating layer 410 and the capacitor contact pad 415. The etch stopping film 420 proceeds to a CVD process using a silicon nitride film. A first mold film 425 is formed on the etch stopping film 420. The first mold film 425 is typically formed at a value between 10000 and 20,000 ANGSTROM. The first mold film 425 is an oxide film and proceeds to a CVD process.

After the first mold film 425 is deposited, a mask layer 430 necessary for a photolithography process is formed.

Referring to FIG. 40, a capacitor lower electrode hole 435 is formed in contact with the upper portion of the capacitor contact pad 415 through a normal photolithography process. The first mold film 425 etch uses a dry etch and uses the etch stop film 420 as an etch end point.

After the etch stopping layer 420 on the capacitor contact pad 415 is removed, the mask layer is removed and a lower electrode layer 450 is formed in the capacitor lower electrode hole 435. As the material of the lower electrode layer 450, materials such as TiN, Ti, TaN, and Pt can be used. The lower electrode layer 450 should be in good contact with the capacitor contact pad 415 and the etch stopper layer 420 is sufficiently thick that the lower electrode layer 450 may fall or fall when the first mold film 425 is removed after the electrode is separated To support it.

Referring to FIG. 41, a first buried layer 445 is formed on the lower electrode layer 450. The first buried layer 445 is formed of TOZS having a good gap fill capability. Or a material having an etching rate different from that of the first mold film such as an organic material is used. In order to prevent the lower electrode from falling off during the process of removing the first mold film 445, it is preferable to reduce the defective device.

The first buried layer 445 is planarized through an etch-back process and the upper layer of the lower electrode 450 is removed to separate the electrodes. The electrode separation process proceeds with a wet etch back process.

The electrode material should be wet-etched slightly after the wet etching of the buried layer 445 so that the electrode tip is not sharpened when the electrode is separated. When the tip of the electrode is sharpened, the capacitor dielectric film formed later is broken and electrode leakage occurs.

Then, the first mold layer 425 and the first buried layer 445 are removed through a LAL lift-off process. Care must be taken to prevent adjacent electrodes from sticking together when removed.

In general, a structure is provided between the electrodes so that adjacent electrodes do not stick or collapse. It is possible to install a ladder-type structure or a structure that is not electrically connected even if a ring-shaped insulating film structure is installed.

Referring to FIG. 42, a zirconium oxide film used as a capacitor dielectric film 460 is formed on the lower electrode 450. The lower electrode 450 is formed by using Tetrakis-ethylmethylamino zirconium (Zr [N (C2H5) 2] 4 or less TEMAZ) as a precursor for forming a zirconium film in the atomic layer deposition chamber. Lt; / RTI > The precursor reacts and bonds with the lower electrode 450 with the atomic layer and supplies purge gas into the chamber to remove excess unreacted gaseous gas. Argon (Ar), helium (He), and nitrogen (N2) gases are used as the purge gas. When the unreacted precursor gas is removed, the chemisorbed precursor on the lower electrode 450 is thinned to the atomic layer level. In this precursor deposition process, the precursors are supplied at a low temperature of about 250 ° C, so even in a capacitor structure having a very high aspect ratio, the precursors are uniformly deposited in all parts such as inside and outside. In particular, the cylinder inlet is not clogged and the precursor is evenly distributed to the bottom of the cylinder, so that the step coverage problem does not occur.

The chamber is maintained at a high temperature of 275 DEG C, and an oxidizing agent is supplied, and the zirconium oxide film is formed by bonding with the precursor. O2, O3, H2O oxidizing agent is used as the oxidizing agent. In this embodiment, O3 having a relatively strong oxidizing power is used for forming a zirconium oxide film. Then, the carbon or nitrogen component in the precursor component is completely oxidized and removed, and a zirconium oxide film is formed. Purge gas is supplied to remove residual by-products. The basic cycle is repeated several times to obtain a zirconium oxide film having a desired thickness. In the present invention, it is preferable to repeat 100 times to 150 times, and the thickness is formed to a thickness of 100 ANGSTROM to 150 ANGSTROM.

Since the precursor is injected at a low temperature and the reaction gas is supplied at a high temperature to cause an oxidation reaction, a zirconium oxide film having excellent step coverage can be obtained even in a structure having a very high aspect ratio.

After formation of the zirconium oxide film, a zirconium oxide film (not shown) may be formed on the zirconium oxide film to form a zirconium oxide film-forming capacitor dielectric film 460.

The capacitor dielectric film 460 has been conveniently processed with a zirconium oxide film (ZrO 2) or a zirconium oxynitride film (ZrOCN) for explanation. However, another capacitor dielectric film may be used as the ZZ (ZrO 2 / Al 2 O 3 / ZrO 2) Al2O3 / TaO2), Hf2O3, or the like can be used.

At this time, if the precursor gas is supplied at a low temperature and the oxidizer gas is supplied at a high temperature to form a dielectric film, the process can be performed so that the capacitor dielectric film has excellent step coverage in a structure having a large aspect ratio.

An upper electrode 470 is formed on the capacitor dielectric film 460. As the material of the upper electrode 470, materials such as TiN, Ti, TaN, and Pt can be used.

Although not shown in the figures, if an interlayer insulating film is formed and metal wirings are formed, a capacitor dielectric film having excellent step coverage is formed on a capacitor having a large aspect ratio, and a capacitor having no leakage, Lt; RTI ID = 0.0 > DRAM < / RTI >

In particular, since the bridge-shaped insulating film has an internal spacer structure at both source and drain regions, the GIDL can basically control the refresh time of the blocking DRAM.

Example 4 using a DRAM in which a bridge type spacer is located inside the electrode.

Fig. 43 is a block diagram showing a system embodiment employing a DRAM having a bridge-type spacer in an electrode.

43, the memory 520 is a DRAM memory having a transistor connected to a central processing unit (CPU) 510 in the computer system 500 and having a spacer structure in the form of a bridge on the inner wall of the gate . Such a computer system may be a notebook PC used as a medium for using a DRAM memory, a desktop PC using a DRAM memory in general, or an electronic apparatus requiring a memory and equipped with a CPU. The digital product families in which the memory 520 is embedded and which store data and control the functions may also be the system 500. The memory 520 may be directly connected to the CPU and may be connected to the CPU through a bus or the like. FIG. 43 is an element that can basically be entered as all the electronic devices are digitized, although the respective elements are not shown sufficiently.

As described above, a DRAM using a transistor having a bridge type spacer structure inside a gate electrode does not cause a GIDL phenomenon, so that the leakage time can be reduced, the refresh time can be easily adjusted, and a highly integrated device can be easily produced.

By connecting the source drain bridge type spacer to the gate electrode, the GIDL problem can be solved and the word line structure can be increased by using the field region to reduce the current increase and the word line resistance to obtain excellent transistors.

In addition, a DRAM manufactured using the transistor having the structure described above can be applied to a system to realize a digital product having a very high performance.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that it is possible.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a semiconductor device having an RCAT structure made by a general technique. Fig.

2 shows a semiconductor device having a SRCAT structure made by a general technique.

Figure 3 is an RCAT structure made with conventional techniques.

FIG. 4 is a graph showing the relationship between the inner spacer depth and the GIDL when made with the general technique of FIG.

5 is a graph showing the relationship between the internal spacer thickness and the GIDL when made with the general technique of FIG.

6A and 17B are cross-sectional views illustrating a method of making an RCAT through an embodiment of the present invention.

18A and 25C are cross-sectional views illustrating a method of making RCAT, SRCAT made in another embodiment of the present invention.

Figures 26 and 42 are cross-sectional views illustrating a method of making a DRAM with a SRCAT made in yet another embodiment of the present invention.

Figure 43 is a system block diagram using memory made by the present invention.

Description of the Related Art

100, 200, 300: semiconductor substrate 105, 205, 310: pad oxide film

110, 120, 315: hard mask 155, 235, 255, 350: gate electrode

165, 165, 365: Source drain 138, 240, 340: Bridge spacer

370, 395, 410: interlayer insulating film 160, 260, 380: sidewall spacer

415: lower electrode contact plug 145, 253, 345: connection hole

450: lower electrode 460: capacitor dielectric film

470: upper electrode

520: memory 510: CPU

Claims (20)

Forming an active region and an inactive region to form a device isolation film on a semiconductor substrate; Forming a recessed hole in the active region; Removing the sacrificial film in the recessed hole; Forming a spacer insulating film layer on the sacrificial film layer and planarizing the spacer insulating film layer; Forming a connection hole in contact with the sacrificial layer by etching a part of the inactive region and the active region boundary; Removing the sacrificial layer by injecting an etching solution through the connection hole; Forming a gate electrode dielectric layer on the removed sacrificial film space and the semiconductor substrate; And And an electrode is formed on the gate dielectric film. delete delete delete Forming an active region and an inactive region to form a device isolation film on a semiconductor substrate; Forming a recessed hole in the active region; Forming a gate electrode dielectric layer on the recessed hole; Forming a lower electrode layer on the gate dielectric layer; Forming a spacer insulating film layer on the lower electrode layer and planarizing the spacer insulating film layer; Etching a portion of the inactive region and the active region boundary to form a connection hole to be connected to the lower electrode layer; Forming a gate electrode layer integrated with the lower electrode layer through the connection hole; Forming a bit line by forming a first interlayer insulating film on the gate electrode; Forming a capacitor plug and a capacitor contact pad to form a second interlayer insulating film on the first interlayer insulating film; And Wherein a capacitor layer is formed on the capacitor contact pad, and then a capacitor is formed. delete delete An active region and an inactive region separated by a device isolation film formed on a semiconductor substrate; A recessed hole formed in the active region; A gate dielectric film formed on the recessed hole; An electrode lower layer formed on the gate dielectric film; A first spacer layer formed on the lower electrode layer and connected to the source drain in bridge form; A gate electrode upper structure formed on the first spacer layer and integrally formed with the lower portion of the electrode through a part of the inactive region; A second spacer formed on a side wall of the electrode upper structure, and a source drain impurity layer on a semiconductor substrate formed on the second spacer. 9. The semiconductor device according to claim 8, wherein the lower portion of the electrode and the upper portion of the electrode surround the bridge-shaped first spacer. 9. The semiconductor device according to claim 8, wherein the first spacer formed in the recess hole has a lower surface deeper than the source drain, and the upper surface is parallel to at least the substrate. delete 9. The semiconductor device according to claim 8, wherein the first space layer formed in the recess hole is formed of a silicon nitride film. An active region and an inactive region separated by a device isolation film formed on a semiconductor substrate; A recessed hole formed in the active region; A gate dielectric film formed on the recessed hole; A lower electrode formed on the gate dielectric film and below the recessed hole; A first spacer formed on the lower electrode and connected to the inside of the recess hole in a bridge form; An upper electrode formed on the first spacer and forming a gate electrode integrally with the lower electrode through a part of the inactive region; A second spacer formed on the sidewall of the upper electrode, and a source drain impurity layer on the semiconductor substrate formed on the second spacer; A bit line formed in an interlayer insulating film formed on the upper electrode; A capacitor plug and a capacitor contact pad formed in the interlayer insulating film; A capacitor lower electrode formed on the capacitor contact pad; A capacitor dielectric film formed on the capacitor lower electrode; And Wherein a capacitor upper electrode is formed on the capacitor dielectric film. 14. The semiconductor device of claim 13 wherein the bottom of the recessed hole has a hemispherical surface with a surface area greater than the top surface of the recessed hole. 14. The semiconductor device according to claim 13, wherein the first spacer is surrounded by the gate electrode between the upper electrode and the lower electrode. 14. The semiconductor device according to claim 13, wherein the first spacer is deeply deeper than the source drain impurity layer and has a height higher than that of the semiconductor substrate, and both the substrate with the gate dielectric film and the substrate with the small- Device. delete delete delete delete

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