KR101384334B1 - Apparatus for synchronization of data and clock in memory tester - Google Patents

Abstract

Data and clock synchronizers in memory testers that delay the phase of incoming data to a position where a setup / hold time is assured so that data is always latched at the correct position. Is disclosed.
In the disclosed memory tester, a data and clock synchronization apparatus includes: a host terminal for outputting a command and pattern data for testing a memory, and a pattern generation board for testing the memory according to a control command of the host terminal; A memory tester comprising a communication controller that controls communication between a host terminal and a pattern generation board (PGB), wherein the pattern generation board converts serial data output from the communication controller into parallel data to an algorithm pattern generator (ALPG). A serial input processor and an input data protocol converter to transmit the serial input processor to receive specific pattern data repeated in serial communication, and measure a phase of a current clock and data, and use the measured phase value. Therefore, the phase of the input data is delayed to a position where the set-up / hold time is guaranteed to synchronize the data with the clock.

Description

Apparatus for synchronization of data and clock in memory tester}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data and clock synchronization device in a memory tester. More particularly, the present invention relates to a setup / hold time of a phase of input data. It relates to a data and clock synchronizer in a memory tester that delays to a guaranteed position so that the data is always latched in the correct serial (serializer & de-serializer).

Generally, a memory is a general term used for temporarily or permanently storing data or commands used in a computer, a communication system, an image processing system, etc. Typically, the memory is a semiconductor, a tape, a disk, an optical system, Most of the memory is occupied. There are various types of semiconductor memories such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Flash memory, and ROM (Read Only Memory) classified according to the electrical characteristics of the data storage method. Is the largest.

When such memory is mass-produced, it is shipped through a test process. The memory tester is used to check whether the mass-produced IC memory is normally operated. The process is automated and the result is processed by the built-in computer.

A conventional memory tester is shown in Fig.

The conventional memory tester illustrated in FIG. 1 includes a host terminal 110, a communication controller 120, a pattern generation board (PGB) unit 130, and a memory unit 140 as a test target.

The host terminal 110 serves to receive a test condition for a memory test from a user.

The communication controller 120 provides a specific communication method to communicate between one host terminal 110 and a plurality of pattern generation boards (PGB) 131 to 130 + N in the pattern generation board unit 130. Play a role.

Since the configuration and operation of the plurality of pattern generation boards 131 to 130 + N are the same, only one pattern generation board 131 will be described below for convenience of description.

The pattern generation board 131 is a communication interface 131a in charge of communication between the communication controller 120 and the algorithm pattern generator (ALPG) 131b, and generates a pattern for a memory test to test the memory 141. Algorithm pattern generator 131b.

The conventional memory tester configured as described above includes a plurality of pattern generation boards for testing a plurality of memories.

The conventional memory tester configured as described above sets the ALPG 131b register and the like through the communication controller 120 and the communication interface 131a in order to test the memories in the host terminal 110, and sets the pattern data inside the ALPG 131b. Transfer it to the pattern memory in.

The pattern data thus transmitted is transmitted to the ALPG 131b through the communication interface 131a. For this purpose, the communication interface 131a uses a specific communication scheme. For example, the connection line between the communication controller 120 and the communication interface 131a is configured by selecting one of the parallel communication method and the serial communication method. When exchanging data, a protocol in which information such as ID (ALPG identification) and error detection code (CRC) of the pattern generation board 131 is added to the data is used.

In this case, when the parallel communication method is used between the communication controller 120 and the communication interface 131a, a plurality of data lines can be transmitted at one time as compared to the serial communication method, so that a large amount of data can be sent at the same frequency and the same amount of data can be transmitted. When sending and receiving, it is possible to send data at a lower frequency than the serial communication method, which has the advantage of good stability. However, since communication lines must be connected between one communication controller and a plurality of pattern generation boards, the number of communication lines increases, and signal delay times between communication lines do not coincide.

In addition, when the serial communication method is used between the communication controller 120 and the communication interface 131a, the number of communication lines can be reduced between the communication controller and the plurality of pattern generation boards compared to the parallel communication method, thereby connecting a large number of pattern generation boards. It is possible to do And even at high frequencies, there is only one communication line, so there is no need to match the delay time. However, in order to transmit and receive a lot of data, high frequency must be used, and therefore, a problem of SI (Singnal Integrity) and PI (Power Integrity) must be solved on a PCB.

Therefore, in consideration of these various advantages and disadvantages, it is preferable to set a communication method between the communication controller 120 and the communication interface 131a.

The conventional memory tester disclosed in FIG. 1 assumes that the communication method between the communication controller and the communication interface is a serial communication method.

When the communication method between the communication controller and the communication interface is a serial communication method, the configuration of the communication interface 131a is shown in FIG.

As shown in FIG. 2, the communication interface 131a is a serial input processing unit 201 for converting serial input data generated by the communication controller 120 into parallel data, and in order to deliver necessary data to the ALPG 131b at a later stage. An input data protocol converter 202 for extracting data from a specified protocol, an output data protocol converter 203 for adding specific protocol data from data output from the ALPG 131b, and an output from the output data protocol converter 203 It consists of a serial output processing unit 204 for transmitting the parallel data to which the protocol is added to the host terminal 110 in the form of serial data.

Referring to the operation of the communication interface 131a configured as described above, when the data is transmitted from the host terminal 110 to the ALPG 131b, the data to be transmitted is input to the serial input processor 201 through the communication controller 120. After converting the serial data RX_DATA_SER to the parallel data RX_DATA_PAR in the serial input processing unit 201, the serial input processor 201 transfers the data to the input data protocol converter 202 and uses the specific protocol in the input data protocol converter 202. Only the necessary data portion is extracted and delivered to the ALPG 131b as parallel output data.

After the transmission of all data for the memory test through this process, the host terminal 110 transmits a test start command through the communication controller 120 and the communication interface 131a, and according to the test start command, the ALPG 131b. ) Automatically test the memory and the result is stored in the internal failure memory, and when the test is finished, read the failure memo from the host terminal 110 to analyze the result and pass / fail, etc. Decide

When the host terminal 110 reads data from the ALPG 131b, the output data of the ALPG 131b is input to the output data protocol converter 203, and specific protocol data is added by the output data protocol converter 203. One signal TX_DATA_PAR is generated and transmitted to the serial output processor 204. The serial output processor 204 converts the input parallel data TX_DATA_PAR into serial data TX_DATA_SER and transfers the serial data TX_DATA_PAR to the host terminal 110 through the communication controller 120.

An example of a specific communication protocol is shown in FIG. In general, a preamble signal is continuously output, and information (INFORMATION) data is output or input when the data is written or read by the host terminal 110. After the necessary information data is finished, the usual preamble signal is outputted continuously. For example, A5 is repeated as a hexa value of 8 bits in the preamble data value. The hexa A5 value, which is the data value of the preamble signal, is used as COMMA data to align the byte.

However, in the conventional art, when the data is latched to the clock in serial communication using SERDES, when the input data is out of phase with the clock, the data is accurately corrected due to the margin of the set-up time. There was a problem that could not be tested because it was not latched.

For example, there is no synchronization function to match the phase of the input data and the clock, which causes a problem in that the memory cannot be accurately tested when the input data and the clock do not coincide with each other.

Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art,

The problem to be solved by the present invention is to delay the phase of the input data to a position where the setup / hold time is assured so that the data is always latched at the correct position. The memory tester provides a data and clock synchronizer.

Another problem to be solved by the present invention is to measure the phase of the current clock and the data using the input delay by receiving the specific pattern data repeated in serial communication, and the phase of the input data using the measured value This is to provide a data and clock synchronizer in a memory tester that delays the set-up / hold time to a guaranteed position so that data is always latched correctly in the suspend.

Data and clock synchronization apparatus in the memory tester according to the present invention for solving the above problems,

A host terminal for outputting command and pattern data for testing the memory, and a pattern generation board for testing the memory according to a control command of the host terminal; In the memory tester comprising a communication controller for controlling the communication between the host terminal and the pattern generation board (PGB),

The pattern generation board,

A serial input processing unit converting serial data output from the communication controller into parallel data and transferring the serial data to an algorithm pattern generator (ALPG),

The serial input processing unit,

Receive specific pattern data repeated in serial communication and measure the phase of the current clock and data, and delay the phase of the input data to the position where the set-up / hold time is guaranteed by using the measured phase value. It is characterized by synchronizing data and clock.

The serial input processing unit,

An input delayer for delaying serial data for a memory test output from the communication controller to a delay value;

SERDES converting serial data input from the input delay unit into parallel data according to a bit sleep signal;

A byte aligner which decodes an input preamble signal value and generates a bit sleep signal to the sudes to control byte alignment;

And a delay calculator for measuring a phase of the serial data and an input clock, calculating a delay value for delaying input data using the measured phase value, and transmitting the delay value to the input delay unit.

In the above, the delay calculator,

Calculate a delay value until the output of the sudes changes from a current value to another value, and calculate a difference between the calculated delay value and an initially set delay value to calculate a delay value for delaying input serial data Characterized in that.

In the above, the delay calculator,

With the delay value initialized to "0", the transition is made to the first state at the next clock to increase the delay value to "1" (idelay_val = idelay_val + 1) and then to the second state at the next clock. Transition to and compare the output parallel data of the sudes with the output parallel data of the previously stored data, and if the same is the same, move to the first state and output the delay value increased by "1". .

In the above, the delay calculator,

Transitioning to the second state is performed by comparing the output parallel data of the sudes with the output parallel data of the previously stored data, and if it is not the same, it is determined that an inflection occurs in the input serial data, and the transition to the third state. By calculating the delay value by calculating based on the current delay value.

The delay value calculation,

When the current delay value is greater than or equal to the half period (UI / 2) of the input clock, the half period is subtracted from the increased delay value, and the result value is output as a delay value.

The delay value calculation,

When the current delay value is smaller than the half period of the input clock, the half period is added to the increased delay value and the result value is output as a delay value.

According to the present invention, the phase of the input data is delayed to a position where a setup / hold time is guaranteed, so that serial data can always be latched at a precisely sustained position. There is this.

1 is a block diagram of a memory tester to which the conventional and the present invention is applied,
2 is a configuration diagram of an embodiment of a conventional communication interface,
3 is an exemplary diagram of a conventional communication protocol,
4 is a block diagram of an embodiment of a serial input processor of a data and clock synchronization device in a memory tester according to the present invention;
5 is a state transition diagram for calculating a delay value of the delay calculator in the present invention,
6 to 8 are timing diagrams for calculating a delay value in the delay value calculator of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

The memory tester to which the present invention is applied is the same as that of the conventional memory tester of FIG. 1, the control command of the host terminal 110 and the host terminal 110 for outputting a command and pattern data for testing the memory 141. A pattern generating board 131 for testing the memory 141 according to the present invention; The communication controller 120 controls communication between the host terminal 110 and the pattern generation board (PGB) 131.

As shown in FIG. 2, the pattern generation board 131 converts serial data output from the communication controller 120 into parallel data and transmits the serial data to an algorithm pattern generator (ALPG) 131b. And an input data protocol converter 202.

In the communication interface configured as described above, the present invention configures the serial input processing unit as shown in FIG. 4 so that the data is always latched correctly in SERDES.

Preferably, the serial input processing unit 201 receives specific pattern data (for example, a preamble hexa A5 signal) repeated in serial communication, and measures the phase of the current clock RX_CLK and data RX_DATA_SER. Using the measured phase value, the phase of the input data is delayed to a position where the set-up / hold time is guaranteed, thereby synchronizing the data and the clock.

More preferably, the serial input processor 201 may further include an input delayer configured to delay serial data RX_DATA_SER for a memory test output from the communication controller 120 to a delay value (valid_val). 301); A SERDES 302 for converting serial data output from the input delay unit 301 into parallel data RX_DATA_PAR according to a bit sleep (BIT_SLIP) signal; A byte aligner 303 for decoding an input preamble signal value (hexa A5 signal) and generating a bit sleep (BIT_SLIP) signal to the sudes 302 to control byte alignment; And a delay value calculator 304 for measuring a phase of the serial data and an input clock, calculating a delay value for delaying input data using the measured phase value, and transmitting the delay value to the input delay unit 301.

In the memory tester data and the clock synchronizing apparatus configured as described above, the data output from the host terminal 110 is transmitted to the communication interface 131a of the pattern generation board 131 through the communication controller 120.

The serial input processing unit 201 of the communication interface 131a converts the input serial data into parallel data and delivers the data to the input data protocol converter 202. Only the data necessary by the protocol is extracted and delivered to the ALPG 131b at a later stage.

In the present invention, the waveform of the input data RX_DATA_SER and the input clock RX_CLK in the serial input processing unit 201 causes the input clock RX_CLK to be in the middle of the input data RX_DATA_SER as shown in FIG. Ensure that the setup and hold times of the input clocks for the data are the same. That is, if the input clock period is a UI, the input serial data is delayed using the input delay unit 301 so that the setup time and the hold time are each half period (UI / 2).

More specifically, the input delay unit 301 delays the input serial data RX_DATA_SER in time according to a delay value (idelay_val) as needed, and the sudes 302 is a byte sorter 303. 1-bit serial data is converted into n-bit parallel data (RX_DATA_PAR) by using the bit slip (BIT_SLIP) generated from the N-bit data and output to the input data protocol converter 202.

Here, the byte aligner 303 decodes the hexa A5, which is a preamble signal value, and performs byte alignment to collect eight 1-bit data into one-byte parallel data. For example, bit suspend to sudes 302 until byte data of hexa A5 is output.

The delay calculator 304 measures how much phase the input serial data (RX_DATA_SER) and the input clock (RX_CLK) are in phase, and continuously delays the input serial data with the delay value so that the output of the sused 302 is Delay value from the value to the point of change to another value is detected and the difference with the initial delay value is calculated, and the delay value is provided to the input delay unit 301 by using the result value to delay the input serial data.

The process of calculating the delay value in the delay value calculator 304 is shown in FIG.

When the memory tester is powered up and testing begins, the state machine is ST0, which initializes the delay value (idelay_val) to "0". The state machine then transitions to the first state ST1 at the next clock to increase the delay value by " 1 " (idelay_val = idelay_val + 1). Thereafter, a transition is made to the second state ST2 at the next clock, and the output parallel data data_par of the death is compared with the output parallel data data_par_pre of the previously stored data. In step ST1), the delay value idelay_val1 increased by " 1 " is output to the input delayer 301. That is, the input delayer 301 is set to a value that is increased by 1 from the previous value (the currently set delay value), thereby delaying the input data by a value in which the delay time of one unit is increased.

In addition, the delay calculator 304 makes a transition to the second state ST3 and compares the output parallel data data_par of the death with the output parallel data data_par_pre of the previously stored data. If the output parallel data (data_par) of the sudes is different from the output parallel data (data_par_pre) of the previously stored data, the inflection occurs in the input serial data. After the determination, the transition to the third state ST3 is performed to calculate the delay value based on the current delay value (valid_val).

That is, as shown in FIG. 7, when the current delay value (idelay_val) is greater than or equal to the half period (UI / 2) of the input clock (RX_CLK) (idelay_val ≥ UI / 2), the delay value (idelay_val1) increased by one. The half cycle UI / 2 is subtracted (idelay_val1-UI / 2), and the result is transmitted to the input delayer 301 as a delay value. In FIG. 7, RX_DATA means serial data to be input, RX_DATA_T means serial data delayed by an increased delay value, RX_DATA_C means serial data delayed by a currently set delay value, and RX_CLK means an input clock.

In addition, as shown in FIG. 8, when the current delay value (idelay_val) is smaller than the half period (UI / 2) of the input clock (RX_CLK) (idelay_val <UI / 2), the delay value (idelay_val1) is increased. The half period (UI / 2) is added ((idelay_val1 + UI / 2), and the result value is transmitted to the input delay unit 301 as a delay value. In FIG. 8, RX_DATA means serial data to be input, and RX_DATA_T is increased by one. Means serial data delayed by the delayed value, RX_DATA_C means serial data delayed by the currently set delay value, RX_CLK means the input clock.

When the delay value calculated in the third state ST3 is set in the input delay unit 301 as described above, the setup time and the hold time become UI / 2 as shown in FIG. 6, so that the serial data RX_DATA_SER is stably. Latched at 302, it is possible to accurately convert serial data into parallel data.

The converted parallel data is transferred to the input data protocol converter 202, and the input data protocol converter 202 extracts only the necessary data portion using a specific protocol and delivers the data to the ALPG 131b as parallel output data.

After the transmission of all data for the memory test through this process, when the host terminal 110 transmits a test start command through the communication controller 120 and the communication interface 131a, the ALPG 131b automatically tests the memory. The result is stored in the internal failure memory, and when the test is completed, the host terminal 110 reads the failure memory, analyzes the result, and determines a pass / fail.

When the host terminal 110 reads data from the ALPG 131b, the output data of the ALPG 131b is input to the output data protocol converter 203, and specific protocol data is added by the output data protocol converter 203. One signal TX_DATA_PAR is generated and transmitted to the serial output processor 204. The serial output processor 204 converts the input parallel data TX_DATA_PAR into serial data TX_DATA_SER and transfers the serial data TX_DATA_PAR to the host terminal 110 through the communication controller 120.

Therefore, the user can easily check the memory test result through the host terminal 110.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims and their equivalents. Of course, such modifications are within the scope of the claims.

110 ... Host terminal
120 ... Communication controller
130 ... Pattern Generation Board
131 ... Pattern generation board
131a... Communication interface
131b... ALPG
201 ... Serial input processor
202 ... Input Data Protocol Converter
301 ... Input delayer
302... Sudes
303 ... Byte sorter
304... Delay value calculator

Claims (7)

A host terminal for outputting command and pattern data for testing the memory, and a pattern generation board for testing the memory according to a control command of the host terminal; In the memory tester comprising a communication controller for controlling the communication between the host terminal and the pattern generation board (PGB),
The pattern generation board,
A serial input processing unit converting serial data output from the communication controller into parallel data and transferring the serial data to an algorithm pattern generator (ALPG),
The serial input processing unit,
An input delayer for delaying serial data for a memory test output from the communication controller to a delay value;
SERDES converting serial data input from the input delay unit into parallel data according to a bit sleep signal;
A byte aligner which decodes an input preamble signal value and generates a bit sleep signal to the sudes to control byte alignment;
And a delay calculator for measuring a phase of the serial data and an input clock, calculating a delay value for delaying input data using the measured phase value, and transmitting the delay value to the input delay unit. And clock synchronizer.
delete The method of claim 1, wherein the delay calculator,
Calculate a delay value until the output of the sudes changes from a current value to another value, and calculate a difference between the calculated delay value and an initially set delay value to calculate a delay value for delaying input serial data And a data and clock synchronizer in a memory tester.
The method of claim 3, wherein the delay calculator,
With the delay value initialized to "0", the transition is made to the first state at the next clock to increase the delay value to "1" (idelay_val = idelay_val + 1) and then to the second state at the next clock. By comparing the output parallel data of the sudes with the output parallel data of the susdes previously stored, and shifting to the first state to output the delay value increased by " 1 " Data and clock synchronizer in memory tester.
The method of claim 4, wherein the delay calculator,
Transitioning to the second state is performed by comparing the output parallel data of the sudes with the output parallel data of the previously stored data, and if it is not the same, it is determined that an inflection occurs in the input serial data, and the transition to the third state. And calculating the delay value based on the current delay value.
The method of claim 5, wherein the delay value calculation,
If the current delay value is greater than or equal to the half period (UI / 2) of the input clock, subtract the half period from the increased delay value and output the result as a delay value. .
The method of claim 5, wherein the delay value calculation,
And if the current delay value is less than a half period of the input clock, add the half period from the increased delay value and output the result as a delay value.

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