KR101363422B1 - Non-volatile memory system - Google Patents

Abstract

A non-volatile memory system comprises: a host device which provides copy-back commands in a queuing form to perform a copy-back operation and a copy-back processing rate command indicating a processing rate of the copy-back operation and a write operation; and an NAND flash memory device which performs the copy-back operation based on the copy-back commands wherein the copy-back operation and the write operation are performed in alternation according to the processing rate of the copy-back operation and the write operation. Thus, the non-volatile memory system can improve the operating speed, reduce power consumption, and increase service life of the NAND flash memory device.

Description

Nonvolatile Memory System {NON-VOLATILE MEMORY SYSTEM}

The present invention relates to a semiconductor memory system, and more particularly, to a nonvolatile memory system having at least one NAND flash memory device.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device according to whether data can be stored in a state where power is not supplied. 2. Description of the Related Art In recent years, NAND flash memory devices have been widely used in nonvolatile memory devices because of miniaturization and large capacity of semiconductor memory devices. In general, a NAND flash memory device may perform a read operation and a write operation in units of pages and an erase operation in units of blocks.

The nonvolatile memory system may include a host device and at least one NAND flash memory device. When the host device uses the NAND flash memory device, a copyback operation of moving the target page data stored in the source page to the target page may be involved. For example, a copyback operation is accompanied when a journaling operation is performed on a journaling file system or when a garbage collection operation is performed on a log-structured file system. Can be.

However, conventionally, when the copyback operation is performed, since the target page data is transferred between the host device and the NAND flash memory device through the host interface, the available bandwidth of the host interface is unnecessarily reduced. In particular, since the target page data stored in the source page is already stored in the NAND flash memory device, and no separate data transfer is required, the reduction of the available bandwidth of the host interface by the copyback operation does not require the performance of the nonvolatile memory system. It is a factor to lower it.

An object of the present invention is to provide copyback commands for a host device to perform a copyback operation (ie, including information about a source page address and a target page address) to a NAND flash memory device. In addition to providing in the form of queuing, the processing rate of the copyback operation and the write operation can be determined, and the NAND flash memory device can be internally operated according to the processing rate of the copyback operation and the write operation. To provide a non-volatile memory system to perform alternately. It should be understood, however, that the present invention is not limited to the above-described embodiments, but may be variously modified without departing from the spirit and scope of the invention.

In order to achieve the object of the present invention, a nonvolatile memory system according to embodiments of the present invention provides copyback commands for performing a copyback operation in the form of a queuing, and the copyback operation And a host device for providing a copyback processing rate command indicating a processing rate of a write operation, and performing the copyback operation based on the copyback commands, and performing the copyback operation and the write operation according to the processing rate. It may include a NAND flash memory device to perform alternately.

According to an embodiment, when the processing ratio is m: n (where m and n are positive integers), the n-page data data before and after the copyback operation on m-page data is performed. Write operations may be performed alternately.

According to an embodiment, when the processing ratio is m: n (where m and n are positive integers), the n-page data for n page data is performed between m copy data operations. Write operations may be performed alternately.

According to an embodiment, the copyback operation may be accompanied by a garbage collection operation or a journaling operation.

In an embodiment, the NAND flash memory device includes a first flash translation layer that performs the copyback operation, and the host device interacts with a file system and the file system. and a second flash conversion layer controlling the operation of the NAND flash memory device.

According to an embodiment, the NAND flash memory device may not perform the copyback operation when a copyback cancel command is input from the host device while the copyback operation and the write operation are alternately performed.

In example embodiments, when a copyback completion command is input from the host device while the copyback operation and the write operation are alternately performed, the NAND flash memory device may preferentially perform the copyback operation. Can be.

A nonvolatile memory system according to embodiments of the present invention provides a host device with copyback commands for performing a copyback operation (ie, including information about a source page address and a target page address) to a NAND flash memory device. In addition to providing in the form of queuing, the processing rate of the copyback operation and the write operation can be determined, and the NAND flash memory device can alternately copy and write the operation according to the processing rate of the copyback operation and the write operation. By doing so, the overhead between the host device and the NAND flash memory device may be reduced by performing the copyback operation. As a result, the nonvolatile memory system can improve operating speed (ie, performance), reduce power consumption, and increase the lifetime of the NAND flash memory device. However, the effects of the present invention are not limited thereto, and various modifications may be made without departing from the spirit and scope of the present invention.

Figures 1A-1C are block diagrams illustrating a non-volatile memory system in accordance with embodiments of the present invention.
2A through 2E are diagrams illustrating an example in which a non-volatile memory system alternately performs a copyback operation and a write operation according to embodiments of the present invention.
3A is a graph illustrating a response time for a write command in a conventional nonvolatile memory system.
3B is a graph illustrating a response time for a write command in a nonvolatile memory system according to example embodiments.
4 is a flowchart illustrating an example in which a copyback operation and a write operation are alternately performed in a nonvolatile memory system according to example embodiments.
FIG. 5 is a conceptual diagram illustrating an example in which a copyback operation and a write operation are alternately performed in a nonvolatile memory system according to example embodiments.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

Figures 1A-1C are block diagrams illustrating a non-volatile memory system in accordance with embodiments of the present invention. However, the non-volatile memory system 100 of FIG. 1A will be described for convenience of explanation.

Referring to FIG. 1A, the nonvolatile memory system 100 may include a NAND flash memory device 120 and a host device 140. In this case, the NAND flash memory device 120 may include a solid state drive (SSD), a secure digital card (SDCARD), a universal flash storage (UFS), and an embedded multimedia card (Embedded Multi). Media Card (EMMC), a compact flash card (CF), a memory stick (memory stick), an XD picture card (XD picture card) and the like. As shown in FIG. 1A, the nonvolatile memory system 100 includes a first flash translation layer 122 and a second flash translation layer (FTL) for controlling an operation of the NAND flash memory device 120. The flash conversion layer 142 may be separated, and the first flash conversion layer 122 may be provided in the NAND flash memory device 120, and the second flash conversion layer 142 may be provided in the host device 140. In the present invention, the first flash conversion layer 122 and the second flash conversion layer 142 are referred to as a first flash conversion layer 122 and a second flash conversion layer 142. However, the first flash conversion layer 122 and the second flash conversion layer 142 include at least one function of the flash conversion layer for controlling the operation of the NAND flash memory device 120 Which will be interpreted as various components.

In general, when the NAND flash memory device 120 is used by the host device 140 in the nonvolatile memory system 100, a copyback operation of moving the target page data stored in the source page to the target page may be involved. For example, the copyback operation may be accompanied when a journaling operation is performed in a journaling file system or when a garbage collection operation is performed in a log system file system. However, in the conventional copyback operation, target page data is brought to the host device 140 by a copyback read operation, and then target page data is transferred to the NAND flash memory device 120 by a copyback write operation. Because of the need to send, the available bandwidth of the host interface between the host device 140 and the NAND flash memory device 120 is reduced, thereby degrading the performance of the nonvolatile memory system 100. Accordingly, the nonvolatile memory system 100 includes a first flash conversion layer 122 that performs a copyback operation on the NAND flash memory device 120, and the NAND flash memory device 120 is connected to the host device 140. And a second flash translation layer 142 for controlling the operation, and transmits the copyback commands (QCBCs) to the NAND flash memory device 120 in the form of queuing at the same time. By determining the processing rate of the operation (ie, queuing / throttling copyback protocol interface), the copyback operation is performed by the host device 140 and the NAND flash memory device 120. It is possible to perform only the inside of the NAND flash memory device 120 without transferring data therebetween, and the copyback operation and the write operation may be alternately performed efficiently. As a result, in the nonvolatile memory system 100, target page data may not be transmitted between the host device 140 and the NAND flash memory device 120 during a copyback operation. Hereinafter, the nonvolatile memory system 100 will be described in detail with reference to FIGS. 1A to 1C.

The host device 140 provides the copyback commands QCBC for performing the copyback operation to the NAND flash memory device 120 in the form of a queuing, and indicates a processing rate of the copyback operation and the write operation. The PR may be provided to the NAND flash memory device 120. In some embodiments, the copyback command QCBC may include only information about the source page address and the target page address. The NAND flash memory device 120 performs a copyback operation based on the copyback commands QCBC input from the host device 140, but the copyback operation and the write operation according to the processing rates of the copyback operation and the write operation. Can be done alternately. In this case, when the host device 140 provides the write command WC corresponding to the write request signal to the NAND flash memory device 120, the NAND flash memory device 120 writes based on the write command WC. Can be performed. In detail, the copyback commands QCBC may include information about a source page address and a target page address, respectively, and the copyback commands QCBC are provided in a queuing form. Can be stored in the form of a cue. In this case, the predetermined buffer located in the NAND flash memory device 120 may be a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, or the like, but is not limited thereto. As a result, the NAND flash memory device 120 may process the copyback commands QCBCs according to the queuing order and based on the information about the source page address and the target page address included in each of the copyback commands QCBC. The target page data stored in the source page can be moved to the target page. In this case, the copyback operation may be performed based on a logical level, that is, a logical address. For example, when the NAND flash memory device 120 performs a logical level copyback operation, the NAND flash memory device 120 transfers target page data stored in the source page to a predetermined buffer therein. After reading, the target page data may be written in the target page. In some embodiments, when the NAND flash memory device 120 supports a copy level command of a physical level, the copyback operation may be performed based on a copy level command of a physical level.

When a write operation and a copyback operation are performed in the NAND flash memory device 120, the NAND flash memory device 120 performs a copyback processing ratio command PR, that is, a copyback operation and a write input from the host device 140. The copyback operation and the write operation may be alternately performed according to the processing ratio of the operation. In one embodiment, if the processing ratio of the copyback operation and the write operation is m: n (where m and n are positive integers), a copyback operation is performed on m page data (ie, target page data). Before and after, write operations on n page data (ie, write page data) may be alternately performed. For example, when the processing ratio of the copyback operation and the write operation is 2: 1, the NAND flash memory device 120 performs a copy operation on two page data and then writes one page data. Alternatively, after performing a write operation on one page data, a copyback operation on two page data may be performed. In another embodiment, if the processing ratio of the copyback operation and the write operation is m: n (where m and n are positive integers), a copyback operation is performed on m page data (ie, target page data). In the meantime, write operations on n page data (ie, write page data) may be alternately performed. For example, when the processing ratio of the copyback operation and the write operation is 2: 1, the NAND flash memory device 120 performs a copyback operation on one page data and then writes one page data. In addition, a copyback operation may be performed on one page data again. As such, when the processing ratio of the copyback operation and the write operation is m: n, the NAND flash memory device 120 may interleave the copyback operation and the write operation at a ratio of m: n. However, although the write operation and the copyback operation are alternately performed in the NAND flash memory device 120, since the write operation and the copyback operation are alternated quickly, the NAND is externally used (for example, the host device 140). It can be seen that the write operation and the copyback operation are performed at the same time in the flash memory device 120.

In an embodiment, the NAND flash memory device 120 may not perform a copyback operation when a copyback cancel command is input from the host device 140 while alternately performing a copyback operation and a write operation. Specifically, when the host device 140 outputs a write command WC to the NAND flash memory device 120 to perform a write operation, when the write operation is required to be completed prior to the copyback operation, the NAND A copyback cancel command may be output to the flash memory device 120. In this case, when a copyback cancel command is input from the host device 140, the NAND flash memory device 120 ignores the preset processing ratios of the copyback operation and the write operation, and performs the write operation without performing the copyback operation. By performing only, the write operation can be completed preferentially. According to an embodiment, the NAND flash memory device 120 may delete all copyback commands QCBC stored in a predetermined buffer in response to a copyback cancel command. In another embodiment, when a copyback completion command is input from the host device 140 while the copyback operation and the write operation are alternately performed, the NAND flash memory device 120 preferentially performs a copyback operation to complete. Can be. Specifically, when the host device 140 outputs a write command WC to the NAND flash memory device 120 to perform a write operation, when the copyback operation is required to be completed prior to the write operation, the NAND A copyback completion command may be output to the flash memory device 120. In this case, when the copyback completion command is input from the host device 140, the NAND flash memory device 120 ignores the preset processing ratio of the copyback operation and the write operation, and writes until the copyback operation is completed. May not be performed.

Meanwhile, the copyback operation may be accompanied by a garbage collection operation or a journaling operation. In one embodiment, as shown in FIG. 1A, file system 144 may correspond to a file system such as an extended file system (Ext4), a new technology file system (NTFS), or the like. . Accordingly, the NAND flash memory device 120 may include a first flash conversion layer 122 that performs a copyback operation (eg, a garbage collection operation), and the host device 140 may include a file system 144. And a second flash conversion layer 142 that interacts with the file system 144 to control an operation of the NAND flash memory device 120. In another embodiment, as shown in FIG. 1B, the file system 244 provided in the host device 240 may correspond to a file system such as a log-structured file system (LFS). . Accordingly, the NAND flash memory device 220 may include a first flash conversion layer 222 that performs a copyback operation, and the host device 240 interacts with the file system 244 and the file system 244. And a second flash conversion layer 242 for controlling the operation of the NAND flash memory device 220. In another embodiment, as shown in FIG. 1C, the file system 344 included in the host device 340 is a flash file system different from the file systems 144 and 244. Can be configured. Accordingly, the NAND flash memory device 320 may include a first flash conversion layer 322 that performs a copyback operation, and the host device 300 may include a flash file system 344 and a second flash conversion layer 342. ) Can be performed.

As described above, the nonvolatile memory system 100 includes a first flash conversion layer 122 that performs a copyback operation (eg, a garbage collection operation) on the NAND flash memory device 120, and the host device. By providing a second flash conversion layer 142 at 140 to control the operation of the NAND flash memory device 120, the host device 140 can accurately grasp the internal operation information of the NAND flash memory device 120. The NAND flash memory device 120 may be efficiently controlled based on the NAND flash memory device 120. According to an embodiment, when the host device 140 is first connected to the NAND flash memory device 120, the host device 140 may output a device information request command to the NAND flash memory device 120. In this case, the host device 140 may obtain device information (eg, information about a block size, a page size, etc.) output from the NAND flash memory device 120. According to an embodiment, the host device 140 may output a copyback status request command to the NAND flash memory device 120. In this case, the host device 140 may obtain copyback status information (for example, the number of remaining copyback commands QCBC) output from the NAND flash memory device 120. However, the above-described commands are exemplary, and additional commands for sharing various information between the host device 140 and the NAND flash memory device 120 may be used.

As described above, the nonvolatile memory system 100 allows the host device 140 to provide copy back commands QCBC to the NAND flash memory device 120 in the form of a queue while performing a copy back operation. Determine the processing ratio of the operation and the write operation, and cause the NAND flash memory device 120 to perform the copyback operation and the write operation alternately according to the processing ratio of the copyback operation and the write operation, thereby making a copyback operation. As a result, overhead between the host device 140 and the NAND flash memory device 120 can be reduced. As a result, the nonvolatile memory system 100 may improve operating speed (ie, performance), reduce power consumption, and increase the lifespan of the NAND flash memory device 120. Meanwhile, although the host device 140 is illustrated as having only the second flash conversion layer 142 and the file system 144 in FIG. 1A, the host device 140 may include a central processing unit (CPU) and a cache. It is apparent that the device may further include hardware or software components such as a cache, an operating system (OS), and the like. Similarly, although the NAND flash memory device 120 includes only the first flash conversion layer 122 in FIG. 1A, the NAND flash memory device 120 may include a NAND controller and a microprocessor unit. It is apparent that the hardware may further include hardware or software components such as an MPU, a NAND flash manager, and the like.

2A through 2E are diagrams illustrating an example in which a non-volatile memory system alternately performs a copyback operation and a write operation according to embodiments of the present invention.

2A through 2E, an example in which a copyback operation and a write operation are alternately performed in the nonvolatile memory system 100 is illustrated in detail. For convenience of explanation, one block 131, 132, 133, and 134 is composed of four pages, and the processing ratio of the copyback operation and the writing operation corresponding to the copyback processing ratio command PR is 2: Assume it is two. At this time, the copyback commands QCBC for performing the copyback operation are provided to the NAND flash memory device 120 from the host device 140 in the form of queuing, and the write commands WC for performing the write operation are provided for the host. It is provided from the device 140 to the NAND flash memory device 120, and the processing rates of the copyback operation and the write operation are continuously changed according to the required conditions. For example, the processing rates of the copyback operation and the write operation may be changed each time the preset time elapses, or when the preset condition (for example, the response time is out of the preset range). It may be changed every time, or may be changed in response to an external input of a user. However, this is merely an example, and processing rates of the copyback operation and the write operation may be changed in various ways.

As described above, in the nonvolatile memory system 100, the host device 140 provides copyback commands QCBCs in a queuing form, and the NAND flash memory device 120 queues copyback commands QCBCs. After the data is stored in a predetermined buffer, the copyback commands QCBCs are processed in the queuing order. In this case, the copyback commands QCBC may correspond to a list of page data (ie, target page data) on which the copyback operation is to be performed. As shown in FIG. 2A, two valid page data V and two invalid page data I may exist in the first block 131, and two valid pages may also exist in the second block 132. There may be data V and two invalid page data I. Finally, the NAND flash memory device 120 performs two copy page operations (V) of the first block 131 and two of the second block 132 in the third block 133 by performing a copyback operation. Valid page data V may be written, and page data W input from the host device 140 may be written in the fourth block 134. At this time, since the processing ratio of the copyback operation and the write operation is 2: 2, the write operation on the two write page data W before and after the copyback operation on the two valid page data V is performed. This can be done alternately. For example, after a copyback operation on two valid page data Vs is performed, a write operation on two write page data Ws is performed. Alternatively, since the processing ratio of the copyback operation and the write operation is 2: 2, the write operation on the two write page data W is performed while the copyback operation on the two valid page data V is performed. Alternately it can be done. For example, after a copyback operation on one valid page data (V) is performed, a write operation on one write page data (W) is performed, and then again on one valid page data (V). After the copyback operation is performed, a write operation on one write page data W is performed again. However, in FIGS. 2A to 2E, after a copyback operation on two valid page data Vs is performed, a write operation on two write page data Ws is performed.

Specifically, as shown in FIG. 2B, the NAND flash memory device 120 reads two valid page data V of the first block 131, and then removes the valid page data V. FIG. It is possible to write (ie, denote as FOP) in three blocks 133. Thereafter, as illustrated in FIG. 2C, the NAND flash memory device 120 may write (ie, denote as SOP) two write page data W in the fourth block 134. Thereafter, as illustrated in FIG. 2D, the NAND flash memory device 120 reads the two valid page data V of the second block 132, and then reads the valid page data V in a third manner. It may be written to block 133 (ie, marked as TOP). Thereafter, as illustrated in FIG. 2E, the NAND flash memory device 120 may write (ie, mark FFOP) two write page data W in the fourth block 134. Next, the first and second blocks 131 and 132 may be erased to become empty blocks for a write operation or a copyback operation (eg, a garbage collection operation). As such, the nonvolatile memory system 100 includes a first flash conversion layer 122 that performs a copyback operation on the NAND flash memory device 120, and the NAND flash memory device 120 in the host device 140. And a second flash conversion layer 142 for controlling the operation of the memory device, and transmitting the copyback commands QCBC to the NAND flash memory device 120 in the form of queuing. By determining the processing ratio of the write operation, the copyback operation may be performed only inside the NAND flash memory device 120, and the copyback operation and the write operation may be alternately performed efficiently.

3A is a graph showing a response time for a write command in a conventional nonvolatile memory system, and FIG. 3B is a graph showing a response time for a write command in a nonvolatile memory system according to embodiments of the present invention.

Referring to FIGS. 3A and 3B, FIGS. 3A and 3B illustrate embodiments of the present invention in which a response time for a write command corresponding to a write request signal WRITE REQUEST is higher than that of a conventional nonvolatile memory system. It is shown that it is more stable in the nonvolatile memory system (100, 200, 300). In other words, as shown in FIG. 3A, in a conventional nonvolatile memory system, when a write operation is performed in response to a write command, a write operation and a copyback operation (eg, a garbage collection operation) are specified at specific time points. In this case, since a predetermined delay occurs due to the overhead between the host device and the NAND flash memory device in performing the copyback operation, the response time for the write request signal WRITE REQUEST at the specific time points may be increased. RESPONSE TIME will be longer. As a result, since the response time (RESPONSE TIME) to the write request signal WRITE REQUEST is unstable in the conventional nonvolatile memory system, the performance of the conventional nonvolatile memory system may be greatly degraded. On the other hand, as shown in Figure 3b, in the nonvolatile memory system (100, 200, 300) according to the embodiments of the present invention, in the write operation is performed in response to the write command, the copyback operation is NAND flash The response time for the write request signal (WRITE REQUEST) at all time points is performed only in the memory device, and the copyback operation and the write operation are efficiently performed alternately by the queuing / throttling copyback protocol interface. ) Is almost constant (ie, denoted as VAR). As a result, in the nonvolatile memory system 100, 200, or 300 according to the embodiments of the present invention, since the response time (RESPONSE TIME) to the write request signal WRITE REQUEST is stable, The performance of the nonvolatile memory system 100, 200, 300 may be greatly improved. On the other hand, as described above, in the non-volatile memory system (100, 200, 300), the copyback operation reads the target page data stored in the source page into a predetermined buffer therein and writes it to the target page. It may be performed in a manner of using a copyback operation (eg, a physical level copyback operation) provided by some NAND flash memory devices, or by changing a mapping of a flash translation layer. May be performed. As a result, since the copyback operation is performed only inside the NAND flash memory device, the overall performance of the nonvolatile memory system 100, 200, 300 is improved, and power consumption of the nonvolatile memory system 100, 200, 300 is increased. Also, the write operation to the NAND flash memory device may be reduced, thereby improving lifespan.

FIG. 4 is a flowchart illustrating an example in which a copyback operation and a write operation are alternately performed in a nonvolatile memory system according to example embodiments. FIG. 5 is a flowchart illustrating a nonvolatile memory system according to example embodiments. A conceptual diagram illustrating an example in which a copyback operation and a writing operation are alternately performed.

As shown in FIGS. 4 and 5, in the nonvolatile memory system 100, 200, 300 according to the embodiments of the present invention, the NAND flash memory device may perform a copyback operation 500 from a host device. The copyback commands may be received in a queuing form, and a copyback processing rate command indicating that the processing rates of the copyback operation 500 and the write operation 400 are m: n may be received. Accordingly, the NAND flash memory device stores the copyback commands in a predetermined buffer in the form of queuing, and processes the copyback commands according to the queuing order. Specifically, since the NAND flash memory device has a processing ratio of the copyback operation 500 and the write operation 400 as m: n, the NAND flash memory device performs a copyback operation 500 for m page data (ie, target page data). After performing step S120, the write operation 400 for n page data (ie, write page data) may be performed (step S140). At this time, the NAND flash memory device determines whether to continuously perform the copyback operation 500 and the write operation 400 (Step S160) to continuously perform the copyback operation 500 and the write operation 400. If it should be performed, the steps (Step S120, Step S140) can be repeated continuously. However, this is only one example. As described above, in the NAND flash memory device, since the processing ratio between the copyback operation 500 and the write operation 400 is m: n, copyback of m page data is performed. While the operation 500 is performed, the write operation on the n page data may be alternately performed. On the other hand, although not shown in Figures 4 and 5, the NAND flash memory device, if a copyback cancel command is input from the host device while alternately performing the copyback operation 500 and the write operation 400, the copyback operation 500 may not be performed. Further, when a copyback completion command is input from the host device while performing the copyback operation 500 and the write operation 400 alternately, the NAND flash memory device preferentially performs the copyback operation 500 to be completed. Can be. However, since this has been described above, a duplicate description thereof will be omitted. Although the nonvolatile memory system according to the embodiments of the present invention has been described above with reference to the drawings, the description is illustrative and not restrictive within the scope of the present invention. And the like.

The present invention can be variously applied to a nonvolatile memory system having a NAND flash memory device. Accordingly, the present invention can be applied to a solid state drive (SSD), a secure digital card (SDCARD), a universal flash storage (UFS), an embedded multimedia card (EMMC), a CF card, a memory stick, an XD picture card and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. It can be understood that it is possible.

100: nonvolatile memory system 120: NAND flash memory device
122: first flash conversion layer 140: host device
142: second flash conversion layer 144: file system

Claims (9)

A host device that provides copyback commands for performing a copyback operation in a queuing form and provides a copyback processing rate command indicating a processing rate of the copyback operation and a write operation; And
A NAND flash memory device configured to perform the copyback operation based on the copyback commands, and alternately perform the copyback operation and the write operation according to the processing ratio;
If the processing ratio is m: n (where m and n are positive integers), the write operation on n page data is alternately performed before and after the copyback operation on m page data is performed. Non-volatile memory system, characterized in that. delete delete The method of claim 1, wherein the copyback operation is accompanied by a garbage collection operation or a journaling operation,
The NAND flash memory device includes a first flash translation layer that performs the copyback operation.
And the host device includes a file system and a second flash translation layer that interacts with the file system to control an operation of the NAND flash memory device. delete The NAND flash memory device of claim 1, wherein the NAND flash memory device does not perform the copyback operation when a copyback cancel command is input from the host device while the copyback operation and the write operation are alternately performed. Nonvolatile memory system. The NAND flash memory device of claim 1, wherein when a copyback completion command is input from the host device while the copyback operation and the write operation are alternately performed, the NAND flash memory device preferentially performs the copyback operation. Non-volatile memory system, characterized in that.

A host device that provides copyback commands for performing a copyback operation in a queuing form and provides a copyback processing rate command indicating a processing rate of the copyback operation and a write operation; And
A NAND flash memory device configured to perform the copyback operation based on the copyback commands, and alternately perform the copyback operation and the write operation according to the processing ratio;
When the processing ratio is m: n (where m and n are positive integers), the write operation on n page data is alternately performed between the copyback operations on m page data. Non-volatile memory system, characterized in that. 9. The method of claim 8, wherein the copyback operation is accompanied by a garbage collection operation or a journaling operation,
The NAND flash memory device includes a first flash translation layer that performs the copyback operation.
And the host device includes a file system and a second flash translation layer that interacts with the file system to control an operation of the NAND flash memory device.

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