KR101345437B1 - Interfacing apparatus and method for communication between chips - Google Patents

Abstract

An interface device for communication between a first chip operating as an application processor (AP) of the present invention and a second chip processing processes under the control of the AP, the address from the first chip to the second chip An address selection line for transmitting an address selection signal for distinguishing an address transmission section for transmitting related information and a data transmission section for transmitting data, and for transmitting the address related information or the data from the first chip to the second chip A plurality of address / data lines, a line transmitting a signal instructing to execute an operation from the first chip to the second chip, a line transmitting a signal instructing to execute a write operation, a read operation Control lines including a line for transmitting a signal instructing execution, the address selection line, the And a controller of the second chip for processing the data according to the number of address / data lines and the signals transmitted through the control lines, wherein the controller is configured to perform the control in the address transmission interval determined according to the address selection signal. The data transmitted in the data transmission section may be processed using read / write operation information, data size information, and address information acquired through the address related information transmitted through address / data lines.

Interface, address selection signal, address transmission section, data transmission section, burst transmission

Description

Interfacing apparatus and method for communication between chips

1 is a diagram illustrating an SRAM interface structure using a memory interface.

2 illustrates an SPI interface structure.

3 illustrates an I2C interface structure.

4 illustrates an interface structure using general-purpose input / output pins.

5 illustrates an interface structure according to a preferred embodiment of the present invention.

6 illustrates an interface device according to a preferred embodiment of the present invention.

7A and 7B illustrate data formats transmitted in an address transmission section and a data transmission section, respectively, according to an embodiment of the present invention.

8A and 8B are timing diagrams illustrating a single transmission operation in an interface device according to a preferred embodiment of the present invention.

9A and 9B are timing diagrams illustrating a burst transfer operation in an interface device according to a preferred embodiment of the present invention.

10 is a flowchart illustrating a communication procedure between chips according to a preferred embodiment of the present invention.

The present invention relates to an interface apparatus and method for chip-to-chip communication in a communication system.

In order to process processes in chips of a communication system, a means for connecting the chips and transmitting control signals and data is required. An interface is performed to perform such a function. The interface is a connection means, and a serial interface such as Serial Peripheral Interface (SPI), Inter-IC (I2C), or the like is used for communication between chips, or First In, First Out (FIFO). An interface such as static random-access memory (hereinafter referred to as SRAM) is used. The interfaces will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an SRAM interface structure using a memory interface. The SRAM interface is an interface used for memory access.

Referring to FIG. 1, one of the two chips is an application processor (hereinafter, referred to as an 'AP') 110 to control processing of processes. The other chip is a slave system 120 (hereinafter referred to as slave), which processes processes under the control of the AP.

Interfaces connecting the AP 110 and the slave 120 transmit three control signal lines Pin for transmitting control signals and 16 address lines for transmitting an address and data. There are 16 data lines. The control signal lines, that is, the chip select bar (hereinafter referred to as "CSB") line, the writing enable signal (hereinafter referred to as "WEB") line, and the output enable signal (output enable bar) The slave 120 performs a read / write operation according to a signal transmitted from the AP 110 through the “OEB” line. The slave 120 includes an interface controller 125 for controlling interface signals transmitted through the interface.

Using the CSB, WEB, and OEB transmitted from the AP 110, the slave 120 controls pads for a read / write signal and an internal block (not shown) (eg, a memory block). Control signal is determined, and a selection signal is generated using the address related information transmitted from the AP 110. Among the read / write signals, in the case of a write signal, data is transmitted from the AP 110 to an internal block through a data line, and when a read signal is activated, data read from the internal block is read from the data line. It is transmitted to the AP 110 through. At this time, the time taken to transmit one halfword is determined by the slower operating system among the slave 120 and the AP 110.

The SRAM interface has a clearly defined timing or standard for each signal, and thus is relatively simple to implement, and uses a large number of data lines (pins) to transmit high-speed data. In addition, the SRAM interface is very versatile enough to be applied in a System on Chip (SoC) including almost all central processing units (CPUs). However, many pins must be used for address and data transfer, and the die size increases due to the use of many pins even if the actual internal logic is small.

2 is a diagram illustrating an SPI interface structure.

Referring to FIG. 2, when an SPI interface is used between the AP 210 and the slave 220, three pins CLK, CSB, and DATA necessary for control signal transmission and data transmission are used. Here, the CLK carries a clock signal. As illustrated in FIG. 2, a data enable (DATA_EN) signal or an interrupt request (IRQ) signal may be further configured.

In general, the SPI interface is useful for transmitting continuous data streams that require less than 10Mbps of performance. However, in order to use the SPI interface for stream transmission, a lot of design effort is required in manufacturing the control unit (SPI I / F Controller) 225 of the slave 220, and the internal design complexity (Design) Complexity also increases.

3 is a diagram illustrating an I2C interface structure.

Referring to FIG. 3, when the I2C interface is used between the AP 310 and the slave 320, bidirectional communication is possible using two pins of SCL and SDA. The SCL line is a line carrying a clock signal, and the SDA line is a line transmitting data and control information. Since at least the I2C interface that can communicate using the two lines has a simple interface specification, it is easy to manufacture the controller (I2C I / F Controller) 325 of the slave 320, but the speed of the interface itself is high. There is a disadvantage that it is not suitable for data transmission because only a maximum of 400Kbps is supported.

In addition, since the I2C interface is basically divided into an address transmission section and an data transmission section, the control unit 325 can be easily manufactured without major changes in the system. Since the format is 8 bits, in order to transmit an address or data exceeding 8 bits, the data must be divided in two times, and a separate hardware block must be implemented to recognize it. There is a problem in that complexity increases.

4 is a diagram illustrating an interface structure using general purpose input / output (GPIO) pins.

Referring to FIG. 4, general purpose input / output pins are used to communicate between the AP 410 and the slave 420. Typically, a chip is equipped with general-purpose input and output pins for which no particular purpose is imposed.

For communication using the general-purpose input / output pins, the AP 410 sends the control signals CSB, WEB, OEB, R / W, ADDR_SEL, and SIZE [to the controller 425 of the slave 420 through the general-purpose input / output pins. 1: 0]), and data AD [15: 0]. The control unit 425 processes the data by accessing an internal block according to the transmitted control signals. Therefore, when using the general-purpose input and output pins, since the pins are already provided, no separate hardware logic is required.

However, although the number of pins used for the interface is small as shown in FIG. 4, it is not suitable for high-speed transmission of data because it communicates using general-purpose input / output pins. Also, the higher the frequency of software execution, the lower the performance of the system. Even if the software can be executed frequently, it cannot be processed quickly if it is necessary to continuously read data. Therefore, the interface structure as shown in FIG. 4 has a disadvantage that it can be applied to a system requiring a low data rate.

Accordingly, there is a need for a universally usable chip-to-chip interface with high data rates while reducing design complexity.

An interface device for communication between a first chip operating as an application processor (AP) of the present invention and a second chip processing processes under the control of the AP, the address from the first chip to the second chip An address selection line for transmitting an address selection signal for distinguishing an address transmission section for transmitting related information and a data transmission section for transmitting data, and for transmitting the address related information or the data from the first chip to the second chip A plurality of address / data lines, a line transmitting a signal instructing to execute an operation from the first chip to the second chip, a line transmitting a signal instructing to execute a write operation, a read operation Control lines including a line for transmitting a signal instructing execution, the address selection line, the And a controller of the second chip for processing the data according to the number of address / data lines and the signals transmitted through the control lines, wherein the controller is configured to perform the control in the address transmission interval determined according to the address selection signal. The data transmitted in the data transmission section may be processed using read / write operation information, data size information, and address information acquired through the address related information transmitted through address / data lines.

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An interface method for communication between a first chip that operates as an application processor (AP) of the present invention and a second chip that processes processes under the control of the AP, wherein the first chip is a controller of the second chip. Determining, by the controller, whether the address transmission section transmits address related information or a data transmission section transmitting data according to the address selection signal transmitted to the address selection signal; And processing data transmitted in the data transmission section by using read / write operation information, data size information, and address information acquired through the address related information to be transmitted.

The foregoing is a somewhat broad summary of features and technical advantages of the present invention in order that those skilled in the art will be better able to understand it from the following detailed description of the present invention. Additional features and advantages of the present invention, which form the subject matter of the claims of the invention, in addition to those features and advantages, will be better understood from the following detailed description of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be described with reference to the accompanying drawings. Those skilled in the art will appreciate that the concepts and specific embodiments of the invention described below may be altered or modified in various ways to attain the objects of the invention. It will also be appreciated by those skilled in the art that the concepts and structures equivalent to those disclosed herein are not to depart from the spirit and scope of the broadest form of the invention. It should be noted that the same reference numerals and the same elements in the drawings are represented by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention provides a universally usable interface having a high data rate with low design complexity by using multiple pins to transmit address and data in a communication system.

5 is a diagram illustrating an interface structure according to a preferred embodiment of the present invention. The present invention relates to 19 lines (CSB, WEB, OEB, AD [15: 0]) using dedicated pins for 19 SRAM interfaces for control signals and address / data, and to indicate an address phase. One general purpose I / O pin (GPIO) is used to communicate.

Referring to FIG. 5, the AP 510 controls the operation of the slave 520 by control signals transmitted through control signal lines. In detail, the AP 510 transmits CSB, WEB, and OEB signals to the slave as signals for controlling the slave 520. The AP 510 selects a slave 520 to process specific processes among the slaves. The AP 510 transmits the CSB signal to inform the selected slave 520 that the slave 520 is selected. The WEB signal is a signal for notifying that the selected slave 520 should perform a write operation at a specific time point, and the OEB signal is for notifying that the data for read operation should be transmitted to the selected slave 520 at a specific time point. It is a signal.

The AP 510 transmits data to be processed according to the control signals to the slave 520 through an AD [15: 0] line. In particular, the present invention multiplexes not only data but also address-related information through 16 AD [15: 0] lines for transmitting the data and transmits the same together. That is, instead of transmitting address-related information and data through separate lines (pins), the address-related information and data are integrated and transmitted through common lines while distinguishing an address-related information transmission section and a data transmission section. do. The present invention thus has sixteen integrated pins for address related information transfer and data transfer. The address-related information transmission section or data transmission section is distinguished by an address selection (Address_Select: ADDR_SEL) signal transmitted through a general-purpose input / output pin (GPIO). Thus, in the present invention, by not separately using pins for transmitting address related information, the number of pins used can be reduced without causing performance degradation. In addition, it is easy to apply to a small terminal having a large size constraint by reducing the number of pins used.

Interface signals transmitted from the AP 510 are transmitted to a host I / F controller 525 of the slave 520, and the controller 525 controls the processes according to the signals. Control to perform.

The interface and the controller 525 will be described in detail with reference to FIG. 6.

6 illustrates an interface device according to a preferred embodiment of the present invention. For convenience of description, the AP is not shown in FIG. 6 and will be omitted.

Referring to FIG. 6, the interface device 600 of the present invention may include a host-slave block corresponding to the controller 525, the host-slave block 525, and an AP (not shown). The interface 610 is connected. The interface structure of the present invention is similar to the SRAM interface structure, but the major difference is that the size of the data can be stipulated to support the burst operation in which the address and data are multiplexed and the data is continuously transferred easily. Since the signal of the existing SRAM interface is almost used as is, the performance can be improved without changing the system.

The host-slave block 525 is a control path engine (hereinafter referred to as "CPE") 620, an address path engine (hereinafter referred to as "APE") 630, a data path engine 640 (Data Path Engine, hereinafter referred to as 'DPE').

The CPE 620 receives an internal block (not shown) according to the control signals when the CSB 660 signal, the WEB 662 signal, and the OEB 664 signal, which are control signals, are input. I / O pad control of the I / O pad control, generates a signal for determining the read / read access (Write / Read access) to the internal block and delivers to the internal block. That is, the write / read 670 operation signal and the enable 672 signal are generated and transmitted to the internal block according to the input control signal. In addition, the APE 630 transmits the information on the address selection (ADDR_SEL) 666 signal received from the AP to the CPE 620 so that the CPE 620 matches the read / write timing with the read / write information. The write connection 670 signal and the enable 672 signal are transmitted to the inner block.

In this case, the CSB 660 signal is a signal indicating whether the selected chip (slave system) is operated. It means that '0' is used and '1' is not used. The WEB 662 signal is a signal for controlling whether or not a write operation is performed. If the signal is '0', the WEB 662 signal is performed. The OEB 664 signal is a signal for controlling whether the read operation is performed. When the signal OEB 664 is '0', it means that the read operation is performed. In addition, the CPE 620 controls the read / write operation of the APE 630 according to the control signals (CSB 660, WEB 662, OEB 664).

The CSB 660 signal refers to a signal transmitted through the CSB line 660, the WEB 662 signal refers to a signal transmitted through the WEB line 662, and the OEB 664 signal refers to an OEB line ( The signal transmitted through the 664, the write / read operation 670 signal is transmitted via the write / read operation line, the enable 672 signal is transmitted via the enable line 672, address The select 668 signal refers to a signal transmitted through the address select line 668. In addition, the lines are devices constituting the interface.

 The APE 630 determines whether the information received from the AP through the address / data (AD [15: 0]) line 668 through the address selection 666 signal received from the AP is address related information or data. In this case, the address selection 666 signal is 1 bit. If '0', it means address-related information transmission, and if '1', it means data transmission. When the address selection 666 signal provides address-related information as '0', the transmitted information (SIZE [1: 0], Address) and control signals (CSB 660, WEB 662, OEB ( The APE 630 controls the internal block selection (Select [x: 0]) 674 signal and the address (ADDR [x: 0]) 676 signal by controlling the CPE 620 according to the signal 664). Create and pass to the corresponding inner block.

Whether to perform a write operation or a read operation is determined by the CSB 660, WEB 662, and OEB 664 signals received by the CPE 620. The CPE 620 determines the APE 630 according to the determination. Control the operation of In detail, when it is determined to perform a write operation, the APE 630 according to the received address selection 668 signal may write a corresponding address to write data received through the AD [15: 0] lines. The data is transferred through the write data (WDATA [15: 0]) lines 678 to an inner block of the block. When it is determined that the read operation is performed, the APE 630 transmits data stored in the DPE 640 to the AP through the AD [15: 0] lines according to the received address selection 668 signal.

Herein, in the case of the read operation, data read from an internal block of a corresponding address is temporarily stored in a Tx First Input First Output Buffer (hereinafter referred to as 'Tx FIFO') 650 of the DPE 640. Stored as. In other words, the DPE 640 reads data read through the read data RDATA [15: 0] lines 680 from an internal block corresponding to the address provided from the APE 630 in a read operation. According to the burst size, the data is stored in a Tx First Input First Output Buffer (hereinafter referred to as Tx FIFO) 650. The APE 630 transmits the data stored in the DPE 640 to the AP through the AD [15: 0] lines 668 according to the control signals.

The size signal SIZE [1: 0] mentioned above is provided to the address selection 666 signal in the address transmission section for the purpose of providing information on the transmission unit of data transmitted for one address related information. Signal included. In the present invention, two bits are used to provide the size signal, which indicates a transmission unit of data transmitted between the slave and the AP. Each meaning of the 2-bit size signal according to an embodiment of the present invention may be determined as shown in Table 1 below. Burst operation is determined according to the transmission unit according to the size signal.

In the burst size of Table 1, a halfword represents a basic transmission unit, and one halfword represents 16 bits. In the system, one halfword transmission is called a single transfer, and a plurality of halfword transmissions is called a burst transfer. Referring to Table 1, when the size signal is '00', it means single transmission as one half word, and in other cases, burst transmission as a plurality of hard words. In addition, here, the single transmission means transmitting address related information every time data of one half word unit is transmitted, and the burst transmission means transmitting only one half word address related information when transmitting a plurality of data. That is, in the burst transmission, four halfwords transmit only one halfword of address-related information for four halfwords of data transmission, and eight halfwords transmit only one halfword of address-related information for eight halfwords of data transmission. . Accordingly, burst transmission means transmitting only one half word of address-related information to data transmission of a plurality of predetermined half words.

The size signal described above is included in a control signal transmitted through the AD [15: 0] line 668 in the address transmission section, and is transmitted. An example of a format in which the control signal is transmitted will be described with reference to FIG. 7A. In addition, the format of data transmitted in the data transmission section transmitted after the address transmission section is also shown in Fig. 7B.

7A and 7B illustrate data formats transmitted in an address transmission section and a data transmission section, respectively, according to an exemplary embodiment of the present invention.

Referring to FIG. 7A, address related information transmitted to AD [15: 0] lines 668 in an address transmission section is transmitted in 16 bits ([15: 0]), which are one halfword, and includes address information. The 12-bit address field, the 2-bit size field containing information on the size (transmission unit) of the data to be transmitted, and whether it is a read operation or a write operation for the data to be transmitted in the data transmission section. It consists of a 1-bit read / write (R / W) field that contains information about the information. By the read / write field value, it is possible to know whether a read operation or a write operation is performed on the address in the address transmission section. In this way, since the present invention can know in the address period whether to read or write data while transmitting the address transmission and the data transmission using 16 identical address / data lines, the data is read in the read operation. You can come and store it in advance, and send data quickly on demand.

Referring to FIG. 7B, data transmitted in a read operation or a write operation in a data transmission period is transmitted by 16 bits through the AD [15: 0] lines 668.

8A and 8B are timing diagrams illustrating a single transmission operation in an interface device according to a preferred embodiment of the present invention, and illustrate cases of write and read operations, respectively.

Referring to FIG. 8A, control signals transmitted from the interface apparatus 600 illustrated in FIG. 6 to the controller (host-slave block) 525 through the interface 610 will be described.

In the present invention, the address selection 666 signal of FIG. 6 is divided into an address transmission section (Address Phase) 801 and a data transmission section (Data Phase) 802.

As shown in FIG. 8A, a section in which the address selection ADDR_SEL signal is '0' means an address transmission section 801 for transmitting address related information. In the address transmission section 801, the controller 525 recognizes the information transmitted to the address / data (AD [15: 0]) lines 668 as address-related information, and the R / W through the transmitted information. Information, size information, and address information are obtained. The R / W information R / W, size information SIZE [1: 0], and address information Address are provided in the format shown in FIG. 7A. In FIG. 8A, since the size is 1, this corresponds to a single transmission of 1 halfword. The size information is provided as shown in Table 1 above.

As described above, in the single transmission, data is transmitted in the data transmission section 802 of one half word after the address transmission section 801. In addition, since the CSB signal is '0' in the address transmission section 801, the operation is executed, and since the WEB signal is '0', the write operation is performed.

After the address transmission section 801 has elapsed, the CSB signal becomes '0' and the AP instructs the controller 525 to execute an operation. This means that the data transmission section 802 is performed because the ADDR_SEL signal is '1'. . Accordingly, the controller 525 performs a read or write operation on data transmitted through AD [15: 0] lines. Since the WEB signal is '0', the controller 525 performs a write operation on the transmitted data. That is, the controller 525 writes the transmitted data to an internal block corresponding to the address Address0 by using the address information Address0 obtained through the information transmitted in the address transmission section 801.

In FIG. 8A, since the OEB signal indicating the read operation continues to indicate '1', the read operation is not performed.

Referring to FIG. 8B, as shown in FIG. 8A, a section in which the address select signal ADDR_SEL is '0' means an address transmission section 803 for transmitting address related information. In the address transmission section 803, the control unit 525 recognizes the information transmitted to the address / data (AD [15: 0]) lines 668 as address-related information, and the R / W through the transmitted information. Information, size information, and address information are obtained. In FIG. 8B, since the size is 1, this corresponds to a single transmission of 1 halfword. As described above, in the single transmission, data is transmitted in the data transmission section 804 of one half word after the address transmission section 803. In addition, since the CSB signal is '0' in the address transmission section 803, the operation is executed. Since the WEB signal is '0', the write operation is performed. That is, the operation is executed when the CSB signal is '0', which means that the write operation is performed because the WEB signal is '0'.

After the address transmission section 803 has elapsed, the CSB signal becomes '0' and the AP instructs the controller 525 to execute an operation, which means that the data transmission section 804 is made because the ADDR_SEL signal is '1'. . Accordingly, the controller 525 performs a read or write operation on data transmitted through the AD [15: 0] lines. Since the OEB signal is '0', the controller 525 performs a read operation to transmit the read data. At this time, the controller 525 reads from an internal block corresponding to the address Address0 using the address information Address0 obtained through the information transmitted in the address transmission section 803 and stored in the Tx FIFO 650. Data is transmitted when the CSB signal and the OEB signal become '0'. At this time, since the WEB signal indicating the write operation indicates '1' in the data transmission section 804, the write operation is not performed.

9A and 9B are timing diagrams illustrating a burst transmission operation in an interface device according to a preferred embodiment of the present invention, and illustrate cases of write and read operations, respectively.

Referring to FIG. 9A, the interface device 600 illustrated in FIG. 6 is described through control signals transmitted to the controller 525 through the interface 610.

As shown in FIG. 9A, a section in which the address select signal ADDR_SEL is '0' means an address transmission section 901 transmitting address related information. In the address transmission section 901, the control unit 525 recognizes the information transmitted to the address / data (AD [15: 0]) lines 668 as address-related information, and the R / W through the transmitted information. Information, size information, and address information are obtained. In FIG. 9A, since the size is 4, it corresponds to a burst transmission in which data of a plurality of halfwords is transmitted. This corresponds to the case where the size of Table 1 is '01'. As described above, in the case of burst transmission, data of a plurality of halfwords is transmitted in the data transmission section 902 after the address transmission section 901. That is, since the size is 4, data is transmitted by 4 halfwords in the data transmission section 902. In addition, since the CSB signal is '0' in the address transmission section 901, the operation is executed. Since the WEB signal is '0', the write operation is performed. That is, the operation is executed when the CSB signal is '0', which means that the write operation is performed because the WEB signal is '0'.

After the address transmission section 901 has elapsed, the CSB signal becomes '0' and the AP instructs the controller 525 to execute an operation, which means that the data transmission section 902 is performed because the ADDR_SEL signal is '1'. . Accordingly, the controller 525 performs a read or write operation on data transmitted through AD [15: 0] lines. Since the WEB signal is '0', the controller 525 performs a write operation on the transmitted data. In this case, the controller 525 writes the transmitted data to an internal block corresponding to the address Address0 using the address information Address0 obtained through the information transmitted in the address transmission section 901. At this time, for each half word data transmitted in the data transmission section 902, the provided address value Address0 is incremented by '2' and a write operation is performed on the corresponding address.

In FIG. 9A, since the OEB signal indicating the read operation continues to indicate '1', the read operation is not performed.

Referring to FIG. 9B, as shown in FIG. 9A, a section in which the address selection ADDR_SEL signal is '0' means an address transmission section 903 for transmitting address related information. In the address transmission section 903, the control unit 525 recognizes the information transmitted to the address / data (AD [15: 0]) lines 668 as address-related information, and the R / W through the transmitted information. Information, size information, and address information are obtained. In FIG. 9B, since the size is 4, it corresponds to a burst transmission in which data of a plurality of halfwords is transmitted. As described above, in the single transmission, data of a plurality of halfwords is transmitted in the data transmission section 904 after the address transmission section 903. That is, since the size is 4, data is transmitted by 4 halfwords in the data transmission section 904. In addition, since the CSB signal is '0' in the address transmission section 903, the operation is executed. Since the WEB signal is '0', the write operation is performed. That is, the operation is executed when the CSB signal is '0', which means that the write operation is performed because the WEB signal is '0'.

After the address transmission period 903 has elapsed, the CSB signal becomes '0' and the AP instructs the controller 525 to execute an operation, which means that the data transmission period 904 is performed because the ADDR_SEL signal is '1'. . Accordingly, the controller 525 performs a read or write operation on data transmitted through the AD [15: 0] lines. Since the OEB signal is '0', the controller 525 performs a read operation to transmit the read data. At this time, the controller 525 reads from an internal block corresponding to the address Address0 using the address information Address0 obtained through the information transmitted in the address transmission section 903 and stored in the Tx FIFO 650. Data is transmitted when the CSB signal and the OEB signal become '0'. At this time, the controller 525 reads data stored in the Tx FIFO 650 by increasing the provided address value Address0 by '2' and reading the data stored in the Tx FIFO 650 in the data transmission section 902. To the AP. Since the WEB signal indicating the write operation indicates '1' in the data transmission section 904, the write operation is not performed.

In case of a write operation instead of a single transfer in the transfer size as described in FIG. 9A and a write operation, address decoding is performed, and when a control signal related to the data transmission section is input, data to be written is transferred to an internal block. After that, the size value is decreased by one. Then, after automatically increasing the address of the next data, if a control signal related to the data transmission section is input again, the process of transferring the data to be written is repeatedly performed until the size value becomes '0'. 9A illustrates an embodiment of operating four halfwords, the data transmission section 902 is divided into four halfwords, and the controller 525 writes a write operation to the corresponding inner block in each halfword unit. To perform. Herein, the controller 525 increases the address of each half word of the data transmission section 902 by '2' and performs a write operation on the corresponding address. The reason why the address is increased by '2' is because the address is changed in units of 8 bits. In this way, an address for 8 halfwords or 16 halfwords can be generated.

In addition, when the transmission size is a burst transmission and a read operation as shown in FIG. 9B, the controller 525 performs address decoding and reads data read from the decoded address to the Tx FIFO 650 of FIG. 6. Save and decrease the size value by 1. Then, the controller 525 automatically increases the address of the next data, stores the read data back in the Tx FIFO 650, and decreases the size value by one. The controller 5250 repeats the above process until the size value becomes '0' while reading data, storing the data in the Tx FIFO 650 and reducing the size value. When transmitted, the controller 525 simultaneously transmits data stored in the Tx FIFO 650 to the AP.

As shown in FIG. 9B, FIG. 9B illustrates an embodiment of operating with four halfwords. Thus, the data transmission section 904 is divided into four halfwords, and the controller 525 reads data from the corresponding inner block. The operation of storing the Tx FIFO 650 is performed in units of halfwords. Herein, the controller 525 increases the address of each half word of the data transmission section 904 by '2' and reads data from the corresponding address.

However, when only a single transmission is performed as shown in FIGS. 8A and 8B, if there is no dedicated interface hardware logic, the software burden of the AP using the AP increases. Accordingly, as a method of increasing the data rate while effectively reducing the software burden of the AP, a burst operation without an address is proposed as shown in FIGS. 9A and 9B.

Further, in order to simplify hardware logic, the present invention proposes to receive data while automatically increasing an address according to a size SIZE [1: 0] signal in the case of a read operation in burst transmission. Therefore, since the write operation transmits data from the AP, the write operation can be transmitted to the internal bus while increasing only an address without a separate storage medium such as a FIFO. However, for write operations in burst transmissions, the slave must continue to send data to the AP as much as SIZE [1: 0] and must be stacked on a storage medium (eg Tx FIFO) in advance because it does not know how fast it will operate. By using the storage medium, performance can be greatly improved even in a read operation of the AP.

10 is a flowchart illustrating a communication procedure between chips according to a preferred embodiment of the present invention. In the present invention, an interface method for communicating between chips is based on the CSB 660, WEB 662, OEB 664, and ADDR_SEL 666 received from the interface 610 by the controller (host-slave block) 525 of FIG. 6. It is performed by generating a signal for a write or read operation by receiving a control signal of the H1) and accessing an internal block with the next incoming data.

Referring to FIG. 10, in step 1002, the controller 525 maintains an idle state.

In step 1004, when the control signals CSB 660, WEB 662, OEB 664, and ADDR_SEL 666 are received from the AP through the interface 610, the controller 525 determines whether a read operation is performed. Check it. The read operation may be confirmed by the 'R / W' field of FIG. 7A in the data transmitted through the address / data line. If it is determined that the read operation is performed by the control signal, the controller 525 proceeds to step 1006, and if it is determined that the write operation is performed, proceeds to step 1020.

In step 1006, the controller 525 determines whether the read operation determined in step 1004 is for single transmission or burst transmission in the address-related information transmitted in the address transmission section by the 'SIZE' (shown in Table 1) field. Check and set an initial size value according to the 'SIZE' information. If the operation is for a single transmission, the controller 525 proceeds to step 1018, and if the operation is for burst transmission, proceeds to step 1008.

In step 1008, the controller 525 decodes the address information transmitted through the AD [15: 0] lines to know an address to perform a read operation on the burst transmission.

In step 1010, the control unit 525 reads from the inner block of the corresponding address according to the decoded address information, stores it in the Tx FIFO 650, decreases the size value by one, and automatically stores the address value as '2'. Increase by.

In step 1012, the controller 525 checks whether the size value is zero. If the size value is 0, the process proceeds to step 1014. If the size value is not 0, the process returns to the step 1008.

In step 1014, the controller 525 transmits the data stored in the Tx FIFO 650 to the AP according to an operation instruction of the control signals 'CSB' signal and 'OEB' signal in step 1010. In FIG. 10, the transmission of the stored data to the AP is performed after the size value becomes 0. However, the stored data is transmitted to the control signal ('CSB' signal and 'OEB' signal even before the size becomes 0). ) May be transmitted to the AP according to the instruction to perform the operation. That is, even when performing steps 1010 to 1012, the controller 525 may transmit the data to the AP if an instruction to perform an operation of the control signal is performed.

If the operation is determined to be for a single transmission in step 1006, in step 1018, the controller 525 decodes the transmitted address, reads data from an internal block of the corresponding address, and transmits the data to the Tx FIFO 650. Save it. Thereafter, the controller 10 proceeds to step 1014 to transmit the stored data according to the operation execution instruction of the control signal ('CSB' signal and 'OEB' signal) related to the data transmission.

If the operation is determined to be a write operation in step 1004, in step 1020, the controller 525 checks the 'SIZE' (shown in Table 1) field in the address-related information transmitted in the address transmission section, in step 1004. It is checked whether the determined write operation is for single transmission or burst transmission, and sets a size value according to the 'SIZE' information. If the operation is for a single transmission, the controller 525 proceeds to step 1028. If the operation is for burst transmission, the control unit proceeds to step 1022.

In operation 1022, the controller 525 decodes address related information transmitted through AD [15: 0] lines to know an address to perform a write operation for the burst transmission. In addition, data is received from an AP through the AD [15: 0] lines according to the control signal ('CSB' signal and 'WEB' signal).

In step 1024, the controller 525 transmits the received data to an internal block of the corresponding address according to the decoded information, decreases the size value by 1, and automatically increases the address.

In step 1026, the controller 525 checks whether the size value is '0'. If the size value is '0', all operations for the write operation are performed, and therefore, operation 1016 is performed. If the size value is not 0, the flow returns to step 1022. That is, if the size value is not '0', it is determined that all data of burst transmission is not transmitted, and the process is repeatedly performed until the size value is '0'.

If it is determined in step 1020 that the operation is for a single transmission, in step 1028 the control unit 525 decodes the transmitted address and transmits data transmitted through AD [15: 0] lines to the decoded address. Access by accessing the internal block (Internal Access) and transmit.

In the above-described AP using the interface and the slave chip, the AP may communicate with the slave by executing software in the following order.

1. Set the GPIO pin connected to the slave to '0'. In the present invention, the general-purpose input / output pin is used as a signal ADD_SEL that provides information on whether an address transmission section or a data transmission section.

2. Determine the slave to execute the operation, and combine the address value, R / W value, and size value (SIZE [1: 0]) of the internal block to execute the operation with the slaves. Send it through.

3. Initialize the general purpose I / O pin setting (set it to '1').

4. Read / write data continuously according to the set R / W value and size value.

The format of the data to be used in the AP may be formed in the same format as that shown in FIGS. 7A and 7B.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited by the illustrated embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

As described above, the present invention is not only applicable to a field requiring a large bandwidth by using a conventional SRAM interface but also has an advantage that it can be easily used in a terminal having a large size restriction by using a small number of pins. In addition, by reducing the number of pins used, the PCB routing net is reduced, so that the terminal can be efficiently configured. The present invention can provide a universally usable chip-to-chip interface with high data rates while reducing design complexity. The present invention can provide a simple interface to implement when the external chip (particularly the AP) to be controlled, and can communicate without the constraints of the AP.

Claims (9)

An interface device for communication between a first chip that operates as an application processor (AP) and a second chip that processes processes under the control of the AP, An address selection line for transmitting an address selection signal for distinguishing an address transmission section for transmitting address-related information from the first chip to the second chip and a data transmission section for transmitting data; A plurality of address / data lines transferring the address related information or the data from the first chip to the second chip; A line for transmitting a signal instructing to execute an operation from the first chip to the second chip, a line for transmitting a signal for instructing the execution of a write operation and a line for transmitting a signal for instructing the execution of a read operation Control lines comprising a, And a controller of the second chip for processing the data according to the signals transmitted through the address selection line, the plurality of address / data lines, and the control lines, The controller uses the read / write operation information, data size information, and address information acquired through the address related information transmitted to the address / data lines in the address transmission section determined according to the address selection signal. Interface device characterized in that for processing the data transmitted in the transmission section. The method of claim 1, The data size information, Interface information characterized in that the information on the transmission unit of a single or a plurality of data transmitted for one address related information. delete The method of claim 1, Wherein, A read / write signal indicating whether a read operation or a write operation is received by an internal block by receiving a signal indicating execution of the operation, a signal indicating execution of a write operation, and a signal indicating execution of a read operation, and enabling the internal block ( A control path engine for transmitting a signal indicating a Enable state to the inner block; The address selection signal, the address-related information and a selection signal for receiving the data to inform the selection of the internal block and an address signal for transmitting an address are transmitted to the internal block, and the write operation under the control of the control path engine. An address path engine for transmitting the data to the inner block and transmitting data stored in a data path engine to the first chip in the read operation; In the case of the read operation, the interface device including a data path engine for storing the data read from the internal block. 5. The method of claim 4, The data path engine, And a storage unit configured to store data read from the internal block when the read operation is determined based on the read / write operation information of the address related information. An interface method for communication between a first chip that operates as an application processor (AP) and a second chip that processes processes under the control of the AP, Determining, by the controller, whether the controller transmits address-related information or a data transmission section for transmitting data according to an address selection signal transmitted by the first chip to the controller of the second chip; If the determination result is the address transmission section, the data transmission section using read / write operation information, data size information, and address information acquired through the address related information transmitted through address / data lines Interface method comprising the step of processing data transmitted to. The method according to claim 6, The data size information, Interface information characterized in that the information about a single or a plurality of data transmission units transmitted for one address-related information. The method according to claim 6, The process of processing the data, A read / write signal indicating whether a read operation or a write operation is received to an internal block by receiving a signal indicating operation execution, a signal indicating execution of a write operation, and a signal indicating execution of a read operation, and enabling the internal block Transmitting a signal indicating a status to the inner block; Receiving the address selection signal, the address related information and the data to inform the selection of the selection of the internal block, and transmits an address signal for transmitting an address to the internal block, and in the case of the write operation to the internal block Transmitting data and transmitting data stored in the controller to the first chip in the read operation; In the case of the read operation, the method further comprising the step of storing the data read from the internal block. 9. The method of claim 8, And storing data read from the internal block when it is determined that the read operation is performed through the read / write operation information of the address related information.

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