KR101326534B1

KR101326534B1 - Flip chip package

Info

Publication number: KR101326534B1
Application number: KR1020070045483A
Authority: KR
Inventors: 김은경; 김성동; 안효석; 장동영
Original assignee: 서울과학기술대학교 산학협력단
Priority date: 2007-05-10
Filing date: 2007-05-10
Publication date: 2013-11-08
Also published as: KR20080099655A

Abstract

The present invention discloses a flip chip package having a structure capable of realizing accurate alignment and bonding between bumps on a flip chip and pads of a substrate, which are electrically connected to the metal wires even if the pitch between metal wires constituting the flip chip is reduced.

A flip chip package according to the present invention includes a flip chip including a metal wire and a bump electrically connected to the metal wire; And

A flip chip package in which a cavity is formed on one surface and a conductive pad connected to a terminal includes a substrate formed on a surface of the cavity, and bumps of the flip chip are guided and aligned by the cavity and bonded to the conductive pad of the substrate.

The cavity is formed by an organic material layer having a predetermined height formed on the substrate, and includes a larger width than the flip chip to accommodate the flip chip,

The flip chip is bonded to the bump of the flip chip and the conductive pad of the substrate while the flip chip is located in the cavity, the flip chip has a lower edge is inserted into the cavity so that the side surface thereof corresponds to the top of the cavity, and the inner wall of the cavity The space between the outer circumferential surface of the flip chip is further filled with an underfill resin fixed to prevent the flip chip from flowing in the position.

Flip chip, pad, bump

Description

Flip chip package

1 is a schematic cross-sectional view of a flip chip package according to a first embodiment of the present invention;

2A through 2D are cross-sectional views of the substrate, in stages, illustrating a method of manufacturing the substrate of the flip chip package shown in FIG.

3 is a schematic cross-sectional view of a flip chip package according to a second embodiment of the present invention.

The present invention relates to a flip chip package, and more particularly, to a flip chip package configured so that bumps arranged with a fine pitch on the flip chip can be bonded in a precisely aligned state with pads on a substrate.

The fastest growing field in the electronic device package industry, such as semiconductor packages, is the flip chip field. In the flip chip bonding method, the flip chip and the substrate are aligned and electrically connected to each other in a state opposite to the conventional wire bonding method. Brief description of the flip chip bonding method is as follows.

Some regions of the metal lines constituting the flip chip are exposed to the outside through via holes (or pad openings), and conductive pads are formed on the exposed regions of the metal lines. Then, a conductive bump (minimum ball) is formed on the conductive pad of the flip chip, and the flip chip and the substrate are electrically connected (connected) by bonding the bump to the conductive pad formed on the terminal of the substrate.

The flip chip method has a higher connection density and a shorter connection distance than the conventional wire bonding and tape automated bonding (TAB) methods, thereby enabling high speed (high performance) and high density connection. The flip chip bonding technique involves bonding an under bump metallurgy (UBM) layer to the pad opening on the metal wiring of the flip chip and bonding the UBM layer (conductive pad) back to the conductive bumps.

By connecting the metal wires of the flip chip to the terminals of the substrate (more precisely, conductive pads electrically connected to the terminals) through the bumps, electrical signals can be transferred between the flip chip and the substrate, and mechanical bonding is also achieved. Here, the UBM layer has excellent bonding force between the bump of the flip chip and the conductive pad of the substrate, and serves to prevent mutual diffusion between the bump of the flip chip and the substrate.

In the state where the size of the flip chip is small or unchanged, the density of the metal wiring of the flip chip increases with the high integration of the device, and thus the pitch between the conductive pads formed in the exposed area of the metal wiring, i.e., on the conductive pad. The pitch between the formed bumps can only be reduced significantly.

The increase in metallization of the flip chip due to this high integration reduces the pitch of the bumps, including processes such as alignment accuracy between the flip chip and the substrate, selection of bump and UBM materials, height uniformity of the bumps, and power supply. This brings about design difficulties.

In particular, when mounting a flip chip on a substrate in which the pitch between bumps formed in the flip chip is significantly reduced, the bump may not be bonded correctly to the corresponding pad of the substrate, but may be partially bonded, or may be in contact with other pads adjacent thereto. have. This phenomenon is a problem that must be solved, which impairs the basic functions of the device.

The present invention is to solve the misalignment between the bump of the flip chip and the conductive pad of the substrate caused by the pitch reduction between the metal wiring of the flip chip due to the high integration of the flip chip, that is, the pitch between bumps formed in the exposed area of the metal wiring. It is an object of the present invention to provide a flip chip package capable of realizing accurate alignment between a bump formed on a flip chip and a conductive pad formed on a substrate.

A flip chip package according to the present invention includes a flip chip including a metal wire and a bump electrically connected to the metal wire; And a substrate having a cavity formed on one surface thereof, the substrate including a conductive pad connected to a terminal formed on a surface of the cavity, wherein bumps of the flip chip are guided and aligned by the cavity and bonded to the conductive pad of the substrate.
The cavity is formed by an organic material layer having a predetermined height formed on the substrate, and includes a larger width than the flip chip to accommodate the flip chip,
The flip chip is bonded to the bump of the flip chip and the conductive pad of the substrate while the flip chip is located in the cavity, the flip chip has a lower edge is inserted into the cavity so that the side surface thereof corresponds to the top of the cavity, and the inner wall of the cavity The space between the outer circumferential surface of the flip chip is further filled with an underfill resin fixed to prevent the flip chip from flowing in the position.

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Hereinafter, a flip chip package according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view of a flip chip package according to the present invention. The flip chip package according to the present invention may include a substrate 20 (or a chip carrier) on which the flip chip 10 and the flip chip 10 are mounted. Board).

Part of the metal wiring constituting the flip chip 10 is exposed to the outside through the via hole, and the conductive pad (not shown in the drawing) serves as a power and input / output terminal in the exposed area of the metal wiring. ) Is formed. The conductive bumps 11 are formed on such conductive pads. The bump 11 may be a copper bump, a gold bump, or a solder bump.

Gold has excellent physical and electrical conductivity, high chemical stability, and does not violate acid and alkali solutions and does not oxidize when heated to high temperatures.

Solder bumps may be formed through various processes such as vacuum deposition, printing, and the like, and in particular, the electroplating process and the printing process are known to be suitable for mass production of solder bumps.

On the other hand, copper bumps are relatively easy to increase the condensation density (connnection density), has excellent electrical and mechanical properties, and has a very high heat transfer properties.

A cavity 22 having a predetermined depth is formed on one surface of the substrate 20 on which the flip chip 10 is mounted, and a surface of the substrate 20 in the cavity 22 is electrically connected to a terminal (not shown). A plurality of conductive pads 21 are formed.

The cavity 22 of the substrate 20 is sized to accommodate the flip chip 10 therein, and in particular, the pad 21 formed on the surface of the substrate 20 in the cavity 22 is the flip chip 10. It is disposed so as to correspond to the bump 11 formed in the one-to-one state, respectively.

On the other hand, if the bottom edge of the flip chip 10 satisfies the condition that is located in the cavity 22 (that is, the condition that the top of the cavity 22 corresponds to the side of the flip chip 10), the substrate 20 The depth of the cavity 22 formed in the surface of is not limited.

In addition, the cavity 22 has a size (area) that can accommodate the flip chip 10, but it is desirable to minimize the gap between the inner wall of the cavity 22 and the outer peripheral surface of the flip chip 10.

In order to electrically connect the substrate 20 and the chip 10 having such a shape, the flip chip 10 is positioned in the cavity 22 of the substrate 20. In this process, the flip chip 10 is automatically guided by the cavity 22, so that the bump 11 formed on the flip chip 10 and the corresponding pad 21 formed on the substrate 20 are automatically aligned to each other. Correspond exactly.

In this state, by bonding the pad 21 of the substrate 20 and the bump 11 of the flip chip 10, the chip 10 and the substrate 20 are electrically connected to each other.

On the other hand, the flip chip 10 is horizontal in the cavity 22 of the substrate 20 according to the conditions of the cavity 22 described above, that is, the height and size of the cavity 22 with respect to the flip chip 10. The bumps 11 of the flip chip 10 may maintain an accurate electrical connection with the pads 22 formed on the surface of the substrate 20 in the cavity 22.

As described above, the underfill resin is accommodated in the state in which the flip chip 10 is accommodated in the cavity 22 of the substrate 20, and the bump 11 of the flip chip 10 and the pad 21 of the substrate 20 are electrically connected to each other. An underfill resin (R of FIG. 1) is used to fill a space existing between the outer circumferential surface of the flip chip 10 and the inner wall of the cavity 22.

As the underfill resin, it is preferable to use a material which is excellent in heat resistance, impact resistance, filling resistance and has a fast curing rate. By the underfill resin, the flow of the flip chip 10 accommodated in the cavity 22 is suppressed, and thus the pads 22 formed on the bump 11 of the flip chip 10 and the surface of the substrate 20 in the cavity 22. The electrical connection of can be maintained more firmly.

On the other hand, the same effect can be obtained even if the underfill resin layer is formed so as to correspond to the entire cavity 22 including the flip chip 10.

As described above, a process of forming the cavity 22 on the substrate 20 in order to accurately align the bump 11 of the flip chip 11 and the pad 21 on the substrate 20 will be described.

2A to 2D are cross-sectional views of a substrate for describing a method of manufacturing a substrate of the flip chip package shown in FIG. 1.

First, referring to FIG. 2A, a plurality of conductive pads 21 are formed on the surface of the substrate 20 to be electrically connected to a terminal (not shown). That is, the conductive pad 21 is formed through a process of forming an existing substrate pad such as sputtering on the terminal of the substrate 20.

In this state, an organic material layer 30 is formed on the substrate 20 including the conductive pads 21 through a printing process or a deposition process (state of FIG. 2B).

In the state where the mask 40 is positioned on the organic layer 30 (the state of FIG. 2C), a portion of the organic layer 30 is selectively removed through an exposure process, and then the mask 40 is removed.

Through the above process, as shown in FIG. 2D, a partition wall 31 made of organic material is formed around a predetermined area of the substrate 20, that is, the area where the pad 21 is disposed, and the inner space of the partition wall 31 is formed. As shown in FIG. 1, the function of the cavity 22 in which the flip chip 10 is accommodated is performed. The partition wall 31 may be formed of an inorganic material, but the reliability of the problem of thermal expansion may not be better than that of the organic material.

Meanwhile, the partition wall 31 constituting the cavity 22 on the substrate 20 may be formed through a deposition process or a patterning process using a dielectric material.

3 is a schematic cross-sectional view of a flip chip package according to another embodiment, and for convenience, only four bumps among bumps formed on one surface of the flip chip are illustrated.

The flip chip package according to the present exemplary embodiment includes a flip chip 100 and a substrate 200 (or a chip carrier or a board) on which the flip chip 100 is mounted.

A plurality of bumps 110 are formed on one surface of the flip chip 100 to be electrically connected to an exposed area of a metal wire (not shown). Kinds of the bumps 110 and materials constituting the bumps 110 have already been mentioned in the description of the first embodiment.

On one surface of the substrate 200 on which the flip chip 100 is mounted, a plurality of conductive pads 210 electrically connected to terminals formed on the substrate 200 are formed. Meanwhile, each conductive pad 210 includes an under bump metallurgy (UBM) layer formed by the process described in the first embodiment. The conductive pads 210 formed on the substrate 200 are disposed to correspond to the bumps 110 formed on the flip chip 100 in a one-to-one state.

Meanwhile, an insulator layer 300 such as an epoxy resin is formed around each conductive pad 210, and the insulator layer 300 has a thickness higher than that of the conductive pad 210. Therefore, the cavity 310 of a predetermined space is formed on the conductive pad 210 by the insulator layer 300. The formation process of the insulator layer 300 uses the substrate pad opening formation process.

In order to electrically connect the substrate 200 and the flip chip 100 having such a shape, the substrate 200 and the flip chip 100 correspond to each other. In this process, each bump 110 formed on the flip chip 100 is positioned in the insulator layer 300 around the corresponding conductive pad 211 of the substrate 200, that is, the cavity 310 formed by the insulating layer 300. )

In this state, since each bump 110 is located in the cavity 310 in the insulating layer 300, when an external force is applied to the substrate 200 or the flip chip 100, or the substrate 200 and the flip chip 100. Even if the initial alignment between the pins is slightly fined, the bumps 110 do not deviate from the cavity 310, and thus each bump of the flip chip 100 does not come into contact with any conductive pads other than the set conductive pads.

As such, the flip chip 100 and the substrate 200 are electrically connected to each other by bonding the conductive pads 210 of the substrate 200 and the bumps 110 of the flip chip 100 to each other in a corresponding state. Bonding of the conductive pad 210 of the substrate 200 and the bump 110 of the flip chip 100 may be performed by various known processes, and thus description thereof will be omitted.

Meanwhile, the height of the insulating layer 310 forming the cavity 310 on the substrate 200 is preferably greater than the height of the conductive pad 210 and smaller than the height of the bump 110 formed on the flip chip 100 surface. . In addition, the area of the cavity 310 is preferably the same as the area of the corresponding bump 110, but determines the area of the cavity 310 so that the bump 110 can be located without damage.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art having various ordinary skill in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. And additions should be considered to be within the scope of the following claims.

For example, in the above description, a structure in which a bump electrically connected to an exposed area of a metal wire of a flip chip is bonded to a conductive pad of a substrate is described, but the present invention is not limited thereto. That is, the present invention can also be applied to a flip chip package having a structure in which a first bump electrically connected to an exposed area of a metal wiring of a flip chip is bonded to a second bump formed on a conductive pad of a substrate.

In the flip chip package according to the present invention as described above, when the bump formed on the flip chip and the conductive pad formed on the substrate, the flip chip is guided to the cavity formed on the substrate, thereby correcting the alignment of the flip chip and the substrate, that is, the bump of the flip chip and the like. Accurate alignment between conductive pads of the substrate can be made.

In addition, a predetermined space is formed by the insulating layer formed around the conductive pad of the substrate, so that bumps formed on the flip chip are guided into the space, so that the bumps of the flip chip and the conductive pad on the substrate are accurately aligned. As a result, an accurate electrical connection is made between the substrate and the flip chip.

Claims

A flip chip comprising a metal wire and a bump electrically connected to the metal wire; And

The flip chip is bonded to the bump of the flip chip and the conductive pad of the substrate while the flip chip is located in the cavity, the flip chip has a lower edge is inserted into the cavity so that the side surface thereof corresponds to the top of the cavity, and the inner wall of the cavity And a space between the outer circumferential surfaces of the flip chip to fill an underfill resin to fix the flip chip so that the flip chip does not flow in the position.

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The flip chip package of claim 1, wherein the substrate further comprises a bump formed on the conductive pad and electrically connected to the bump of the flip chip.