KR101321221B1 - Cryptographic modular apparatus and cryptographic modular method - Google Patents

Abstract

PURPOSE: A modular multiplication device for a password and a method are provided to repetitively perform a twice modulus operation and an add modulus operation, thereby implementing an elliptic curve on a finite field. CONSTITUTION: A coefficient selection unit (110) extracts a coefficient for each bit order for a multiplier from two elements. A twice modulus operation unit (120) performs a first twice modulus operation for a multiplication operation result for a most significant n-bit coefficient and a multiplicand. An add modulus operation unit (130) performs a first add modulus operation for a multiplication operation result for a (n-1) bit coefficient and the multiplicand. A control unit (140) repetitively performs the first twice modulus operation and the first add modulus operation for a lower bit coefficient and the multiplicand. [Reference numerals] (110) Coefficient selection unit; (120) Twice modulus operation unit; (130) Add modulus operation unit; (140) Control unit; (AA) Atom B; (BB) Atom A

Description

Modular multiplication apparatus for cryptography and its method {CRYPTOGRAPHIC MODULAR APPARATUS AND CRYPTOGRAPHIC MODULAR METHOD}

The present invention relates to a cryptographic modular multiplication apparatus and method for an elliptic curve cryptographic system on a finite field.

Due to the advantages of elliptic curve cryptography, efforts are being made worldwide to implement an elliptic curve on a finite body in hardware. Efficient finite field multiplication of elliptic curves on GF (p) for odd characteristic and exponent prime p near 2, efficient finite field multiplication in Certicom's Optimal Normal Basis (ONB) In addition, various techniques have been tried, such as efficient finite field multiplication implementation in Cylink's Optimal Normal Basis (ONB).

However, these recent various techniques have (1) a large amount of computation required to perform public and private key transmissions, and (2) a storage space required for storing arbitrary keys with very large key sizes in terms of key size. (3) In terms of communication bandwidth, there is a problem in that the communication bandwidth required for encrypting a message or transmitting a signature is very large.

In addition, in case of side channel attack (SCA) that finds a secret key by using / analyzing additional information such as power consumption, algorithm execution time, power consumption difference, electromagnetic wave emission amount, etc. This is a real threat to the implementation of cryptographic algorithms in embedded hardware such as ICs, mobile phones, PDAs, and the like. Accordingly, since the operation execution time per unit bit of the secret key is long and the power consumption is large, the focus on the power consumption analysis (SPA and DPA) technology and the corresponding scalar multiplication algorithm is focused.

Republic of Korea Patent Publication No. 1020090037124 (2009.04.15), "Cryptographic operation system having a modular multiplication method, a modular multiplier and a modular multiplier" Republic of Korea Patent Publication No. 1020000000770 (2000.01.15), "Modular multiplication device" Republic of Korea Patent No. 1006304560000 (September 25, 2006), "Scalable multiplication operator on the finite"

By repeatedly performing double modulus and addition modulus operations, we propose a cryptographic multiplying device that can implement an elliptic curve on a finite body in hardware.

In addition, the present invention provides an encryption multiplication apparatus and method for reducing the delay time by performing addition modulus operations by dividing the addition operations in the case of rounding numbers '0' and '1' in 4 bit units in parallel. I would like to.

 Modular multiplication apparatus for two elements of the elliptic curve lower finite body according to an embodiment of the present invention is a coefficient selector for extracting the coefficient of the bit order for the multiplier (multipilier) of the two elements, the most significant n-bit coefficient and multiplier extracted from the multiplier a double modulus operator for performing a first double modulus operation on the multiplicand result of the multiplicand, and a result of the first double modulus operation performed, and a multiplication operation on the n-1 bit coefficient and the multiplier extracted from the multiplier An addition modulus operation unit for performing a first addition modulus operation on.

 The cryptographic modular multiplication apparatus sequentially repeats the first double modulus operation and the first addition modulus operation on the lower bit coefficient and the multiplicand extracted from the multiplier based on the result of performing the first addition modulus operation. The apparatus may further include a controller controlling a double modulus calculator and the addition modulus calculator.

The double modulus operation unit performs a second double modulus operation on the result of performing the first addition modulus operation, and the addition modulus operation unit performs the result of the second double modulus operation, n-2 bit coefficients, and multiplicands. A second addition modulus operation may be performed on the result of the multiplication operation.

The addition modulus operation unit divides the first double modulus operation result and the multiplication operation result into 4 bit units, and adds the first double modulus operation result in 4 bit unit and the multiplication operation result in 4 bit unit in parallel. You can perform the operation.

The addition modulus operation unit includes a carry value by performing an add operation when the rounding numbers are '0' and '1' in parallel with a first double modulus operation result in 4-bit units and a multiplication operation result in 4-bit units. It may include one or more four-bit adder for outputting a five-bit result.

Each of the one or more 4-bit adders includes: a first result output unit configured to perform an addition operation when the rounding number is '0'; A second result output unit configured to perform an addition operation when the rounding number is '1'; And a multiplexer which receives a 1-bit carry bit outputted from a lower unit 4-bit adder and selects one of an execution result value of the first result output unit and the second result output unit based on the received carry bit. It may further include.

The cryptographic modular multiplication method for two elements of an elliptic curve lower finite body in accordance with an embodiment of the present invention comprises the steps of extracting the coefficient of the bit order for the multiplier of the two elements, the highest n-bit coefficient and the multiplier extracted from the multiplier Performing a first double modulus operation on the result of the multiplication operation for the first double modulus operation, and a first addition modulus on the result of the multiplication operation on the n-1 bit coefficient and the multiplier extracted from the multiplier. Performing the operation.

The cryptographic modular multiplication method sequentially repeats the first double modulus operation and the first addition modulus operation on a lower bit coefficient and a multiplicand extracted from the multiplier based on a result of performing the first addition modulus operation. It may include the step of controlling.

In the performing of the first double modulus operation, the first double modulus operation result and the multiplication operation result are respectively divided into 4 bit units, and the first double modulus operation result and 4-bit multiplication operation are respectively performed in 4-bit units. Performing an addition operation on the result in parallel.

In the step of performing an addition operation in parallel, the addition operation when the rounding number is '0' and '1' is parallel to the first double modulus operation result in 4-bit units and the multiplication operation result in 4-bit units. And outputting a 5-bit result including a carry value.

According to an embodiment of the present invention, an elliptic curve on a finite body may be hardware-implemented by repeatedly performing a double modulus operation and an addition modulus operation.

In addition, according to an embodiment of the present invention, the addition operation when the rounding numbers are '0' and '1' may be divided into 4 bit units to perform an add modulus operation in parallel to reduce the delay time.

1 is a block diagram illustrating a configuration of a cryptographic modular multiplication apparatus according to an embodiment of the present invention.
2 illustrates a modular multiplication device for 224 bits cryptography according to an embodiment of the present invention.
3 is a block diagram of a coefficient selector of a 224 bit cryptographic multiplication apparatus according to an embodiment of the present invention.
4 illustrates a configuration of a double modulus calculation unit of a 224-bit cryptographic modular multiplication apparatus according to an embodiment of the present invention.
5 is a block diagram of an addition modulus calculator of an N-bit cryptographic multiplication apparatus according to an exemplary embodiment of the present invention.
FIG. 6 illustrates a 4-bit adder of an add modulus calculator according to an exemplary embodiment of the present invention.
7 illustrates a configuration of a modulus calculation unit of a cryptographic modular multiplication apparatus according to an embodiment of the present invention.
FIG. 8 summarizes the synthesis result for the 224-bit elliptic curve cryptographic modular multiplication device according to an embodiment of the present invention, and FIG. 9 shows the simulation result.
10 is a flowchart illustrating a cryptographic modular multiplication method for two elements of an elliptic curve lower finite body according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

1 is a block diagram illustrating a configuration of a cryptographic modular multiplication apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the cryptographic modular multiplication apparatus 100 according to an embodiment of the present invention includes a coefficient selector 110, a double modulus operator 120, and an add modulus operator 130.

As illustrated in FIG. 1, AB mod P, which is a modular multiplication, may be calculated for an element A and an element B of an elliptic curve lower fin through a cryptographic modular multiplier according to an embodiment of the present invention. Where P = 2 ⁿ −t and A = a _{n −1} 2 ^n-1 + a _{n -2} 2 ^n-2 + o + o + a ₁ 2 + a ₀ = (a _{n -1} , a _{n -2} , ㅇㅇㅇ, a ₀ ) and B = b _{n -1} 2 ^n-1 + b _{n -2} 2 ^n-2 + ㅇㅇㅇ + b ₁ 2 + b ₀ = (b _n-1 , b _{n -2} , ㅇ ㅇㅇㅇ, b ₀ ).

The coefficient selector 110 extracts a coefficient for each bit order of the multipilier among two elements of the elliptic curve lower finite body. In the case of FIG. 1, the coefficient selector 110 may extract b _{n −1} to b _{0, which} are coefficients for each bit order of the element B that is a multiplier.

The double modulus operator 120 performs a first double modulus operation on the multiplication result of the most significant n-bit coefficient and the multiplicand extracted from the multiplier from the coefficient selector 110. The first double modulus operation may be a double mod P based operation on one finite element.

1, the double modulus calculating section 120 for the first multiplication result of b _{n -1} A of the n most significant bits of the coefficient b _{n -1} and the multiplicand element A extracted from the multiplier element B The result of the first double modulus operation b _{n -1} A2mod P may be output by performing a double modulus operation 2mod P.

The addition modulus operator 130 performs a first addition modulus operation on the first double modulus operation result and the multiplication operation result of the n−1 bit coefficient and the multiplier extracted from the multiplier. The first addition modulus operation may be an add mod P-based operation of two finite field elements.

As shown in FIG. 1, the addition modulus calculation unit 130 performs b _{n -1} A2mod P which is the result of the first double modulus operation performed, b _{n -2} which is the adjacent lower bit of the most significant bit from the element B that is a multiplier, and the element. A first addition modulus operation may be performed based on the result of the multiplication operation A on b _{n -2} A mod P, and the result of the first addition modulus operation (b _{n -1} A2mod P) + b _n-2 A mod You can output P

The cryptographic modular multiplication apparatus 100 according to an embodiment of the present invention is a first double modulus operation and a first addition modulus with respect to a lower bit coefficient and a multiplicand extracted from a multiplier based on a result of performing a first addition modulus operation. The controller 140 may further include a controller 140 controlling the double modulus operator 120 and the add modulus operator 130 to sequentially repeat the operation.

According to an embodiment, the controller 140 controls the double modulus operator 120 to perform a second double modulus operation on the result of performing the first addition modulus operation, and the second modulus operator 130 performs the second modulus operation. The second modulus operation may be performed to perform the double modulus operation result and the multiplication operation result of the n-2 bit coefficient and the multiplicand.

As shown in FIG. 1, the double modulus operator 120 performs a second double modulus operation on (b _{n -1} A2mod P) + b _{n -2} A mod P which is a result of performing the first addition modulus operation. ) To output ((b _{n -1} A2mod P) + b _{n -2} A mod P)) 2mod P as a result of the second double modulus operation.

In addition, the addition modulus calculation unit 130 may apply to (mod) (b _{n -1} A2mod P) + b _{n -2} A mod P) 2mod P, which is the result of the second double modulus operation, and n-2 bit coefficients and multiplicands. Can perform a second addition modulus operation on b _{n -3} A mod P, which is the result of the multiplication operation, and the result of the second addition modulus operation ((b _{n -1} A2mod P) + b _{n -2} A mod P 2) mod P + b _{n -3} A mod P can be printed.

The control unit 140 extracts from the multiplier based on the result of performing the second addition modulus operation and then double modulus operation unit 120 and addition to sequentially repeat the double modulus operation and the addition modulus operation on the lower bit coefficient and the multiplicand. The modulus calculator 130 may be controlled. Hereinafter, a modular multiplication apparatus for 224 bit elliptic curve cryptography according to an embodiment of the present invention will be described in detail with reference to FIG. 2.

2 illustrates a modular multiplication device for 224 bits cryptography according to an embodiment of the present invention.

Referring to FIG. 2, the cryptographic modular multiplication apparatus 100 according to an embodiment of the present invention uses a coefficient selector 110, a chooser, a double modulus operation unit 120 (A2mod P), and an addition modulus operation unit 130 (CPlusDmodP). The cryptographic modular multiplication apparatus 100 includes the above-described process of performing mod P twice of one finite element and addition mod P of two finite elements for performing AB mod P, which is a modular multiplication of Equation 1 below. Is performed sequentially and repeatedly.

[Equation 1]

However, in Equation 1, P = 2 ⁿ −t and A = a _{n −1} 2 ⁿ⁻¹ + a _{n −2} 2 ^n-2 + ..... + a ₁ 2 + a ₀ = (a _{n -1} , a _n-2 , ...., a ₀ ) and B = b _{n -1} 2 ^n-1 + b _{n -2} 2 ^n-2 + .... + b ₁ 2 + b ₀ = (b _{n -1} , b _{n -2} , ...., b ₀ ).

The coefficient selector 110 extracts a bit order coefficient for a multiplier of two elements of the elliptic curve lower finite field. Both elements A and B may be elements of a 224 bit elliptic curve lower finite body. Hereinafter, referring to FIG. 3, the coefficient selector of the 224 bit cryptographic multiplier according to the embodiment of the present invention will be described in detail.

3 is a block diagram of a coefficient selector of a 224 bit cryptographic multiplication apparatus according to an embodiment of the present invention.

Referring to FIG. 3, the coefficient selector 110 of the cryptographic modular multiplication apparatus 100 according to an exemplary embodiment of the present invention may extract a start signal S_chooser and a clock clk in order to extract a coefficient for each bit order for a multiplier. Means for adjusting the bit order 112 from the most significant bit to the least order relative to the 224-bit multiplier value In_chooser inputted on the basis of; and an extraction means for selecting and extracting a coefficient for each order starting from the most significant bit ( 113, and means 11 for combining the extracted order-specific coefficients.

The coefficient selector 110 outputs the coefficient for each order extracted according to the end signal d_chooser as an output value o_chooser.

Referring back to FIG. 2, the double modulus arithmetic unit 120 (A2mod P) performs a double modulus operation on the result of the multiplication operation on the multiplicand and the bit coefficient extracted from the multiplier from the coefficient selector 110 (Chooser). . The double modulus operation may be a double mod P based operation on one finite element. Hereinafter, referring to FIG. 4, a double modulus calculation unit of a 224-bit cryptographic modular multiplication apparatus according to an embodiment of the present invention will be described in detail.

4 illustrates a configuration of a double modulus calculation unit of a 224-bit cryptographic modular multiplication apparatus according to an embodiment of the present invention.

Referring to FIG. 4, the double modulus operator 120 of the cryptographic modular multiplication apparatus 100 according to an embodiment of the present invention outputs an output value o_A2 by performing a double modulus operation from a 224 bit input value In_A. do. The 224 bit input value In_A may be a multiplication result of a bit coefficient for each multiplier and a multiplicand.

To this end, the double modulus calculation unit 120 performs a double operation from the 224 bit input value In_A to output a result In_A2 121 and a modulus operation to the output In_A2 of the output double operation. It may include a means (122, U mod P) for performing the output (o_u mod P).

Referring back to FIG. 2, the add modulus operator 130 (CPlusDmodP) performs an add modulus operation on the result of the double modulus operation performed and the multiplication operation result of the lower bit coefficient and the multiplier extracted from the multiplier. The addition modulus operation may be an addition mod P-based operation of two finite fields. Hereinafter, an addition modulus calculation unit of an N-bit cryptographic multiplication apparatus according to an embodiment of the present invention will be described in detail with reference to FIG. 5.

5 is a block diagram of an addition modulus calculator of an N-bit cryptographic multiplication apparatus according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the addition modulus calculator 130 of the cryptographic modular multiplication apparatus 100 according to an embodiment of the present invention may perform the element modulus C and the addition modulus operation from two input elements C and D of N bits. Each element D is divided into 4 bit units. According to an embodiment, the k value shown in FIG. 5 may be a divisor of 224 bits to distinguish 4 bits.

According to an embodiment, the add modulus operator 130 performs an add operation in the case where the rounding numbers are '0' and '1' in parallel for each of the 4-bit unit of the element C and the 4-bit unit of the element D, thereby performing one-bit addition operation. It may include one or more four-bit adder 210 for outputting a five-bit result containing a carry out of.

As illustrated in FIG. 5, each of the 5-bit results may include a carry out of 1 bit, and an addition operation result of 4 bits of the divided element C and 4 bits of the element D. FIG.

The addition modulus operator 130 outputs a result value of N + 1 bits as a result of the addition operation of the elements C and D. Hereinafter, the 4-bit adder 210 will be described in detail with reference to FIG. 6.

FIG. 6 illustrates a 4-bit adder of an add modulus calculator according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the add modulus calculator 130 may include a first result output unit 211, a second result output unit 212, and a multiplexer 213.

The first result output unit 211 (C + D) performs an addition operation when the rounding number is '0' for the 4-bit unit of the element C and the 4-bit unit of the element D. FIG. The second result output unit 212 (C + D + 1) performs an addition operation when the rounding number is '1' for the 4-bit unit of the element C and the 4-bit unit of the element D. FIG.

Also, the multiplexer 213 receives a 1-bit carry in output from the lower unit 4-bit adder and based on the received cavibit, the first result output unit 211 and the second result output unit ( Select any one of 212).

7 illustrates a configuration of a modulus calculation unit of a cryptographic modular multiplication apparatus according to an embodiment of the present invention.

Referring to FIG. 7, the modulus operation unit 220 of the cryptographic modular multiplication apparatus according to an embodiment of the present invention uses the UP value from the n + 1 bit (225 bit) result value of the addition operation of the elements C and D. Consider. Herein, the UP value satisfies the expression UP = U- (2 ⁿ -t) = U + t-2 ⁿ , and is a value obtained by subtracting the n + 1 th bit value from the calculation result of the U + t value.

The modulus calculation unit 220 calculates U + t, and if the n + 1 th bit of U is '1', determines that U + t is greater than 2 ⁿ and that U> P, and n of U If the +1 th bit is '0', the result of the calculation of the U + t value is greater than U> P if the n + 1 th bit is '1', otherwise U <P.

To this end, the modulus calculator 220 of the cryptographic modular multiplication apparatus according to an embodiment of the present invention may include a U Plus T calculator 221, a controller 222, and an extractor 223.

The U Plus T operation unit 221 calculates a U + t value based on the difference UP with modulus P from the result of the addition operation of two elements (U = C + D), and the extraction unit 223 calculates the calculated U The n + 1 th bit is extracted from the + t value, and the controller 222 controls a modulus operation (U mode P) on the result of the addition operation of the two elements from the extracted n + 1 th bit.

FIG. 8 summarizes the synthesis result for the 224-bit elliptic curve cryptographic modular multiplication device according to an embodiment of the present invention, and FIG. 9 shows the simulation result.

8 and 9, according to the 224 bit elliptic curve cryptographic modular multiplication apparatus according to an embodiment of the present invention, a double modulus operation and an addition operation when the rounding numbers are '0' and '1' are each 4-bit unit. The delay time can be reduced by performing add modulus operations in parallel.

Specifically, the modular multiplying apparatus of the present invention does not generate delay compared to the conventional sequential calculation method, including a configuration of performing an addition operation in units of 4 bits. For example, in the case of sequential calculation, the delay time waiting for carry to calculate the next digit is possible because all the 223th digits must be calculated for the calculation up to the 224th digit. On the other hand, in the present invention, however, the delay time waiting for the carry value is not generated by calculating 224 bits in total 56 units by dividing into 4 bit units.

That is, according to the present invention, 56 units divided into 4 bit units are each independently performed at the same time, so that both cases with and without the number of rounds are calculated in advance, and 56 is selected to select whether the rounded number is 0 or 1. Only one operation is required, which can be more efficient than the sequential rounding calculation and can reduce latency.

10 is a flowchart illustrating a cryptographic modular multiplication method for two elements of an elliptic curve lower finite body according to an embodiment of the present invention.

In step 1010, the coefficients of the bit order for the multiplier of the two elements of the lower elliptic curve are extracted.

In operation 1020, a first double modulus operation is performed on the result of the multiplication operation on the most significant n-bit coefficient and the multiplicand extracted from the multiplier.

According to an embodiment, step 1020 divides the first double modulus operation result and the multiplication operation result into 4 bit units, respectively, and parallelly performs the first double modulus operation result in 4 bit unit and the multiplication operation result in 4 bit unit. It may be a step of performing an addition operation. For example, an add operation when rounding numbers '0' and '1' are performed on the first double modulus operation result in 4-bit unit and the multiplication operation unit in 4-bit unit to include a carry value in parallel. It may be a process of outputting a bit result.

The first double modulus operation performed in step 1030 and the first addition modulus operation are performed on the multiplication operation result of the n−1 bit coefficient and the multiplier extracted from the multiplier.

The first double modulus operation and the first addition modulus operation are sequentially performed on the lower bit coefficient and the multiplicand extracted from the multiplier based on the result of the first addition modulus operation performed in step 1040.

The method according to the embodiment may be embodied in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI &gt; or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (11)

In a modular multiplication apparatus for two elements of an elliptic curve lower finite body,
A coefficient selector for extracting coefficients for each bit order of multipliers of the two elements;
A double modulus operator configured to perform a first double modulus operation on a multiplication operation result of the most significant n-bit coefficient and the multiplicand extracted from the multiplier; And
An addition modulus operation unit configured to perform a first addition modulus operation on the first double modulus operation result and the multiplication operation result of the n-1 bit coefficient and the multiplier extracted from the multiplier
Modular multiplication device for cryptography comprising a. The method of claim 1,
The double modulus operation unit and the addition to sequentially repeat the first double modulus operation and the first addition modulus operation on the lower bit coefficient and the multiplicand extracted from the multiplier based on a result of performing the first addition modulus operation Control unit controlling the modulus operation unit
Modular multiplication device for cryptography further comprising. 3. The method of claim 2,
The double modulus calculation unit
Perform a second double modulus operation on the result of performing the first addition modulus operation;
The addition modulus calculation unit,
A cryptographic modular multiplication apparatus for performing a second double modulus operation result and a second addition modulus operation for the multiplication operation result for n-2 bit coefficients and multiplicands. The method of claim 1,
The addition modulus calculation unit
Dividing the first double modulus operation result and the multiplication operation result into 4 bit units and performing an addition operation in parallel on the first double modulus operation result in 4 bit units and the multiplication operation result in 4 bit units. A modular modular multiplication device for characterization. 5. The method of claim 4,
The addition modulus calculation unit,
A 5-bit result including a carry value is output by performing an add operation when the rounding number is '0' and '1' in parallel to the first double modulus operation result in 4-bit unit and multiplication operation in 4-bit unit. One or more 4-bit adders
Modular multiplication device for cryptography comprising a. The method of claim 5,
Each of the one or more 4-bit adders,
A first result output unit configured to perform an addition operation when the rounding number is '0';
A second result output unit configured to perform an addition operation when the rounding number is '1'; And
A multiplexer that receives a 1-bit carry bit output from a lower unit 4-bit adder and selects one of an execution result value of the first result output unit and the second result output unit based on the received carry bit.
Modular multiplication device for cryptography further comprising. In the cryptographic modular multiplication method for two elements of an elliptic curve lower finite field,
Extracting a bit order coefficient for a multiplier of the two elements;
Performing a first double modulus operation on the result of the multiplication operation on the most significant n-bit coefficient and the multiplicand extracted from the multiplier; And
Performing a first addition modulus operation on the result of the first double modulus operation performed and the multiplication operation result on the n-1 bit coefficient and the multiplier extracted from the multiplier;
Modular multiplication method for cryptography comprising a. The method of claim 7, wherein
Controlling to sequentially repeat the first double modulus operation and the first addition modulus operation on the lower bit coefficient and the multiplicand extracted from the multiplier based on the result of performing the first addition modulus operation.
Modular multiplication method for cryptography comprising a. The method of claim 7, wherein
The step of performing a first double modulus operation,
Dividing the first double modulus operation result and the multiplication operation result in units of 4 bits, and performing an addition operation in parallel on the first double modulus operation result in units of 4 bits and the multiplication operation result in units of 4 bits
Modular multiplication method for cryptography comprising a. 10. The method of claim 9,
The step of performing an addition operation in parallel,
A 5-bit result including a carry value is output by performing an add operation when the rounding number is '0' and '1' in parallel to the first double modulus operation result in 4-bit unit and multiplication operation in 4-bit unit. Steps to
Modular multiplication method for cryptography comprising a. A computer-readable recording medium having recorded thereon a program for performing the method of claim 7.

Images